OH NO!
I HAVE TO DESIGN A PA
Pete Zampardi
CS Mantech
May 2013
Circuit Design Is Complicated
- All Problems Should be Blamed on the Transistor Model or Process
Technology Guy:
Do You Really Know What
All This is Doing?
Design Guy:
The Problem is
Obviously Here…
Outline
• I’ve just been asked to design a handset PA, now what?
• What type of PA do they want? When do they want it? What Market?
• Type of PA determines die complexity and process(or material) selection.
• When they want it may determine process technology and approach.
Architecture is decided by specifications.
• Linear (bias usually included on chip, though this is changing)
 SEAL PA (HELP, etc – switch for different power levels)
 ABC PA (Analog bias control) – smart biasing for
different powers
• Saturated (usually PA – multiband) with CMOS or all CMOS.
• FEM – What does it have to include? Switch, duplexer, controller
• Multi-mode (combines different types) How many bands? Interface?
• The market (low cost, smart phone) for also has impact on technology
selection.
• What else do they want in the module (we won’t address, but switch selection,
filters, etc come into play here)
Outline II
• How Do I Do Design Once I’ve Settled?
• Simulation environment/design kit
• Simulators (Cadence/ADS). ADS primarily used for PA design
• EM (electro-magnetic) Simulators to simulate “passive devices” and matching
structures
• Momentum for on-wafer and laminate
• HFSS if you get really serious and need to worry about bond wires etc. (HFSS if
structure cannot be accurately modeled with 2D description)
• Models – the link from simulator to process
• Simulation says it will work, now what?
• Layout
• Active Devices
• p-cells and design rules
• Passive devices and interconnects
• Simulate AGAIN! Things like MIM caps, Inductors, etc depend on what’s
around them so need EM simulation of real layout!
• Packaging and other stuff…
Outline III
• My Simulation and Layout are done, now what?
• LVS: Layout vs. schematic check
• Make sure that what you designed/drew is what you simulated
• Design for manufacturing time!
• Statistical simulation of PA die to account for manufacturing process
variation.
• Stuffs gonna vary, you need to make sure the PA will yield.
• Adjust circuit elements to make them vary less with the process.
• Statistical Simulation of Packaging
• Thermal Considerations
• Tape-Out!
• Testing
• Bench
• Characterization
• Production test (sub-set of characterization tests)
• Probe test
• Final RF test
What Are We Building???
Basics of PA
(Courtesy: Nick Cheng, CSICS 2011)
Multi-Stage
Type of PAs
 Here we just talk about “broad” categories. Can have combinations too!
 Cellular PA (for simple handset)
– Linear (TDMA, WCDMA(3G), LTE(4G))
• As you expect, has a linearity requirement and less stringent ruggedness requirements than
saturated PA (GSM). Has other requirements like mid-power efficiency, etc.
– GSM (2G)/EDGE (2.5G)
• GSM is saturated, no linearity requirement. Same chain is also used for linear. CMOS controller
usually used. EDGE is linear. Usually re-uses the PA chain
 Multi-mode, Multi-band (MMMB)
– Some combination of above!
 WLAN
– Primarily data, higher frequency, lower output power (sometimes)
– Has linearity requirements that are stringent.
Market?
 The PA market has generally fragmented to “Low-Cost” and “Premium” segments
 For low-cost, cost is primary factor. PA specs are typically not as stringent (although
this is changing a little). Not really fancy and silicon (CMOS) actually plays okay in this
space.
 For Premium (mostly Smart Phones), performance is key. GaAs HBT (BiHEMT or
BiFET) is still dominant technology here.
Leveraging Silicon and Compound Semiconductor
Attribute
Silicon
√
Cost
Enablement
High voltage handling
Thermal conductivity (heat dissipation)
Support
√
√
Electrical conductivity (performance of
passives)
Mechanical strength
√
Ability to integrate features
√
NRE Cost ($$/maskset)
Unit cost (cents/mm2)
III-V
√
√
√
Fab cycle time
Fab capacity
√
√
Fab automation (process consistency)
√
√
Model, PDK Methodology
√
√
Both Silicon and GaAs are Essential for Device Leadership
Technology Trends Summarized
• Architectural Leverage of CMOS, GaAs and Advanced
Interconnect are all required to achieve optimum cost /
performance
• We can deliver future solutions that will allow:
• High Volume feature phones to have better RF connectivity than
today’s high-end Smartphones
• Embedded Wireless Broadband solutions that enable gigabit
speeds
• Some Illustrations of next steps in the above follow:
• Multimode-Multiband Solutions to Enable Smaller, Low-Cost
Smartphones
• Increasing Use of Signal Conditioning and Improvements needed
for High speed Wireless Data
Multimode RF Solutions
An Illustration of Size & Performance
Performance
Size
Discrete
Antenna
Switch
~
~
~
Multimode
Hybrid
Band/Mode
Switch
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~
~
Antenna
Switch
Best Performance
Flexible, Smaller
Band/Mode
Switch
~
~
~
~
~
~ ~
~
~
Antenna
Switch
Lowest Cost & Size
Integrated MMMB RF Solutions Will Reduce Size and Power
Specs & Requirements
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Frequency – must operate across a band, not single point
Collector Voltage – a range (0.5 (low power) to 6)
Bias Supply Voltage – a range (also low current draw)
Output Power Minimum (-50) to Maximum (27, 29, 34 dBm)
Power Gain (26 to 28 dBm)
Gain Variation over Temp (-1 dB to 1 dB)
ACP (1st and 2nd) and ACP under mismatch
DC/DC Compatibility
MSL Level
ESD Robust
Max Current
Receive Band Noise
Research Papers Typically Only Report
Harmonics
Stuff in RED and they usually quote ACP
Leakage Currents
to the SYSTEM spec, not PA SPEC
Switching Time
Stability, Control Slope
Pad configuration
Many specifications besides Gain,
PAE, and Linearity
Not everything looks as good on
Wafer as it does on paper!
Examples of PA Parameters
Gain for Different Tuning Conditions
PAE for Different Tuning Conditions
100
10
5
PAE =
80
15
PAE (%)
Transducer Gain (dB)
20
Gain (Pout/Pavail)
60
40
20
0
-20 -16 -12 -8
-4
0
4
8
0
-20 -16 -12 -8 -4 0 4 8 12 16 20
Available Input Power (dBm)
12 16 20
Available Input Power (dBm)
Ref Lvl
-23.8 dBm
Ave DC Current (A)
Ave. DC Current for Different Tuning Conditions
0.4
0.3
Pout − PAvail
PDC
Collector
Current
0.2
Marker 1 [T1]
-29.45 dBm
899.71543086 MHz
RBW
VBW
SWT
30 kHz
300 kHz
500 ms
RF Att
Mixer
Unit
10 dB
-20 dBm
dBm
-23.8
1
1 [T1]
-29.45
899.71543086
CH PWR
-15.00
ACP Up
-50.20
ACP Low
-49.57
ALT1 Up
-63.25
ALT1 Low
-62.50
-30
-40
-50
dBm A
MHz LN
dBm
dB
dB
dB
dB
1RM
-60
-70
EXT
-80
0.1
-90
ACPR=
Power in Main Channel/Power in Sideband
cu2
cu2
0.0
-20 -16 -12 -8 -4 0 4 8 12 16 20
Available Input Power (dBm)
-100
cu1
cu1
C0
C0
-110
cl1
cl1
cl2
-120 cl2
-123
Center 900 MHz
Date:
26.APR.2004
400 kHz/
18:30:54
From Marcel Tutt: Microwave Measurements and Their Uses
Span 4 MHz
Logic and Control Interface (Silicon Coming into Linear)
• Systems supporting Penta-Band WCDMA and Quad- Band GSM/EDGE
need 8 discrete control lines!
– 7 RF paths 3 bits for I/O switch control
– 21 operating modes  5 bits for PA mode control
• More standards/bands/modes  more control lines
– Creates routing challenges at the board level
– PA modules become I/O limited at the package level
• Standardized serial bus interface, i.e. MIPI, significantly reduces control
interface I/O requirements  3 discrete control lines
- VIO, DATA, CLOCK for MIPI
Package Integration Path
On Package
Matching
Component
Detector ICs
Switch
GaAs/SOI
Component
Passive IC
PA for Different Bands
In GaAs
Bias Control IC
In Silicon
Bond Wires
Via in Laminate
PA die is not the only thing in there (percentage cost)
Lots of Trade-offs
Real-Life Front-End Module (FEM)
HINT: NOT MADE OF DISCRETES
WCDMA Usually
Combine These
On-chip
Power Amp IC
Control/Logic IC
Simulation: DC, Trans.,
S-par
and HB
Layout: GDSII
Simulation: DC, Trans.,
S-par and HB
Layout: GDSII
Glasbrener
Breaking EDA Barriers
RFIC Panel 2002
Power Amp Product
Simulation: DC, Trans. S-par
and HB
EM Simulation
Layout: Gerber
Components
SMT, Filter, etc
Substrate and Assembly
Each Piece Has It’s Own Challenges
•
•
•
Components (Simple Small Signal Models Okay)
• Fit for Design Flow:
• Tunable for Optimization
• Sensitivity Analysis for Tolerance Selection
• Fixed Predefined Sizes
Components
• NO Double-Counting
Substrate (Feature Size Determined by Customer/Product Needs)
• EM Simulate as Soon and Much as Possible
• Variation is Important (Weed Out Bad Layouts)
•
Design Issue
• Need to Run DRC and LVS on Substrates
Substrate
ICs (Controller and PA)
• DC, Time Domain, Small Signal S-parameter and Possibly HB/Env sims
• Design Library Supported by Foundry/Fab
• EM Sim. for on Chip Passives (Inductors, MIM Caps, Bad wiring)
•
Design Issue
• Need to Run DRC and LVS on ICs
•
Challenges for Controller
• Predictable Interface with PA for Co-Simulation/Co-Development
Control/Logic IC Power Amp
•
Challenges for PA
• Models Need to Work in DC, Small Signal, and Large Signal with Correct DC Predictions Under Large
Signal
• Need to Simulate with Everything Else Substrate, Logic/Control and Components
• Let’s Not Even Talk about Diplexer’s Filters, etc…
IC
WCDMA/Multi-Mode Considerations
Challenge: AM&S Approach Needed for Most Circuitry
• Control Circuitry is ON-CHIP!
•
What the PA Must do Now is Complicated
• Power Level Switching/Control
• No Vref Bias Circuits
• Simple Switch Control
Power
Power
Transistors
Transistors
• Barrie Gilbert “RF design is 30% RF, 70% Bias Circuit”
•
Analog-mixed Signal Modeling Methodology Must be Applied
• Fully Scalable Device Models (for Optimization)
• Statistical Simulations (Physically Based is Better)
• For High Volume Commercial Products, Yield Matters!
•
Statistics for Laminate Variations are Important (Not Just the Die)
Most of the Chip is
NOT Power Transistors
PA Die are More than “Just Two Transistors”
 Carriers/Phone manufacturers
are benchmarking phones for
linear applications at 16 dBm or
“mid-power”
– GaAs HBT/BiFET enables bypass switch or parallel stage
design
– Si also good for this
 This is being addressed several
different ways
 This may move (lower) in the
future
Probability
Mid-Power Efficiency
5.0%
4.5%
4.0%
3.5%
3.0%
2.5%
2.0%
1.5%
1.0%
0.5%
0.0%
16 dBm
-20
-10
0
10
20
Pout, dBm
Urban PDF
•
•
Suburban PDF
CDMA Development Group
– Urban & Suburban Output Power
Statistics
Application to Power Amplifier
– 5dB offset for worst case PCS
losses between PA and antenna
– 90% Operation 10dB to 17dB
Below Rated Power
– Low Power Efficiency
Enhancement Statistically
Significant
30
More Recently – III-V BiFET/BiHEMT
B
E
B
C
C
D
GaAs HBT
BiFET
-Analog FET added for bias & LF switch
45
PAE
-10
-20
Gain
25
-30
20
ACP1
15
ACP (dBc)
Gain (dB)/PAE (%)
35
30
-40
10
-50
ACP2
5
0
-60
2.2
2.4
2.6
2.8
3
pHEMT
BiHEMT
- FET added for switching and bias
0
40
G
3.2
Vref (V)
Address Bias and Mid-Power Efficiency
S
Si(Ge) vs. GaAs Status
•
•
•
•
Si(Ge) is rugged enough for linear applications
Si(Ge) performance is adequate for linear 900 MHz operation
Si(Ge) performance at 900 MHz for GSM not quite as good as GaAs
Si(Ge) higher frequency performance insufficient for 1.9 GHz linear or
saturated applications (for linear the gain is too low, for saturated the
PAE is not nearly as good)
• Si(Ge) is fine for some other “PA” applications like WLAN
• Really don’t need the (Ge) for the most part if you use HB device
Si(Ge) Currently Does Not Have Market Traction
for Handset PAs
BUT! Can TSV help RF Gain (not so much)?, Good Low Voltage
Operation (not at high current), and Functionality Still Make People Ask!
Si(Ge) Bipolar PA Examples
Philips – “Smart
Technology Mix” 2003
ATMEL TST0912
(1999)
SE2546, 1.24 x 0.94mm
SiGe Semiconductor – 2.4GHz PA
Ericsson PBA 316 03 (2002)?
Ericsson/IBM 2002
HA31010 SiGe dual-band WiFi PAM: 4x4mm
Si(Ge) DOES Have Market Traction for WLAN PAs
Moore Integration Dilemma’s
(or Sometimes Moore is Less)
Schlovin & del Alamo
Uses Latest Generation
Being
CMOS ($$$$)
Sucked into
For Chip-Size
Baseband
SOI
Or
SOS
Breakdown &
RF Performance
Degrade with
Node
Technology Node:
0.13 um
2.8mmx1.5mm
RF Performance Gets Worse AND
Mask Cost Increases Dramatically
(RF Does Not Scale Like Digital)
130-65 nm
65 nm
45 nm
Okay, I’ve Selected Technology, Time to Design…
How Do I Do Design Once I’ve Settled?
• The most popular PA design flow (for commercial handset PA is Agilent
Design System (ADS) “front-end” and Cadence “back-end” where frontend is the circuit simulation and “back-end” is the layout and checking of
the chip.
• Besides the chips themselves, the package (laminate) also is used for
output match and needs to be simulated.
• The simulation phase is usually done with NO KNOWLEDGE of the
layout, it is the point at which architecture is being defined. Many
pieces are unknown, but can be guessed at from previous designs.
(W)CDMA PA/FEM Product Development Flow
Challenge: For RF LAYOUTS Matter!
Simulate Stuff
You Didn’t Know
Earlier (Passives)
Don’t Know Layout or off-chip stuff
Understand Critical Blocks
With Estimated Tolerance to Parasitics
Feasibility
Study
Provide Tools
For 1st Order
Best Guess of
Things You Will
Layout
(Inductors/Caps)
Know Variations
Scalable
Device
Models
(Partial)
Building Block
IC Design
Extend
Simulation
MCM_RF
IC Layout Parasitic
Initial Simulation
Schematic
Connectivity/
DC/Functionality
Layout
Module Design
(Layout)
IC Design
Layout
Best Guess
At Bond Wires
Co-Simulation
IC+Module
EM Simulation
CoSimulation
For Production,
Statistical
Simulation
Over Die Process
And
Package Variation
Design for
Manufacturing
“Device” Compact Models
Challenge: Curve Fitting is Appealing to Non-Physicists
• Compact Models Provided (at Schematic Phase) for:
• Transistors
• HBTs (for Logic and for Power Chain).
• MESFETs (for Logic and Switching Functions).
• Diodes (Used in Logic Circuits and ESD)
• Resistors (Precision Thin-film and Semiconductor)
• Inductors (Inductor Tool Provided to Help Selection, EM Sim Later)
• Simulation Based on Method of Line, Momentum and S-parameters
Pulled in
• Capacitors (Tool Provided for Selection, EM Sim Later)
• SMTs and Wirebonds (Part specific models and EM Sim Later)
Compact Models are Required for Bias Circuit
Design and for Power Device Optimization
Provides an Easy Path for Statistical Simulation
So What Does This Mean for Mantech Community?
• The devices (not just transistors, but caps, resistors, inductors) depend
on manufacturing.
• Front-End Devices (here we mean stuff in the semiconductor):
Transistors, Diodes, and Semiconductor resistors behavior depends on
the starting material and the fabrication process.
• Back-End Devices (MIM caps, thin-film resistors, inductors, etc) depend
primarily on process and are just as important for circuit yield and
function as the active devices.
• Device Designers and Modelers need to know what is really on the
wafer not what is thought to be on the wafer!
• If these things change, and the models don’t reflect them, designers
become “unhappy” (Different=BAD)
During “Simulations Phase” Designers Make Some
Choices
Designs using “ideal components” will never resemble reality!
• Should already know what they are designing and what the technology needed for it is
(topology is selected already, including type of bias design)
• Within the technology, they now want to select from a palette of devices to make their
circuit. These are the front end devices.
•
•
•
•
•
•
•
HBTs – different HBTs can be used for different purposes – there are trade-offs. Scalability is a
good approach to provide designers with the right tool for the job.
FETs – the requirements on the FET depends on how it is used. For bias circuit, FET above
Emitter is okay. For higher frequency/power switching, the FET must be under the HBT.
Diodes (can be BE, BC, or Schottky) are also used for different purposes and should be
scalable. The use is from bias circuit to logic to ESD/ruggedness protection.
Resistors can be semiconductor or thin-film. There are pro’s and con’s to each and this should
be communicated to designers by letting them know the tolerance (sheet resistance and due to
geometry variations from fab) as well as the temperature coefficients.
MIM capacitors are important for matching in the circuit. The variation is very important to
communicate to designers. The variation can differ by type, film thickness, and layout
Inductors are fabricated from the metallization layers. Variation in the metal resistance,
geometry, and inter-level dielectric spacings can be important.
Bondpads – bond pads actually count as a device, but usually not important until layout phase
Variation of Device Features Is Important To Know
Ledge
CC
EC Effects Contact Resistance (Emitter)
EM Determines Emitter Size (current density), Emitter Resistance, and is Part of Ledge Definition
BC Part of Base Contact Resistance and Ledge Formation. BC to BP spacing also important for offset
BP Determines Cbc of Device and Defines Part of Passivation Ledge
CC Part of Collector Resistance and Also Defines Part of Cbc (especially reverse bias)
AA Device Isolation (contributes some overlap capacitance)
ALMOST ALL IMPORTANT PARAMETERS SCALE WITH AREA!
Two-Stage Design Considerations
Vi(t)
Predistorter
S1
Vx(t)
Vo(t)
Linearized
System
=
S2
Vo(t)
Vo(t)
Vi(t)
Vi(t)
Vo(t)
Vx(t)
Vx(t)
Vi(t)
Stage
System
Add
Predistorter
Linearize
FirstSingle
Stage
of PA –ISNon-linear
atoPredistorter!
• Efficiency and Linearity “Compromise” Takes on a
Different Meaning Once We Realize This
After Lavrador IEEE Microwave Magazine, August 2010
Geometry Types – Different Transistors
for Different Purposes!
Straight Finger
Nb>Ne
(BEBEBEBEB)
Ne>Nb
Round Devices
Ne=Nb
Horseshoe
CBE
(EBE)
CEB
(EBEBEBE)
(½E)BEBEB(½E)
Device
QSM
QSM
Dot
Ring
Description
M1+BC base finger
M1 only on emitter connection
QSB
QSB
BC base finger (extra Cbc)
Narrower BC=lower Cbc
M1/M2 on emitter
QSB_ALT
1 Base, 2 Emitter version of QSB
QSF
1 Base, 2 Emitter
M1/M2 on emitter (at certain width)
QSF
QS
QS
1B, 1E, 1C, M1 only on E
QR
True-ring emitter HBT
QRH
Horse-shoe (ring) emitter HBT
QD
Dot emitter HBT
Only Practically Supportable with Scalable Model
Transistor Sizing
• Depends on:
• Required Output Power
• Reliability Limits (Thermal, Electrical)
• Performance Requirements
• Loss of Stuff After the PA!!!
Current Density vs. Output Array Area
0.4
0.35
Current Density (mA/um2)
0.3
0.25
WCDMA
0.2
PCS
GSM
0.15
0.1
0.05
0
0
2000
4000
6000
Output Array Emitter Area
8000
10000
12000
Calculation Example
•
•
•
•
•
Find Power in dBm
Convert Power to mW
Use Power Supply Voltage to convert to mA
Divide by Total Linear Efficiency
Pick Device Area to Not Violate Your Current Density Rules!
• Working backwords: Divide by device area = current density (mA/um2)
In Mike Golio’s Words:
A Bit is a Bit, a Watt is a Watt
Examples
• (GSM PA) Output Power= 36 dBm (=3.98 W), PAE=56 %, 3.5
Volts ⇒ 1.137 Amps/7680 µm2=0.26 mA/µm2
Bias Close to gain peak for GSM
• (CDMA/AMPS) Output Power=29 dBm (=0.794 W),
PAE=35%, 3 Volts ⇒ 0.667 Amps/5760 µm2=0.12 mA/µm2
Bias for good linearity for CDMA
• Fujitsu (1998), Output Power=31 dBm, (1.259 W), PAE=63.2%
Driver=8 fingers=320 (Icq=0.0625 mA/µm2), Power=48
fingers=1920 (Icq=0.052 mA/µm2), Vce=3.5 (this is a RESEARCH
paper using a “gold-sandwich” device)
For Linear PAs, Bias is set by DESIGN, not Technology
For GSM, Bias Set to Peak Gain, No Higher
Saturated PA Bias (Power Control with CMOS)
Base Current Control
Silicon Chip
•
Amplifier output power is adjusted by
means of
voltage saturation by limiting DC collector
voltage
(After Ripley, 2009
IMS)
•
•
Amplifier output power is adjusted by means of limiting DC
base current
Implemented with voltage control through moderate
impedance or high impedance current source
Bias Circuit Examples and Challenges
•
•
Current Mirror
• With applied Vref
• Problems cold
• Beta sensitive
• Bias resistor
Vref sensitive
Current Ratio, Base Current
Compensated Mirror
• Problems Cold
• Bias resistor sensitive
Iref=(Vref-Vbe)/Rref
Iref
Vbe
Vbe




 1 + VCE 2 VA 

A2
1
I2 =
I ref 
 1 + V V 
A1


1
A
BE
A 
 1 + 1 + 2  


 β
A1  






 1 + VCE 2 VA 

A
1

I 2 = 2 I ref 

+
V
V
A1
1
2


A
1
BE
A 
1+
1 + 2  
2



β + β  A1  

Figures from: Jarvenin, “Bias Circuits for GaAs,” IMS 2001, pp. 507-510
General Definition of Resistor (Any Kind!)
Lbody
Lcont
dW (∆W)
Actual
Wbody
Lbody: Resistor Length
Wbody: Resistor size
Lcont: Contact Size, Resistor size, mis-alignment
R=
2 RC
L
+ RS
(W + ∆W )
(W + ∆W )
(Rc absorbs the dL term)
Long Skinny Resistors Depend on dW
Short Fat Resistors Depend on Rc
Variation Depends on Aspect Ratio
Old Pre-BiFET Solutions (CMOS Assisted PA)
 Multiple Chip Solutions (Flexible / Added Features)
– CMOS Integrated Circuit
– 6mm x 6mm WCDMA PA
CMOS Bias IC
(From Fowler,
RFIC 2002)
Bandgap
Voltage
Reference
Combinational Logic
Stage-1 Bias
Input
Matching
Circuit
Stage-1
Analog
Control
Circuit
Stage-2 Bias
Inter-stage
Matching
Circuit
Stage-2
Output
Matching
Circuit
2-Stage GaAs PA MMIC
50Ω Matched Power Amplifier Multi-Chip Module
Multi-Mode is Pushing Things Back This
Way to Include Digital Interface
Packaging and Output Match
 Okay, so now all the “chip” level stuff is decided. For PAs, the packaging (matching
network) is also part of the design!
 The packaging (we won’t go into great detail) involves knowing the assembly accuracy,
bond-wires (shapes, etc since they are inductors), and SMD components (values and
tolerance).
 There is some give and take on the array size to accommodate other specs and getting
the matching right.
 Once all this is in place, things are optimized to meet a given performance specification.
At least on paper 
Once You Have Simulation Done, It’s Layout Time!
 Once the simulations (in this case, just baseline, no statistics) are completed, that
schematic must be translated into the technologies (semiconductor and package). The
package size is usually known before even simulation is done.
 The layout is not always done by an electrical engineer (how things are routed matters
ELECTRICALLY). Some layout engineers are TOO creative.
 The exercise of laying out the chip is the same as trying to put 10 lbs of manure into a 5
lb bag. Improper layout generally results in a larger die which impacts fab utilization.
 This is where many of the design rules, especially spacing rules, via sizes, etc, become
important and impact die size. Bond pad size reduction (if the probe guy doesn’t kill
you) becomes important here if the design is bondpad size limited (even if it’s not
smaller pads shrink the die foot-print dimensions some).
Not a Good Time to Color Outside the Lines!
Okay, I think My Layout is Done, Now What
DRC (Design Rule Check)
 DRC, or Design Rule Check is run after layout (it’s usually a good idea to DRC blocks
as you are doing it if you are doing larger circuits).
 This check is meant to make sure that whatever got drawn is manufacturable in the fab.
It does not, by itself assure that yield will be good or that some problems won’t be
created. Again, good layout helps.
 This is generally where fab engineers first see the designs!
 Why is DRC not enough?
– Bad layout practices can change the electrical performance by adding unwanted
resistance, inductance, or capacitance. Good designers actually look at the layouts and
include important parasitic elements from the layout into the simulation to see if they are
impacting performance. Good designers also do EM simulation at this point to see if there
are any issues.
– Sometimes one of those creative guys finds a way to lay things out differently than anyone
before him that leads to yield failures 
Design Kit - DRC
BP
EM
Emitter
Contact
Base
Contact
Emitter
BC
Base
Contact
Base
Collector
Collector
Contact
• Physical Structure
Sub - Collector
Semi Insulating Substrate
-
• Design Rules – Process Capability
Intent, Implementation, Verification, and Release
• Width Rule
EC.W
– Min Width of Emitter Contact
• Enclosure Rule
EM.E.EC – Min Enclosure of Emitter Contact by Emitter Mesa
• Spacing Rule
BC.S.EM – Min Space of Base Contact to Emitter Mesa
Meaningful Design Rule Names – Easier Comprehension by Designers
Isolation
Passing DRC DOES NOT MEAN IT IS A GOOD
LAYOUT!
 DRC rules are supposed to represent fab capability.
– Either developed using test masks or from historical products
• Test masks not usually statistical, may not test all topologies
 Designers are VERY good at exposing “weak points” in the process.
 Following certain “rules” for good manufacturability can help
 Rules should be changed in a controlled manner, not “sprung” on design teams at last
minute
 You cannot possible check everything that’s ever gone wrong because of fab events
Yield Enhancement Layout
1. Make layouts as small as possible.
Smaller layouts have just as good yield as big ones, and you can fit more on a wafer. Use minimum design rules when it makes your layout
smaller.
2. Allow greater than minimum spaces if possible.
When it does not grow the layout beyond the available space, move elements as far apart as possible. If the layout is wiring limited, spread out the
devices, and vice versa. If you have white space, use it!
3. Even out the wiring.
Within a layer, spread out the wires, and balance the wiring between levels. Avoid a very dense level matched with a very sparse level.
4. Avoid shorts.
Wiring shorts are a more likely problem than opens, so when space is tight widen the spacing rather than the wire width. Also, avoid coincident
edges of unconnected metals since the topology may result in shorts.
5. Avoid opens.
Most opens occur at contacts or vias, so use redundant vias!
6. Do not add unnecessary wiring.
Without a specific electro migration or performance requirement, avoid redundant wires or fattening existing wires. If you find a better way to hook
up a node, delete the old one. Resistance of local wiring is normally negligible compared to device conductance (for FETs).
7. Allow Extra Overplots (extensions) where possible
For M1-M2 vias and M1 over via if other design rules allow, make the M1 or M2 bigger than the minimum via overlap. This will provide some
protection against via etch blow-out. Also, move vias away from edges (center them) if possible.
8. Avoid Small Slivers, notches, or donuts in metallization.
Avoid having small protrusions of metal or “notches” since these have problems lifting off and can reduce yield. Also, avoid enclosed shapes in
metallization since they may not lift (even very large enclosed openings may present problems!).
Layout Close to Finalized
– Electromagnetic (EM) Simulations
 Since we want to be like “good” designers, let’s look at what get’s fed into EM
simulation and how that is impacted by process.
 The first thing is the “EM stack” a definition that goes into the tool based on the
information on metal thicknesses and dielectric thicknesses in the processes. For nonplanar processes, this can be tricky since the thicknesses may change with feature
size! This information comes from the fab and may or may not be routinely monitored
(on actually processed wafers not test wafers). This applies to laminates too.
 The second thing that becomes important is the GEOMETRY of the metals: drawn
width vs. realized width, alignment to layers below, etc. For laminates, even though the
features are much grosser than wafer, it is important too!
What the EM Simulator Thinks the Back-End Looks Like
Top Coat
Scratch Protection
Metal 3
Interlevel Dielectric 2
V2 (Via)
Metal 2
Interlevel Dielectric 1
V1 (Via)
MIM Layer
NV (Via)
Metal 1
GaAs
Need Thicknesses, Dielectric Constants, and Sheet Resistances
What Back-End REALLY Looks Like
Variation of “Back-End” Devices – MIM,
Inductors, etc is Also Important
Tough to Simulate When Far from “Ideal”
Design Kit – Passive Device
• Use of EM in Modeling
• Passive Structure Described with
pCell is Known a Priori
• Layer Stack is Known
• Terminal Definitions are Known
It is possible!
• How ?
•
•
•
•
Extract Geometry Information
Predefined Layer Structure
Defined the Freq Range from DC to 3Fo
Launch EM Behind Scene if Necessary
(No Re-calculation if no Changes Were Made.)
• Resulting s-param File Included in Circuit Sim.
Process Variations Can be Simulated as Well.
Circuit: Inductors – Neighbors Matter, Don Not Know
Layout On-Chip Inductor Tool Customized in ADS
Select
inductor type,
frequency
Enter TW,
S, N, ID
Calculato
r outputs
L,Q, etc.
Specify
required L,
Q, layout
area
Press ‘Select’
to place
instance in
schematic
Selector Mode
Calculator Mode
Kwok, Mantech 2008
Parasitics and Array Simulation
(Teaching Designers to Fish)
Simple Multiplicity
Factor
Pro: Fast/Simple
Con: Phase Error
>8GHz
Transmission Line:
Pro: Moderate Speed, Scalable,
Easy
Con: Accurate Up to 12GHz
EM Simulation Reduced Number of HBTs or All HBTs
Pro: Easy to Do, No Modeler Required
Con: Simulation Speed Bogs Down with Increased
Transistor Count
Lumped Element
Pro: Fast
Con: Layout Specific, Hard to
Scale
Load-Pull Power Sweep with Different EM
Approaches
Gain Comparison
Pout Comparison
22
30
20
25
Pout, meas
Gain, meas
Gain, EM-1HBT
Gain, EM-2HBT
Gain, EM-3HBT
16
Gain,EM--12HBT
Gain, Simple_M
14
Gain, TLM
Pout, EM-1HBT
20
Pout (dBm)
Gain (dB)
18
Pout, EM-2HBT
Pout, EM-3HBT
15
Pout,EM-12HBT
Pout, Simple_M
10
Pout, TLM
Gain, Lumped
Pout, Lumped
5
12
0
10
-15
-10
-5
0
5
10
-15
15
-10
-5
0
5
10
15
Pin (dBm)
Pin (dBm)
• On-wafer LP measurement at
freq=1.9GHz, Vc=3.4V, Ic=14.6mA
Ic Comparison
200
180
Ic (mA)
160
Ic(mA), meas
140
Ic(mA), EM-1HBT
120
Ic(mA), EM-2HBT
Ic(mA), EM-3HBT
100
Ic(mA),EM-12HBT
80
Ic(mA),simple_M
60
Ic(mA), TLM
Ic(mA), Lumped
40
20
0
-15
-10
-5
0
Pin (dBm)
5
10
15
No Huge Differences
EM Slightly Better
No Impact on Circuit Level Simulation
EM (Match and Ground)
Challenge: Where is Ground?
+45 degree
phase
Y1
Vcc
Y2
DC
Feed
DC
Feed
DC
Feed
Input
matching
Vcc
DC Feed
and
Harmonics
tuning
Inter stage
matching
-45 degree
phase
Power
Combiner
DC Block
RF IN
-45 degree
phase
Bias circuit
1st stage
Input
matching
Inter stage
matching
DC Feed
and
Harmonics
tuning
+45 degree
phase
Bias circuit
2nd stage
Vcc
Vcc
Vref Y1 Vref Y2
DC
Feed
DC
Feed
DC
Feed
Y1
Vcc
Y2
Why BSV (backside via) is important
More important as frequency increases too!
W. Sun, Workshop WSO, 2012 International Microwave Symposium
V=0; I=0
Defined in circuit Sim (static equation)
One single node in circuit
Infinite current sink
No current between two tied nodes
(no inductive/resistive loss)
Re-simulate! and LVS (Layout vs. Schematic)
 With the EM blocks done, now everything gets re-simulated to make sure stuff is okay.
 While doing DRC, the other thing that can be done concurrently (and should be in-case
something get’s accidentally moved while fixing stuff) is LVS, or Layout versus
Schematic.
 LVS compares the simulation information to the on-wafer information to make sure you
are building what you simulated.
– Checks connections of circuit elements to make sure it’s wired how you want.
– This is where checks of device type, area, and value can be performed.
– This is generally restricted to die level, but sometime expanded to product level
 Smiley Face…
 With simulation done, layout done, design rule checked, and layout vs. schematic
verified, it’s time to fab some wafers!
Design Kit – LVS
• Applications – Layout vs Schematic (LVS)
BP
EM
• LVS Procedure
• Extraction of Netlist from Layout
Base
Contact
Emitter
Contact
Emitter
BC
Base
Contact
• Device Recognition Based on
Collector
Physical Layers
• Device Properties Drawn from
Sub-Collector
Semi-Insulating Substrate
Physical Processed and/or Derived Layers
Only Exception: Inductive Devices (Same as Interconnect Physically)
Base
• Netlist from Schematic – Created from Physical Devices, with Handling of Probe
Component Behavior Considered (E.g., Voltage source Open, Current Probe Short,
etc.)
• Comparison of Extracted Netlist from Layout and Netlist from Schematic
Myth: LVS depends on pCell – NO! LVS do NOT depends on pCell at All!
Most Immature Features in Kit for
Compound Semiconductor Technologies
Collector
Contact
Design Kit –Layout Parasitic Extraction and LVS
(Full Chip EM ≠ LPE (Layout Parasitic Extraction)
• Parasitic Extraction
Equivalent Circuit Models of Interconnect
NOT Included in Device Model – Appropriate
for Broadband Application (Time Domain Sim)
• Considerations
• Device Model Boundary to Eliminate
Double Counting of Physical Effects
• Proven for RC, Inductance and Mutual a Real Challenge
• EM Engine with Proper Design Hierarchy and Frequency Range
• LVS – a Prerequisite for Parasite Extraction
Binding the Extraction Results (Equivalent Circuit or S-Parameter) with
Original Circuit
IC Level Schematic
With Simple SMT
Physical Verification OK
LVS
Post Layout
Extraction
Physical Design
With or w/o Connectivity
Time Domain CktSim
Freq Domain Sim
Modeling/Design Philosophy
What are the Expectations?
 Goal of Modeling (for PA) is to Get Designer on the Green
– Compact Models are the Drivers, Irons, and Wedges
– Correlation of Lab and Simulation Benches is Like “reading the green”
– Not as Trivial as Small-signal or Low-frequency Simulations
 Modeling VARIATION of the Process is More Important than Modeling a “Hero Device”
– Variation is Important for Yield and System Performance
– Nominal-ness of Measured Part not Obvious Early on
 There is a LOT More Than Just the Active Device
Model That Can Account for Differences
Goal of Simulation is to Get Close as
Fast as Possible, Predict Trends
HBT Circuit Simulation – Parameter Selection
Analysis Summary of Parameters and their Effects
Device
parameters
Impacted Model
Parameters
Observations
Vbe
Is, Ibei, Iben
Controls turn-on voltage and shift both Ic
and Ib
β
Ibei, Iben
Controls Ib, Rb and changes DC current
gain
Re
Re
Rb
Rbi, Rbx
Highly correlated to β, affects RF power
gain
Rc
Rci, Rcx
Rci is insignificant, Rcx is correlated to
Rcsh
fT
Tf
Tracks transit time, depends slightly on
base and strongly on collector design
Cbe, Cbc
Cje, Me, Pe, Cjc, Cjen, Mc,
Pc
Affect total transit time, impedance and
RF gain.
Tracks emitter resistance, affects Gm and
RF gain
HBT Model Development – Parameter Selection
Selection Criteria – Model Parameters
• Parameters that affect most of device/circuit performance
•
•
•
•
•
DC gain β (Ic/Ib)
Turn-on voltage Vbe
Series resistances Re, Rb, Rc
Junction capacitances Cje, Cjc
Transit time Tf
• Data available in database from process control measurements
• Leverage existing data for fast model development instead of years of
data collection.
• Parameter set must be device-physics compliant and should be
physically non-correlated.
Factor Selection - HBT
• Base Thickness (BT)
• Impacts DC Gain (β), Small-Signal (fT and fMAX), and Base Resistance
(Rbsh)
• Base Doping (BD)
• Impacts DC Gain (β), Small-Signal (fT and fMAX), and Base Resistance
(Rbsh)
• Collector Thickness (CT)
• Impacts Cbc(reverse), Breakdown Voltage, and Small-Signal Performance
(fT and fMAX)
Base thickness and doping occur as product
(Gummel Number) in β and
Rbsh and impact many device parameters
Collector thickness is supposed to interact with β for
ruggedness and impacts a number of device parameters
Package Variation (Output Match)
Laminate DOE Simulation Tool
• Batch Based Momentum Simulations on DOE
states to capture the laminate process
variations:
•
•
•
•
Layer over Layer Misalignment
Geometry Size Variations
Dielectric and Layer Thickness Variations
Can Also Be Applied at Die Level
• After Completion of the Batch Based
simulation, a Symbol is Generated to Enable
the Passive Block, with DOE Analysis Results,
to Simulator with Other Blocks at the Circuit
Level
• Pareto charts in ADS Data Display is created
once the circuit level DOE analysis is
complete.
Portion of
Output Match
Symbol
in ADS
schematic
Seven
laminate
related
variables are
defined for
DOE
analysis
Automated Electromagnetic Corner Analysis
Laminate Variation
Laminate Variations are Also Important
For Electrical Parameter Variation!
+/-5% From Laminate Only!!!
Automated Electromagnetic Corner Analysis
Pareto Chart Shows Which Parameter(s) Are Most Sensitive
PAE
ACPR
After World Record Turn Around Time, Your
Wafers Are back! It’s Tune-Time!
 The designer has the wafers, the laminates, and all the other external components. These are
assembled and tested.
 The testing at this point in time is generally more detailed than dispositioning product
(characterization). Tested over Power-Voltage-Temperature (PVT). Have to meet spec from low
power to rated power, specified voltage range (battery minimum to charger), and -35 to 85C.
This is also for every frequency within a band.
 If performance is not being met for one of the specifications, then there are basically two options.
The first option is to “tune” by changing SMD’s in the matching network and/or bond wires. If
these work, life is good since the chip does not to be re-spun.
 The other “parameter” that can be modified with the biasing of the PA or the interstage match
(on-chip). Those will require a re-spin (show PA workshop result on what the interstage matching
cap does). Show Vincent’s metric.
 Caveats: designers need to make sure it’s a nominal wafer and nominal laminate or there will be
yield problems later. Statistical models help assure the design is robust.
So You Think It Works, Right?
 After characterization of basic specs, there are other specs that must be checked
before you can send stuff to a customer:
 Junction temperature (junction to board Rth)
 Ruggedness: Does it blow-up when you turn-it on? Does it blow-up under mismatch?
 ESD: if you zap it, does it fry?
 Transient performance (switching, etc), stuff they will likely do in the phone.
 Reliability Testing (product rel).
 If you have to change something to meet one of these, it is often at the die level so it’s a
spin. Note these things are not really related to performance, but may end up trading
off with it!
 These things are often tested towards the end of the development so are
usually the most painful/urgent to correct because of schedule
Some Examples
Gain vs. Temperature
Vref=2.6 Volts
30
Gering, PAWS 2002
Gain (dB)
25
20
15
Pgain, T=-30 C, InGaAsN
10
Pgain, T=85 C, InGaAsN
Pgain, T=25 C, InGaAsN
Pgain, T=-30 C, Control
5
Pgain, T=25 C, Control
Pgain, T=85 C, Control
0
0
5
10
15
20
25
30
Pout (dBm)
Waveform under VSWR
Thermal Scan. Tj<Rel Limit?
Ramping…
 Once the circuit has passed everything (sometimes in parallel to it) it’s time to ramp.
This is where the rubber meets the road for the manufacturing.
 If statistical simulation of the die and laminate has been applied, and sensitivity to
bondwires/die placement is minimize/understood, this can go smoothly.
 Probe limits need to be developed
– A goal is to be able to SIMULATE these first
– A second best approach is using DOE builds
 Final test limits need to be developed
– Also useful to have DOEs (see Mantech 2004 paper)
 Survive ramp and keep fingers crossed 
References
M. Glasbrener, “Breaking EDA Barriers” 2002 IEEE MTT Panel Discussion
B. Gilbert, “Biasing techniques for RF/IF signal processing”, presented at the MEAD Lecture Series shortcourse
lecture, UC Berkeley, CA,1987
P. Zampardi, “III-V HBT Modeling Issues and Future Directions”, CMRF 2004 Workshop, Montreal,
Quebec, Canada
K. Kwok, “Simple DOE-based inductor tool for design automation”, 2008 CS Mantech Conference, Paper
17.2
Y. Yang, “An Innovative and Integrated Approach to III-V Circuit Design”, Microwave Journal, September
2008, pp. 136-156
W. Sun, Workshop WSO, 2012 International Microwave Symposium
A. Metzger, “Evaluation of thermal balancing techniques in InGaP/GaAs HBT power arrays for wireless
handset power amplifiers,” 2012 IEEE Topical Workshop on Handset Power Amplifiers for Wireless
Communications
Jarvenin, “Bias Circuits for GaAs,” IMS 2001, pp. 507-510
Ripley , “Power Detection and Control for Handset Power Amplifiers,” IMS Workshop WSF, 2009
Hongxiao Shao – Mantech 2011 Workshop
Nick Cheng, “Challenges and Requirements of Multimode Multiband Power Amplifiers for Mobile
Applications,” CSICS 2011, pp. 1-4
Acknowledgements
 The support of the SWKS Newbury Park Design Automation and Device Design Teams
is gratefully acknowledged, especially Mats Fredriksson, Kai Kwok, Hongxiao Shao,
Weimin Sun, and Yingying Yang