EGR 278
Digital Logic Lab
File: N278L5A
Lab # 5
Designing Combinational Logic Circuits
A.
Objective
The objective of this laboratory is to emphasize the use of combinational logic circuits to solve
problems. Circuits with both single and multiple outputs will be used.
B.
Materials
Breadboard
5V Power Supply
Wire, switches, LEDs, etc.
Various combinational logic IC’s
C.
555 Timer IC
2.2 k resistors
0.01 uF, 0.068 uF Capacitors
Buzzer (Radio Shack Miniature Audio Transducer)
Introduction
There are numerous practical applications of combinational logic circuits. Circuits can be easily
designed and built to control outputs for various input combinations or to perform some
mathematical or logical function.
Some circuits can be easily designed by directly writing a logical expression to solve the problem.
As an example, suppose that we desired to design a circuit to turn on a light using either of two
switches. If either switch is up, the light will be lit. If both switches are up or both switches are
down, the light will not be lit. If we call the output OUT and the inputs from the switches IN1
and IN2, we can fairly easily reason that
OUT = IN1 • IN2 + IN1 • IN2 = IN1 ⊕ IN2
As problems become more complex, a simple design procedure can be used as is listed below.
Combinational Logic Design Procedure
1.
State the problem
2.
Determine the required inputs and outputs
3.
Assign variables to each input and output
4.
Derive a truth table
5.
Simplify output expressions
6.
Implement each expression
Example: Design a circuit with 4 inputs that has outputs with a binary value equal to the number
of inputs that are HIGH.
Following the Combinational Logic Design Procedure above:
1.
State the problem: Specified with the example in this case
2.
Determine the required number of inputs and outputs: 4 inputs are specified. If all 4 inputs
are HIGH, the output code will be 1002 , so 3 output bits are required.
3.
Assign variables to each input and output: Call the 4 inputs A, B, C, and D. Call the 3
outputs E, F, and G
Page 2
4.
Truth table:
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5.
Inputs
B C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
E F G
0 0 0
0 0 1
0 0 1
0 1 0
0 0 1
0 1 0
0 1 0
0 1 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 0
0 1 1
0 1 1
1 0 0
Simplify output expressions: K-maps for each output are shown below.
CD
AB 00
00 0
01
0
11
0
10
0
01 0
0
0
0
01
11 0
0
1
0
10 0
0
0
0
6.
CD
AB 00
00 0
01
0
11
1
10
0
CD
AB 00
00 0
01
1
11
0
10
1
0
1
1
1
01 1
0
1
0
11
1
1
0
1
11 0
1
0
1
10
0
1
1
1
10 1
0
1
0
E = ABCD
F = A’CD + A’BD + A’BC + ABC’ + ACD’ + AB’D
G = A⊕ B⊕ C⊕ D
Implement each expression: (not shown).
Minimization of Multiple Output Circuits
Minimization problems for circuits with single outputs are relatively straightforward, however,
circuits with multiple outputs are more difficult to minimize. The difficulty in minimizing
multiple output circuits results from the fact that simply minimizing the output expression for
each of the outputs does not always produce the minimal complete circuit. Since product terms
generated as a part of one output can be shared by another output, the use of non-minimal product
terms can sometimes result in more shared gates and thus results in fewer gates for the complete
circuit.
Page 3
Example:
Suppose that a certain circuit has 4 inputs (A,B,C,D) and 3 outputs (F1, F2, F3) where the outputs
are defined as:
F1 = Σ(3, 5 - 7, 11, 13 - 15)
F2 = Σ(0, 4 - 6, 8, 12 - 14)
F3 = Σ(0 - 3, 5, 6, 8 - 11, 13 - 14)
If these 3 outputs were minimized separately into SOP form, the K-maps and output expressions
would be:
CD
AB 00
00 0
01
0
11
1
10
0
CD
AB 00
00 1
01 0
1
1
1
01
11 0
1
1
1
10 0
0
1
0
F1 = CD + BD + BC
01
0
11
0
10
0
CD
AB 00
00 1
01
1
11
1
10
1
1
1
0
1
01 0
1
0
1
11
1
1
0
1
11 0
1
0
1
10
1
0
0
0
10 1
1
1
1
F2 = C’D’ + BC’ + BD’
F3 = B’ + C’D + CD’
Implementing these three functions would require 11 gates (not counting inverters) as shown in
Circuit 1.
C
D
B
D
B
C
C'
D'
B
C'
B
D'
C'
D
C
D'
B'
F1
F2
F3
Circuit 1
Page 4
If the 3 outputs previously considered were now minimized by looking for shared gates in order
to minimize the number of gates used for the total circuit, the K-maps and output expressions
would be:
CD
AB 00
00 0
01
0
11
1
10
0
01 0
1
1
1
01
11 0
1
1
1
10 0
0
1
0
F1 = CD + BC’D + BCD’
CD
AB 00
00 1
01
0
11
0
10
0
CD
AB 00
00 1
01
1
11
1
10
1
1
1
0
1
01 0
1
0
1
11
1
1
0
1
11 0
1
0
1
10
1
0
0
0
10 1
1
1
1
F2 = C’D’ + BC’D + BCD’ F3 = B’ + BC’D + BCD’
Implementing these three functions would require only 7 gates (not counting inverters) as shown
in Circuit 2. Note that two groupings in the K-maps above are non-minimal and these groupings
correspond to the gates labeled U1A and U1B in Circuit 2. These gates are shared by the 3
outputs. Also note that 4 gates were saved as compared to the previous implementation.
C
D
B
C'
D
B
C
D'
C'
D'
B'
F1
U1A
F2
U1B
F3
Circuit 2
Buzzer Circuit
LEDs have been used to indicate the binary values of the outputs of most circuits constructed so far
this semester. In Lab #3 the output of a gate was used to control an auto marker bulb. In this lab, one
of the circuits will be used to sound a buzzer. The buzzer to be used sounds when an input waveform
is applied to the input at a frequency of about 2kHz as shown below.
T = 0.5ms
Square-wave
generator
f = 2 kHz
Buzzer
Buzzer Specifications:
Radio Shack Miniature Audio Transducer
Catalog Number: 273-078
Input: 2 kHz half-duty square wave
Voltage: 3 -12 VAC
Maximum Current: 40 mA
Sound output: 85 dB min.
Page 5
555 Timer
The 555 timer circuit is a popular IC that can be used to implement many types of circuits, including a
square wave generator. The 555 is a linear IC (like an operational amplifier or a voltage regulator)
rather than a digital IC, thus it does not necessarily use TTL voltage levels. In fact, the supply voltage
for the 555 can range from 4.5V to 18V. If a 5V supply if used, it can easily interface with TTL
circuits. The 555 timer can supply an output current of up to 200 mA.
The 555 timer will be discussed in more detail in a later lab. At this time, a circuit using a 555 timer
configured as a squate-wave generator (clock generator) is simply provided.
Vcc
R
8
A
Vcc
7 Discharge
4
Reset
Output 3
R
B
6 Threshold
Trigger
2
C
Control
Voltage 5
Ground
1
0.01 uF
Circuit 3: 555 Timer connected as a square-wave generator
The output of Circuit 3 is shown below in Figure 1.
Output
Voltage
T
Vcc
TH
TL
time
0
Figure 1: Output waveform fo r a 555 square-wave generator
The period and frequency of the output can be determined using the following relationships:
The high time is given by:
TH = 0.693(RA + RB )C
The low time is given by:
TL = 0.693(RB )C
The total period is given by:
T = TH + TL = 0.693(RA + 2RB )C
Page 6
The frequency of oscillation is given by:
f =
And the duty cycle is given by:
D =
(R A
1.44
+ 2R B )C
TH
RA + RB
=
x 100%
T
R A + 2R B
Controlling the clock generator with a logic circuit:
The output of the 555 clock generator can be disabled by setting Reset (pin 4) LOW and enabled by
setting Reset HIGH, so the 555 timer can be be easily controlled by connecting the output of a TTL gate
to Reset. Circuit 4 below illustrates a logic circuit controlling a 555 timer which will sound a buzzer
when the output of the gate is HIGH.
Vcc
8
Vcc
2.2k
4
Reset
f = 2 kHz
7 Discharge
Logic
Circuit
Output 3
Buzzer
4.4k
6
0.068 uF
Threshold
Trigger
2
Control
Voltage 5
Ground
1
Circuit 4: Buzzer controller circuit
0.01 uF
Page 7
D.
Preliminary Work
1.
Design a combinational logic circuit with a single output that will serve as an “auto buzzer
circuit.” This circuit should output a HIGH signal (to sound a buzzer) for each of the
following conditions:
a) if the driver’s DOOR is open and the KEYS are in the ignition
b) if the SEATBELT is not buckled, the SEAT is occupied, and the KEYS are in the
ignition
d) if the HEADLIGHTS are on and the KEYS are not in the ignition.
The auto buzzer circuit is illustrated below.
HEADLIGHTS
(on = HIGH, off = LOW)
SEAT
(occupied = HIGH, not occupied = LOW)
SEATBELT
(buckled = HIGH, not buckled = LOW)
DOOR
Auto
Buzzer
Circuit
OUTPUT
(HIGH activates the buzzer)
(closed = HIGH, open = LOW)
KEYS
(in ignition = HIGH, not in ignition = LOW)
Determine a truth table for the circuit described about and determine a minimal design for
the circuit. Implement the circuit using only AND, OR, NOT, NAND, NOR, and XOR
gates. Generate full circuit documentation for the circuit, including the buzzer controller
circuit (Circuit 4).
2.
Design a combinational logic circuit with multiple outputs that will serve as a 2-bit
multiplier. As illustrated below, the circuit will multiply the 2-bit input (A1 and A0) by the
other 2-bit input (B1 and B0). Since the largest value for each input is 112 = 310 , the largest
possible output is decimal 910 or 10012 . Thus the output requires 4 bits: B3, B2, B1, and
B0.
(MSB) A1
A0
(MSB) B1
B0
2-bit
Multiplier
Circuit
F3 (MSB)
F2
F1
F0
A1 A0
x B1 B0
F3 F2 F1 F0
Determine a minimal design for the circuit described above. Implement the circuit using
only AND, OR, NOT, NAND, NOR, and XOR gates. Your grade will be based to some
extent on the number of gates used. The fewer the gates, the better the grade! Display the
output using four LEDs. Generate full circuit documentation for the circuit.
3.
Calculate the low time (TL), the high time (TH), the period (T), the frequency (f), and the
duty cycle of the output of the buzzer controller circuit shown in Circuit 4.
Page 8
E.
Laboratory Work
1.
2.
Construct the circuit designed in step 1 of the Preliminary Work according to the wire
table generated. Note any changes. Test the circuit for all possible input switch
combinations and record the results in a truth table.
Construct the circuit designed in step 2 of the Preliminary Work according to the wire
table generated. Note any changes. Test the circuit for all possible input switch
combinations and record the results in a truth table.