IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
2961
A Novel High-Frequency Transformer-Linked
Soft-Switching Half-Bridge DC–DC Converter With
Constant-Frequency Asymmetrical PWM Scheme
Tomokazu Mishima, Member, IEEE, and Mutsuo Nakaoka, Member, IEEE
Abstract—This paper presents a novel soft-switching halfbridge dc–dc converter with high-frequency link. The newly proposed soft-switching dc–dc converter consists of a single-ended
half-bridge inverter controlled by an asymmetrical pulsewidthmodulation scheme and a center-tapped diode rectifier. In order
to attain the wide range of soft commutation under constant
switching frequency, the single active edge-resonant snubber cell
composed of a lossless inductor and a switched capacitor is employed for the half-bridge inverter leg, providing and assisting
zero-current-switching operations in the switching power devices.
The practical effectiveness of the proposed soft-switching dc–dc
converter is demonstrated by the experimental results from an
800 W–55 kHz prototype. In addition, the feasibility of the dc–dc
converter topology is proved from the viewpoints of the high
efficiency and high power density.
Index Terms—Asymmetrical half-bridge (AHB) dc–dc converter, constant-frequency pulsewidth modulation (PWM), highfrequency (HF) link, soft commutation, zero-current switching
(ZCS).
I. I NTRODUCTION
T
HE ADVANCEMENT of the asymmetrical half-bridge
(AHB) dc–dc converter and its related technology has
been propelling the development of power supply system with
a large-voltage step-down function in a variety of applications such as plasma display panel, HID lamp, LED backlight driving, mobile and telecommunication equipment, and
contact-less battery chargers [1], [2]. In particular, most of
pulsewidth-modulation (PWM) dc–dc converters with a centertapped or a current doubler rectifier are widely recognized to
be one of the most promising circuit topologies suitable for this
type of power conversion in terms of a high power density, low
profile, and its easy-to-implement control scheme [3], [4].
As a soft-switching AHB dc–dc converter, a series resonant
asymmetrical dc–dc converter with pulse switching frequency
modulation (PFM) scheme has been one of the most practical
Manuscript received August 13, 2008; revised January 7, 2009. First published February 6, 2009; current version published July 24, 2009.
T. Mishima is with the Department of Electrical Engineering and Information
Science, Kure National College of Technology, Hiroshima 737-8506, Japan
(e-mail: mishima@kure-nct.ac.jp).
M. Nakaoka is with the Graduate School of Science and Engineering,
Yamaguchi University, Yamaguchi 753-8511, Japan, and also with the Electric
Energy Saving Research Center, Kyungnam University, Masan 631-701, Korea.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2013692
solutions due to the wide range of soft-switching performance
[2], [5]. The PFM-controlled dc–dc converter, however, has
a shortcoming of severe audible noise generation in the lowoutput-power setting as well as the difficulty for design and
optimization of the passive filter parameter. As a result, those
drawbacks of PFM make PWM dc–dc converter more attractive
to the industrial electric power processing.
In the soft-switching PWM dc–dc converters, zero-voltage
switching (ZVS) has been popular, owing to the less additional
passive components [6], [7]. However, the ZVS commutation
based on the edge resonance with lossless capacitors in parallel
with switching power devices significantly depends on the load
current. This property causes severe limitation of the softswitching operation range under light-load regions. On top of
that, the ZVS scheme is generally not suitable for insulated-gate
bipolar transistor (IGBT) with MOS gate-controlled bipolar
mode characteristics because of the tail current transition at its
turn-off commutation [8], [9].
As a solution to overcome the problems, the zero-currentswitching (ZCS) PWM soft-switching AHB dc–dc converter
topology was newly proposed by the authors in [10]. In this
paper, the performance and feasibility of the new active edgeresonant snubber (AERS)-assisted ZCS-PWM AHB dc–dc converter are evaluated and intensively reported with experimental
analysis performed by the prototype circuit. In particular, the
converter characteristics on the actual conversion efficiency, as
well as the ZCS operation range achieved by the asymmetrical PWM duty-cycle control scheme, are discussed in more
details.
This paper is organized as follows. The circuit configuration
of the proposed dc–dc converter is described with its distinctive
merits. In the next section, operating mode transitions and the
principle, as well as the power regulation scheme, are described.
In addition, the practical circuit design strategy for the softswitching dc–dc converter is introduced in line with describing
the specification of an 800 W–55 kHz prototype. Furthermore,
the circuit operations and static characteristics are demonstrated
by the experimental data obtained from the prototype, and
finally, the feasibility of the ZCS-PWM AHB dc–dc converter
topology is discussed from the practical point of view.
II. C IRCUIT D ESCRIPTION
Fig. 1 shows the proposed dc–dc converter configuration.
Here, Ed represents the input supply dc voltage. This circuit
0278-0046/$26.00 © 2009 IEEE
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
Fig. 1. Proposed AERS-assisted ZCS-PWM half-bridge dc–dc converter with
center-tapped rectifier.
topology is based on an LLC resonant PFM half-bridge dc–dc
converter and is derived from the single-ended push–pull inverter introduced in [11] and [12].
Aside from the main switch Q1 (S1 /D1 ), the high side part
of the half-bridge leg comprises the ZCS-assisted inductor Lr1
and the resonant lossless capacitor Cr actively switched by
the auxiliary switch Q3 (S3 /D3 ), all of which operate as an
active snubber for Q1 . In the low side part of the leg, the other
ZCS-assisted inductor Lr2 is inserted in series with the other
main switch Q2 (S2 /D2 ). The resonant and power factorcorrecting capacitor Cs , which is effective for blocking the dc
component of the half-bridge inverter current and inhibits the
saturation of the high-frequency (HF) transformer, is inserted in
series with Ls that includes the equivalent leakage inductance
Lk of the HF transformer. By utilizing the transformer-parasitic
parameter (Lk , Lm )-based series resonance with Ls and Cs ,
ZCS operation can be performed in Q2 alike.
The AERS-assisted ZCS-PWM dc–dc converter proposed
here has some remarkable advantageous points over the conventional soft-switching schemes such as LLC resonant ZCS-PFM
and ZVS-PWM approach:
1) constant HF switching PWM operation;
2) wide zero-current soft-switching region;
3) optimized HF transformer and output filter;
4) current overlapping mode soft commutation between the
high-and low-side switching power devices due to the
ZCS-assisted inductors Lr1 and Lr2 .
III. O PERATION P RINCIPLE
A. Switching Mode Operation
The key waveforms of the proposed dc–dc converter are
shown in Fig. 2. In addition, its switching mode transitions
and equivalent circuits during switching one cycle are shown
in Fig. 3 under the condition of Lm Ls .
The operation circuit modes are divided into 11 steps during
switching one cycle. While D2 of Q2 is conducting after turnoff commutation of D2 , S1 of Q1 is turned on (Mode 1). Then,
the switch current iQ1 softly increases with the aid of Lr1 ;
thereby, the ZCS turn-on of S1 can be achieved. Edge resonance
with Lr1 and Cr begins at t1 , and D3 of the auxiliary switch Q3
delivers the resonant current circulating in the active snubber
(Mode 2). The edge resonance terminates at t3 when the current
through Q3 reverses its direction (Mode 3).
Fig. 2. Voltage and current waveforms of ZCS-PWM dc–dc converter during
switching one cycle with 45% duty cycle.
Prior to the turn-off of S1 , S3 of the auxiliary switch Q3 in
the AERS cell is turned on (Mode 4). Then, the current iQ3
through Q3 softly increases with edge resonance by Lr1 and
Cr ; thereby, soft-commutation turn-on in Q3 can be performed
under the ZCS mode. Commutation of iQ1 from S1 to D1 is
naturally completed, with the edge resonance continuing from
the previous operation mode (Mode 5). During this interval,
S1 is turned off, and zero-current and zero-voltage switching
(ZCZVS) turn-off can be completely achieved in Q1 (Mode 6).
Commutation of iQ3 from S3 to D3 can be attained, owing to
the series resonance due to Cr , Cs , and Ls . The gate signal
to S3 is removed during this interval, and ZCZVS turn-off
can be achieved in Q3 (Mode 7). Furthermore, the transformer
secondary current reverses its direction; consequently, soft
commutation from Do1 to Do2 is completed in the secondaryside rectifier during Mode 7 due to the leakage inductance of
the HF transformer.
S2 of Q2 is turned on at t7 . Then, the current iQ2 through
Q2 softly increases with the aid of Ls and Lr2 ; thereby, ZCS
turn-on can be achieved in Q2 (Mode 8). In this mode, the
current commutation from Q3 to Q2 is completed. The series
resonance due to Cs , Lr2 , and Ls with the transformer parasitic
parameters takes place (Mode 9). Then, the transformer primary current ip decreases gradually with the series resonance
sustaining from the previous mode. As a result, Do1 begins to
be forward biased, so that the secondary winding of the HF
transformer is shorted (Mode 10). Commutation of iQ2 from
S2 to D2 is naturally completed in Mode 11. The gate signal
to S2 is removed during this interval; thereby, ZCZVS turn-off
can be achieved in Q2 .
The transformer secondary current reverses its direction, and
the rectifier diode Do2 is reversely biased and cut off. At t11 , S1
is turned on by ZCS as well as at t0 , and the converter operation
MISHIMA AND NAKAOKA: NOVEL HF TRANSFORMER-LINKED SOFT-SWITCHING HALF-BRIDGE DC–DC CONVERTER
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Fig. 4. Asymmetrical PWM duty-cycle control scheme: (a) Gate pulse pattern
and (b) circuit diagram of gate pulse generator.
Fig. 3. Switching mode transitions and equivalent circuits during switching
one cycle under Lm Ls .
returns to Mode 1. Note herein that soft commutation between
Q1 and Q2 can be performed by the current overlapping mode
due to Lr1 and Lr2 and that no severe diode recovery appears
in Q1 and Q2 .
B. Gate Pulse Pattern by Asymmetrical PWM-Based
Duty Cycle
The gate pulse timing sequences for all the switches and the
circuit diagram of the pulse generator are shown in Fig. 4(a)
and (b), respectively, [12], [13]. Here, the duty cycle D(=
Ton /Ts ) is adjusted for output voltage control or output power
regulation.
In order to achieve the ZCS operation properly, the controllable range of the asymmetrical duty cycle D is determined by
√
π Lr1 Cr
< D < Dmax
Ts
(1)
where Dmax denotes the maximum duty cycle, and it should be
smaller than 0.5.
The on-period Ton3 of S3 can be fixed in a constant value.
In this interval, the overlapped on-period Ta of S1 and S3 can
be estimated from the resonance period during Mode 4 and
Mode 5 as follows:
√
π Lr1 Cr
.
(2)
Ta ≈
2
Furthermore, the remaining time interval Tb , utilized for the
ZCZVS turn-off commutation of S3 , can be specified by
Cr Cs
Tb ≈ π Ls ·
.
(3)
Cr + Cs
IV. C ONVERTER D ESIGN C ONSIDERATION
A. Circuit Parameters of AERS Cell
In order to ensure the ZCZVS mode turn-off commutation
of the main switch Q1 in the AERS cell, the peak value
of the edge-resonant current through Q1 during its turn-on
commutation should be larger than the transformer primary
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TABLE I
DESIGN SPECIFICATIONS AND CIRCUIT PARAMETERS
OF E XPERIMENTAL P ROTOTYPE C IRCUIT
Fig. 5. Converter characteristics on output/input voltage gain versus converter
switching frequency.
current ip prior to its turn-off commutation. From Fig. 2, this
condition can be expressed by
v (t )
cr 3
> ip (t3 ) ≈ Ipp
Lr1 /Cr
(4)
where Ipp denotes the peak value of ip . Then, the resonant
characteristic impedance Zq1 of the AERS cell is designed by
Lr1
vcr (t3 )
Zq1 =
<
(5)
Cr
Ipp
and Ipp is simply estimated from the HF transformer current at
D = Dmax . Accordingly, Cr can be determined by
Cr >
2
Lr1 Ipp
.
vcr (t3 )2
(6)
The steady-state resonant capacitor voltage vcr (t3 ) is smaller
than the input voltage Ed due to the existence of the capacitor
voltage across Cs . In addition, circulating current within the
active snubber network increases, while the HF transformer
current decreases. Therefore, vcr (t3 ) increases in accordance
with reduction of the duty cycle. Thus, the required capacitance
of the resonant snubbing capacitor Cr can be determined in (6)
by setting the minimum voltage of vcr < Ed .
The peak current Ipp can be determined under condition of
Lm Ls by
Cs
Ed Cs
πNT fs
Ipp ≈
− NT V o
+
(7)
2
Ls
Ls
2NT fo
quality factor Q determined by the series resonant parameters.
The output/input voltage gain G(= Vo /Ed ) of the AHB dc–dc
converter can be defined from the switching frequency fs and
the Ls − Cs series resonant frequency fo by using a fundamental element simplification method [5]
G=
1
· 2NT
1+
Q=
1
k
1−
1
2
2
fo
fs2
+
fs
fo
−
fo
fs
Ls
π2
·
Cs 8NT2 Ro
2
Q
(8)
(9)
where k(= Lm /Ls ) is the ratio of parallel-to-series inductance and NT (= Np /Ns ) is the winding turn ratio of the
HF transformer.
While √
resonant frequency fa in the AERS cell is defined
by 1/(2π Lr1 Cr ), the series resonant frequency fo is determined by
fo =
1
2π (Lr + Ls + NT2 Lo ) · Cs
(10)
where Lr = Lr1 Lr2 .
In the ZCS-PWM scheme treated here, the switching frequency fs is fixed to a value in the region which is smaller
than fo
fs < fo fa .
(11)
where fs and fo denote the switching frequency and the series
resonant frequency of the HF-link half-bridge dc–dc converter,
respectively.
Moreover, owing to the active snubber-assisted soft commutations with the asymmetrical PWM scheme, the switching
frequency of the PWM-based dc–dc converter can be set higher
than that of the PFM-applied counterpart [10].
B. Resonant and Switching Frequency
V. D ESIGN AND S PECIFICATIONS OF P ROTOTYPE C IRCUIT
In Fig. 5, the voltage gain–switching frequency characteristics of the ZCS–PWM dc–dc converter are depicted under a
The prototype of the ZCS-PWM half-bridge dc–dc converter
has been built in order to evaluate the operation characteristics
MISHIMA AND NAKAOKA: NOVEL HF TRANSFORMER-LINKED SOFT-SWITCHING HALF-BRIDGE DC–DC CONVERTER
Fig. 6.
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Simulation current waveforms in AERS cell: (a) Cr = 30 nF, (b) Cr = 55 nF, (c) Cr = 70 nF, and (d) Cr = 100 nF.
of the proposed soft-switching circuit topology and control
schemes. The prototype design specifications and the experimental setup are summarized in Table I.
The input voltage of the prototype dc–dc converter is set in
200 V, and the dc output voltage rating is designed to 15 V in
consideration that the dc–dc converter is suitable as a pointof-load (POL) power converter for the advanced automotive
electric power-train architectures [14]. As a consequence, the
power rating is selected to 800 W, and the winding turn ratio
NT = Np /Ns of the secondary-side center-tapped HF transformer is designed to 5/1.
As one of the examples, the series resonant frequency fo in
(10) and the quality factor Q in (9) are selected to be 80 kHz
and 5, respectively. Accordingly, the series resonant capacitor
Cs and the series inductance Ls with the leakage inductance
Lk of the HF transformer are turned in 260 nF and 16.7 μH,
respectively.
The switching frequency fs is fixed to 55 kHz, taking into
account the electric performance of the IGBT gate driver using
Photocoupler TLP250 under condition of (11). Provided that
the edge-resonant period defined by 1/fa is around 10% of the
switching one-cycle time 1/fs , the edge-resonant frequency fa
can be given as 480 kHz.
The resonant capacitor is required to have a capacitance
large enough for reversing and decaying the current through
the main switch Q1 in the active snubber prior to its turn-off
commutation as mentioned earlier. Now, we have the ZCSassisted inductor Lr1 of 1.6 μH. Prior to the determination
of Cs , the peak current Ipp can be approximately calculated
by (7) [5]
Ipp
Ed
≈
2
Cs
− NT V o
Ls
Cs
πNT fo
+
= 13 A.
Ls
2NT fs
(12)
Therefore, when Lr1 is decided to be 1.6 μH, Cr is given
from (10) by
Cr >
2
Lr1 Ipp
= 27 nF
vcr (t3 )2
(13)
where vcr is selected to be half a dc input voltage (100 V).
Based on the calculated value as a minimum capacitance, the
resonant snubber capacitor Cr is designed in accordance with
the converter soft-switching performance demonstrated by the
simulation results in Fig. 6. Thus, in order to ensure the ZCS
commutation in Q1 without significant power dissipation due
to the circulating current in the active snubber, Cr is selected to
be 70 nF in the prototype circuit.
In accordance with (1), the controlled range of the duty
cycle D is designed by
0.25 < D < 0.45
where the maximum value Dmax is set to 0.45.
(14)
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
Fig. 7. Steady-state operating waveforms in AERS cell at D = 0.43:
(a) Measured waveforms (vcr : 250 V/div; iQ1 , iQ2 , iQ3 : 20 A/div; time :
4.0 μs/div) and (b) simulation waveforms.
Fig. 8. Steady-state operating waveforms in AERS cell at D = 0.3:
(a) Measured waveforms (vcr : 250 V/div; iQ1 , iQ2 , iQ3 : 20 A/div; time :
4.0 μs/div) and (b) simulation waveforms.
VI. E XPERIMENTAL R ESULTS AND E VALUATION
A. Converter Steady-State Operation
The steady-state operating waveforms of the active snubber operation under the duty cycle D = 0.43 and D = 0.3
are shown in Figs. 7 and 8, respectively, compared with the
simulated waveforms. From the measured waveforms, the ZCS
commutation between the main and auxiliary switches can be
confirmed as well as the snubbing operation of the resonant
snubber capacitor Cr . In accordance with reduction of the duty
cycle D, the peak currents in the main switch Q1 and the auxiliary switch Q3 get to be more outstanding. However, the edge
resonant periods related to the peak currents are relatively short,
particularly in the large duty cycle. Thus, the conduction loss
due to the peak current is not so significant, and no profound
reduction of converter efficiency due to the power dissipation
arises.
B. ZCS Commutations in Switching Power Devices
Switching voltage and current waveforms and their V –I
traces of Q1 –Q3 under the duty cycle D = 0.4 are shown in
Figs. 9, 10, and 11, respectively. The complete ZCS turn-on and
the ZCZVS turn-off commutation of each switch are observed
in the respective result. Thus, the feasibility of the proposed
dc–dc converter topology and the soft-switching scheme can be
proven.
Fig. 12 shows the voltage and current waveforms of the
secondary-side diodes Do1 and Do2 . The measured waveforms
depict that the ZCS soft commutation between the two diodes
can be attained in the current overlapping mode due to the
leakage inductances of the secondary-side windings in the HF
transformer. Incidentally, the voltage ringings can be reduced
by employing lossless passive snubbers.
C. Output Power Control Characteristics
The converter performance on output power regulation in the
ZCS-PWM AHB dc–dc converter is investigated under both the
open- and closed-loop control schemes.
Fig. 13(a)–(c) shows the converter characteristics for the
open-loop control scheme, the parameters wherein are the
resistance value of the electric load (KIKUSUI PLZ 1004). In
those results, it can be confirmed that a wide range of output
power regulation can be achieved by a constant-frequency
asymmetrical PWM strategy. The complete ZCS operations
can be attained in the output range of 400–800 W. In the
region under Po = 400 W, the turn-off commutation in Q2
becomes the semi-ZCS mode as shown in Fig. 14. However,
since the voltage and current transitions softly overlap, there
are no significant surges as compared to a hard switching mode
commutation.
MISHIMA AND NAKAOKA: NOVEL HF TRANSFORMER-LINKED SOFT-SWITCHING HALF-BRIDGE DC–DC CONVERTER
Fig. 9.
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ZCS commutations in Q1 : (a) Voltage and current waveforms and (b) V –I trace (vCE(Q1) : 250 V/div; iQ1 : 20 A/div; time : 2.0 μs/div).
Fig. 10. ZCS commutations in Q2 : (a) Voltage and current waveforms and (b) V –I trace (vCE(Q2) : 250 V/div; iQ2 : 20 A/div; time : 2.0 μs/div).
Fig. 11. ZCS commutations in Q3 : (a) Voltage and current waveforms and (b) V –I trace (vCE(Q3) : 250 V/div; iQ3 : 20 A/div; time : 2.0 μs/div).
Fig. 12. Voltage and current waveforms in Do1 and Do2 (vAK : 100 V/div;
i : 50 A/div; time : 4.0 μs/div).
The converter characteristics for the closed-loop control
scheme are shown in Fig. 15, where the output voltage Vo
is regulated to 15 V. The experimental results indicate that
a wide range of output power regulation can be achieved by
the constant-frequency asymmetrical PWM. The complete ZCS
operations are attained in Po = 410 W − 810 W, and the semiZCS operations mentioned earlier are also confirmed in the
region under Po = 410 W.
The actual conversion efficiency is shown in Fig. 16. The
efficiency drop with the load change is due to the increase
of conduction loss in the active snubber rather than the other
circuit components, since the current stress in the active snubber
due to the edge resonance becomes outstanding in the lightload region. However, in the heavy-load region where switching
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
Fig. 13. Open-loop-controlled characteristics: (a) Output power–duty cycle, (b) load current–duty cycle, and (c) output voltage–duty cycle.
Fig. 14. Semi-ZCS turn-off commutation in Q2 (vCE(Q2) : 100 V/div; iQ2 :
5 A/div; time : 1 μs/div).
Fig. 16. Actual efficiency in proposed ZCS-PWM AHB dc–dc converter
(measured by digital power meter YOKOGAWA WT1030).
Fig. 15. Closed-loop-controlled characteristics.
losses account for the large part of the total power loss, the
high efficiency of 96.2% at maximum can be attained under
the constant output voltage condition in the proposed softswitching dc–dc converter.
D. Switching Frequency Evaluation
The switching frequency of the ZCS-PWM scheme is compared with that of ZCS-PFM in Fig. 17 for the same output
power setting. This result depicts that the switching frequency
Fig. 17. Comparison on switching frequencies between PWM and PFM
schemes.
can be increased effectively by employing the asymmetrical
PWM scheme more than the PFM one. Thus, the proposed
ZCS-PWM dc–dc converter and its control scheme are effective
for improvement of the converter power density as well as size
reduction of the passive components.
A discussion on the comparison on the converter efficiencies
between the PWM and PFM schemes is given in the original
conference paper [10].
MISHIMA AND NAKAOKA: NOVEL HF TRANSFORMER-LINKED SOFT-SWITCHING HALF-BRIDGE DC–DC CONVERTER
VII. C ONCLUSION
In this paper, the practical effectiveness of the HF-link
AHB soft-switching dc–dc converter with the single AERS cell
for zero-current commutations under the constant-frequency
asymmetrical PWM scheme has been newly presented, and its
performance on high efficiency power conversion has been
evaluated by in-depth experimental data using its 800 W–
55 kHz prototype. The ZCS operations of the dc–dc converter
are confirmed, and the static characteristics are demonstrated
in order to clarify its feasibility as a high-performance dc–dc
converter. From the results, it has been proven that the ZCSPWM dc–dc converter topology is effective particularly for
the large output current type of power conversion with a large
voltage step-down ratio such as POL power converters. Moreover, the design guideline for the circuit parameters is indicated,
and its validity is also demonstrated by the relevant simulation
and experimental results.
The next challenges include the introduction and evaluation
of PWM and PFM dual-mode schemes in order to achieve a
higher conversion efficiency for the entire output power setting
and further improvement of the power density of the dc–dc
converter.
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Tomokazu Mishima (S’00–M’04) was born in
Tokushima, Japan, in 1975. He received the B.S.,
M.S., and Ph.D. degrees in electrical engineering from the University of Tokushima, Tokushima,
Japan, in 1999, 2001, and 2004, respectively.
Since 2003, he has been with the Department
of Electrical Engineering and Information Science,
Kure National College of Technology, Hiroshima,
Japan, where is currently an Assistant Professor and
engages in the education and research on power
electronics. His main research interests include softswitching dc–dc converters, high-frequency inverters, automotive power electronics, and renewable energy technologies.
Dr. Mishima is a member of the Institute of Electrical Engineering of Japan
and Japan Institute of Power Electronics.
Mutsuo Nakaoka (M’83) received the Ph.D. degree in electrical engineering from Osaka University,
Osaka, Japan, in 1981.
From 1981 to 1995, he was a Professor in the
Department of Electrical and Electronics Engineering, Graduate School of Engineering, Kobe University, Kobe, Japan. From 1995 to 2004, he was
a Professor with the Department of Electrical and
Electronics Engineering, Graduate School of Science
and Engineering, Yamaguchi University, Yamaguchi,
Japan. He is also currently a Visiting Professor with
Kyungnam University, Masan, Korea, and Industrial College of Technology,
Hyogo, Japan. His research interests include application developments of power
electronics circuits and systems.
Prof. Nakaoka is a member of IEEJ, JIPE, KIPE, EPE, and other institutions
related to power electronics. He served as a Chairman of the IEEE Industrial
Electronics Society Japan Chapter in 2001. He received many distinguished
paper awards on power electronics such as the 2001 Premium Prize Paper
Award from IEE-U.K., the 2001/2003 IEEE-IECON Best Paper Award, the
Third Paper Award in 2000 IEEE-PEDS, the 2003 IEEE-IAS James Melcher
Prize Paper Award, and the Best Paper Award of IATC’06.