Semicond. Sci. Technol. 12 (1997) 1355–1357. Printed in the UK
PII: S0268-1242(97)83410-4
Electrical characterization of
inversion layer carrier profile in
deep-submicron p-MOSFETs
Bin Yu†, Kiyotaga Imai‡ and Chenming Hu†
† Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley, CA 94720, USA
‡ ULSI Device Development Laboratory, NEC Corporation, Ibaraki 305, Japan
Received 14 April 1997, accepted for publication 14 July 1997
Abstract. A simple electrical method is presented for the characterization of the
inversion layer in p-channel MOSFETs with either p+ poly gate (surface channel,
SC) or n+ poly gate (buried channel, BC). The d.c. centroid of the inversion layer
profile, Xc , represents the effective thickness of the inversion layer in the SC device
or the physical location of the buried channel in the BC device. For the first time, it
is well demonstrated that, based on the small-signal gate-to-channel capacitance
measurement, the global inversion layer hole profiles in both types of p-MOSFETs
can be constructed from three elements, i.e. Xc (d.c. centroid), Xw (band diagram
characteristic width) and 1Ninv (increment of net carrier area density).
1. Introduction
In deep-submicron MOSFET technology, the thickness of
gate-oxide becomes comparable with that of the inversion
layer. The physical effect of finite inversion layer thickness
(FILT) can no longer be neglected, resulting in deviation
of electrical parameters (e.g. Gm ) from the conventional
model. Further, the combination of thin gate oxide (Tox ≤
100 Å) and high channel doping (≥1017 cm−3 ) results
in sufficient large transverse electric fields at Si/SiO2
interface to make a quantization effect observable even
at room temperature. Although properties of carriers in
inversion layers have been studied for almost three decades,
continued scaling of MOSFETs has led to the increasing
importance for accurate characterization of inversion layer
in order to correctly model the MOSFET’s current drive,
subthreshold swing, short-channel effect, etc. Quantum
mechanical calculation of the inversion layer profile was
recently reported [1–6]. However, a simple electrical
characterization method is much preferred. The quantum
effect manifests itself through such measurable quantities
as the inversion layer charge density. In this paper, a
high-frequency small-signal C–V method is proposed to
characterize the inversion layer in very thin gate oxide
MOSFETs (Tox ≤ 70 Å).
For p-channel MOSFETs, the situation is more
complicated than for their n-channel counterparts due to
the existence of two types of structures: p+ poly gate
(surface channel, SC) and n+ poly gate (buried channel,
BC). In the BC device boron counter-doping is implanted
into the channel to adjust the Vth , and the inversion layer
is rather a global one because the hole-conducting channel
c 1997 IOP Publishing Ltd
0268-1242/97/111355+03$19.50 is locally accumulated in the counter-doping p-region, but
inverted with respect to the n-substrate. In either structure,
the extraction of the inversion layer effective thickness and
carrier profile is very important in device modelling.
2. Theory of extraction method
The experimental set-up for inversion layer characterization
is shown in figure 1. The small-signal gate-to-channel
capacitance, Cgc , is measured between the gate and the
tied source/drain using an HP4284 LCR meter under a high
frequency (100 MHz). Large MOSFETs (50 µm × 50 µm)
are used to minimize the extrinsic influence of gate overlap
capacitance. The net inversion charge in the channel, Qinv ,
RV
is obtained by the integral 0 g Cgc dVgc . The net inversion
carrier area density, Ninv , is given by Qinv /qAeff with Aeff
the effective channel area.
2.1. Extraction of inversion layer effective thickness
Because of the FILT effect, Cgc consists of two components
as shown in figure 1: the intrinsic gate capacitance, Cox ,
and the a.c. small-signal inversion capacitance, Cinv(ac)
Cgc
1Qinv
=
=
1Vgc
1
1
+
Cox
Cinv(ac)
−1
(1)
where Cox is measured directly from the C–V curve with
very large positive Vgc (when the p-MOSFET channel is
biased into accumulation). Cinv(ac) = ε0 εsi /Xinv(ac) Aeff
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Bin Yu et al
Figure 1. Schematic diagram of the experimental set-up
for characterizing the global inversion layer using
high-frequency channel capacitance measurement.
and Xinv(ac) is the equivalent thickness of the inversion
layer under the small-signal condition
1
1
Xinv(ac) = ε0 εsi
−
.
(2)
Cgc
Cox
The physical meaning of Xinv(ac) is the average location
for each small increment of inversion charge. The effective
thickness of the inversion layer, Xinv(eff ) , is defined as the
centroid of the inversion profile:
R Vgc
R
Xinv(ac) dQinv
Vgc0 Cgc Xinv(ac) dVgc
R
Xinv(eff ) ≡ Xc =
=
.
R Vgc
dQinv
Vgc0 Cgc dVgc
(3)
Here Vgc0 is the starting biasing point for the integration
and is appropriately selected to be where the drain current
reaches 0.1 nA per micrometre of channel width. The
physical implication of Xinv(eff ) is the depth in the
inversion layer within which 50% of the net inversion
charge resides. Xinv(eff ) represents the effective thickness
of the inversion layer in an SC device or the physical
location of the buried channel in a BC device.
Figure 2. The measured gate-to-channel capacitance, Cgc ,
for both n+ poly gate (BC) and p+ poly gate (SC)
p-MOSFETs: Tox (BC p-MOSFET) = 70 Å, Tox (SC
p-MOSFET) = 65 Å. Inset: total net charge in the channel,
Qinv , integrated from the Cgc –Vgc curve. Squares,
Vbs = 0 V; triangles, Vbs = 1 V. Device area 50 µm × 50 µm.
2.2. Construction of the inversion layer profile
The inversion layer carrier profile can be constructed
based on three elements: Xc (d.c. centroid), Xw (band
diagram characteristic width) and 1Ninv (increment of net
carrier area density). The inversion profile is the eventual
contour under which each small increment of charge 1Ninv
piles up as a contributing block centring at Xc , with
a width Xw and a height 1Ninv /Xw . Xc is given by
equation (3), while 1Ninv is the difference of Ninv at two
adjacent Vgc biasing points (a sufficiently small step must
be selected). The characteristic width Xw is defined as
the spatial width within which the band diagram drops
by a voltage of kT /q (volts). In a buried-channel pMOSFET, the potential in the counter-doping p-channel
region was solved to be in a √
parabolic shape [7] with the
characteristic length Xw = 2 2ε0 εsi (kT /q)/qNA , where
NA is the effective doping density in the channel region.
In surface-channel p-MOSFET, the characteristic
length
√
Xw = (kT /q)/(QB /ε0 εsi ) with QB = 2qε0 εsi ND φS .
Here ND is the substrate doping density and φS is the
Fermi potential. In this method both NA and ND are
extracted from the C–V measurement and represent the
average doping in the channel region.
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Figure 3. The small-signal inversion layer thickness,
Xinv (ac ) , plotted as a function of Vgc for both BC and SC
devices. The physical implication of Xinv (ac ) is the average
location for each small increment of inversion charge.
3. Results and discussion
The devices used in this study were p-MOSFETs with
both n+ poly gates (BC) and p+ poly gates (SC). The
gate oxide thicknesses were 70 Å (BC) and 65 Å (SC),
respectively. For the BC p-MOSFET, boron counterdoping was performed using 20 keV, 5 × 1014 cm−2 BF2
implantation. Rapid thermal annealing (RTA) was used
in source/drain (S/D) formation to achieve very shallow
junctions (both S/D and counter-doping channel). The
threshold voltages, determined by linear extrapolation in
the Ids versus Vgs plot, were measured to be −0.932 V (BC
p-MOSFET) and −0.674 V (SC p-MOSFET), respectively.
Figure 2 shows the measured Cgc versus Vgc curves for
both types of devices with the inset showing Qinv integrated
as a function of Vgc . From equation (2) the a.c. small-
Deep-submicron p-MOSFETs
Xinv(eff ) (23 Å for the BC p-MOSFET and 4 Å for the
SC p-MOSFET) is observed in both devices. Figure 5
shows the inversion layer profiles for both types of devices
constructed from three elements (Xc , Xw and 1Ninv ) with
the inset showing the piling up of two (out of many)
adjacent small charge increments to obtain the contour of
the inversion layer charge profile. At Vgc = Vth the ‘buriedchannel’ nature of n+ poly gate device is clearly seen (the
peak is located ∼150 Å beneath the surface). The peak
of the inversion layer profile for the p+ poly gate device
is located ∼18 Å beneath the surface. This phenomenon
is, not surprisingly, consistent with the theoretical result
obtained from quantum mechanics calculation.
4. Summary
Figure 4. The centroid of hole profile, Xc , is plotted as a
function of Ninv for both devices. Xc represents the
effective thickness of the inversion layer for the SC device
(in which 50% Qinv resides) and the physical location of the
buried channel for the BC device.
A simple electrical technique for characterizing the global
inversion layer effective thickness and charge profile in
both n+ poly gate and p+ poly gate p-MOSFETs is
proposed based on the high-frequency channel capacitance
measurement. For the studied devices (Tox = 65–70 Å), the
FILT effect already results in about 20% transconductance
deviation (degradation) from the conventional model in SC
p-MOSFETs at Vgc = Vth + 0.5 V. Even in the strong
inversion regime, a finite thickness of the inversion layer
is still observable for both types of devices. The FILT
effect needs to be well addressed in device modelling in
the deep-submicron regime. The extracted inversion layer
profile shows consistency with the predicted result from
quantum mechanical theory.
Acknowledgment
The project was supported by AFOSR/JSEP under contract
F-49620-94-C-0038.
Figure 5. The extracted inversion layer (hole) profiles for
both types of p-MOSFET devices. The method of
constructing an inversion layer profile from three elements
(Xc , Xw and 1Ninv ) is demonstrated in the inset which
shows the piling up of two adjacent carrier increments.
Many such small charge increments pile up to obtain the
eventual inversion layer profile.
signal inversion layer thickness, Xinv(ac) , is extracted and
plotted as a function of Vgc as shown in figure 3. Based
on equation (3) the effective thickness (centroids) of the
inversion layer for both devices is calculated and plotted as
a function of carrier area density Ninv as shown in figure 4.
It is found that, at Vgc = Vth , the effective thickness of
the inversion layer in the p+ poly gate (SC) p-MOSFET
is about 30 Å, while the buried-channel location in the n+
poly gate (BC) p-MOSFET is 150 Å beneath the silicon
surface. At Vgc = Vth + 0.5 V, Xinv(eff ) are 8 Å and 45 Å
for the SC and BC p-MOSFET respectively. Therefore,
with the existence of the FILT effect, the effective oxide
thickness, Tox(eff ) , defined as Tox + Xinv(eff ) , must be used
in the estimation of device performance. In strong inversion
(Vgc ' Vth + 1 V or Ninv = 3 × 1012 cm−2 ), a ‘residual’
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