Slide 1
Successful Design of OC-48/2.5Gbps Interconnects
Limits of FR-4 in
High-Speed Designs
Dr. Edward Sayre, Mr. Michael Baxter, Dr. Jinhua Chen
NESA
Tel: 978 897-8787 v Fax: 978 897-5359
www.nesa.com v info@nesa.com
High Performance Engineering & Design
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Slide 2
Successful Design of OC-48/2.5Gbps Interconnects
The FR-4 Problem in Gigabit Design
• FR-4 is the most common PCB Fabrication material
and the most cost effective.
• Fabricators know how to laminate and etch a wide
variety of conductor patterns and conditions
• A well known material with UL and other approvals
• Question of the Hour!!!!
How far can Gigabit signals be run on 100 Ω
impedance differential etch and at what speeds?
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Slide 3
Successful Design of OC-48/2.5Gbps Interconnects
Total RF Transmission Line Loss

Rdc + Rs f 
Attenuation
(dB) = 4.35Gd * f * Z 0 +

Per Unit Length
Z0


Where: Gd = shunt dielectric conductance [Ω Hz]-1
Rs = skin effect series loss [Ω(Hz)-1/2]
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Slide 4
Successful Design of OC-48/2.5Gbps Interconnects
Frequency Where Skin Effect Losses
Equal Dielectric Losses
fe
Where:
Rs
1 
≡ 
• 2 
Z0 
G d
2
Rs = Skin Effect Resistance [Ω(Hz)-1/2]
Gd = Dielectric Shunt Conductance [Ω Hz]-1
Zo = Transmission Line Impedance [Ω]
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Slide 5
Successful Design of OC-48/2.5Gbps Interconnects
Typical Values for FR-4 & Common Line
Parameters
•
•
•
•
•
Line Width - 8 mil
Line thickness - 1 oz Cu (1.4 mils)
Differential Impedance Zo = 100 Ω
FR-4 Dielectric Constant = 4.5
FR-4 Loss Tangent = 0.021 (assumed constant)
• Skin Loss = Dielectric Loss at fe = 205 MHz
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Slide 6
Successful Design of OC-48/2.5Gbps Interconnects
RF Total Loss vs. Normalized Frequency
Total Loss (% )
80.0%
Percentage Loss
70.0%
60.0%
50.0%
40.0%
30.0%
20.0%
10.0%
0.0%
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency (f /f e )
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Slide 7
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
data rate, PCB lengths from 10”to 50”with 8 mil line width
80.00
PCB Peak to Peak Loss (%)
70.00
60.00
50.00
50"
40"
40.00
30"
30.00
20"
20.00
10"
10.00
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Data Rate (Gbps)
High Performance Engineering & Design
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Slide 8
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
PCB length with 8 mil line width
80.00
PCB Peak to Peak Loss (%)
70.00
60.00
50.00
5 Gbps
40.00
2.5 Gbps
30.00
1.6 Gbps
1.25 Gbps
20.00
622 Mbps
10.00
0.00
0.0
10.0
20.0
30.0
40.0
50.0
60.0
PCB Length (inch)
High Performance Engineering & Design
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Slide 9
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
data rate, PCB lengths from 10”to 50”with 6 mil line width
80.00
70.00
PCB Peak to Peak Loss (%)
60.00
50"
50.00
40"
30"
40.00
30.00
20"
20.00
10"
10.00
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Data Rate (Gbps)
High Performance Engineering & Design
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Slide 10
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
PCB length with 6 mil line width
80.00
70.00
PCB Peak to Peak Loss (%)
60.00
5 Gbps
50.00
2.5 Gbps
40.00
1.6 Gbps
30.00
1.25 Gbps
622 Mbps
20.00
10.00
0.00
0.0
10.0
20.0
30.0
40.0
50.0
60.0
PCB Length (inch)
High Performance Engineering & Design
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Slide 11
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
data rate, PCB lengths from 10”to 50”with 4 mil line width
80.0
70.0
60.0
PCB Peak to Peak Loss (%)
50"
40"
50.0
30"
40.0
20"
30.0
20.0
10"
10.0
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Data Rate (Gbps)
High Performance Engineering & Design
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Slide 12
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of
PCB length with 4 mil line width
80.0
70.0
PCB Peak to Peak Loss (%)
60.0
5 Gbps
50.0
2.5 Gbps
40.0
1.6 Gbps
1.25 Gbps
30.0
622 Mbps
20.0
10.0
0.0
0.00
10.00
20.00
30.00
40.00
50.00
60.00
PCB Length (inch)
High Performance Engineering & Design
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Slide 13
Successful Design of OC-48/2.5Gbps Interconnects
100 Ω Differential PCB
percentage peak to peak loss as the function of data rate
30" traces with 4, 6 and 8 mil line width
60.00
50.00
PCB Peak to Peak Loss (%)
4 mils
6 mils
40.00
8 mils
30.00
20.00
10.00
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Data Rate (Gbps)
High Performance Engineering & Design
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Slide 14
Successful Design of OC-48/2.5Gbps Interconnects
Simulated 2.5 Gbps Eye Pattern
skin effect + dielectric loss (FR-4 loss tangent 0.021) for 40”trace
0.8
0.6
Voltage (V)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0
0.1
0.2
0.3
0.4
Time (ns)
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Slide 15
Successful Design of OC-48/2.5Gbps Interconnects
Simulated 2.5 Gbps Eye Pattern
skin effect + dielectric loss for 40”trace with two backplane connectors
0.8
0.6
0.4
Voltage (V)
0.2
0
-0.2
-0.4
-0.6
-0.8
0
0.1
0.2
0.3
0.4
Time (ns)
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Slide 16
Successful Design of OC-48/2.5Gbps Interconnects
Measured 2.5 Gbps Eye Pattern
skin effect + dielectric loss for 40”trace with two backplane connectors
LONG CONTROL PAIR EYE DIAGRAM, 2.5GBPS
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Slide 17
Successful Design of OC-48/2.5Gbps Interconnects
Differential 1.25 Gbps Eye Pattern
23”trace including two backplane connectors
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Slide 18
Successful Design of OC-48/2.5Gbps Interconnects
Poor Fabrication Results
Differential TDR vs. Risetime
Highly Resistive
Lossy Etch
Skin Effect
Region
SMA Connector
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Slide 19
Successful Design of OC-48/2.5Gbps Interconnects
1.25 Gbps Eye Pattern
properly etched differential pair
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Slide 20
Successful Design of OC-48/2.5Gbps Interconnects
1.25 Gbps Eye Pattern
over-etched differential pair
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Slide 21
Successful Design of OC-48/2.5Gbps Interconnects
FR-4 PCB Limits - Summary
• Eye Diagram Response
– Deterministic Jitter and Risetime Losses are well known and due to dielectric
and conductor skin effect losses.
– Eye diagram mask violations in amplitude or bit time jitter lead to unacceptable
Bit Error Rates
• Fabrication Quality of PCB traces strongly affects eye response.
– 100 Ω impedance line losses not strongly affected by line size.
• Semiconductor pulse fidelity and receiver determining factors
– Receiver threshold region < (15 - 20%) of swing OK
– Risetimes <(15 - 20)% of bit width reduces mask violations
• FR-4 max. line length depends on devices, bit rate, reflections and losses
– As a practical matter, jitter more forcefully impacted by bandwidth limits due to
losses
– Connector reflections shorten maximum length.
• Maximum usable clock rate Fclk ~ (7 - 10) * fe at reasonable PCB lengths of
0.5 meter to 1.25 meter.
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