Direct 100G connectivity with optoelectronic POLYmer
Direct 100G connectivity with optoelectronic POLYmer-
InP integration for data center SYStems
Grant Agreement no. 258846
Specific Targeted Research Project (STREP)
Information & Communication Technologies (ICT)
Deliverable D7.3
Report on applicability and techno‐economic analysis of
POLYSYS subsystems
(Public report)
ICT-POLYSYS D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
ICT-POLYSYS 2 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
List of acronyms
LiNbO
3
MAN
MEMS
MMI
MPO
MW
MZM nm
NRZ
NRZ-ODB
O-OFDM
OOK
DP
DP-QPSK
DRV
DSP
ECOC
EO
ETDM
FTTH
GbE
HDMI
HDTV
HPC
InP
(DE) MUX
3-ASK
AOC
ASIC
AWG
BiCMOS
CAGR
CapEx
CL
Clk
CMOS dB
DC
DD
DFB laser
DHBT
DI
(DE) Multiplexer
3 (level)-Amplitude Shift Keying
Active Optical Cable
Application-Specific Integrated Circuit
Arrayed Waveguide Grating
Bipolar CMOS
Compound Annual Growth Rate
Capital Expenditure
Coupling loss
Clock
Complementary Metal–Oxide–Semiconductor decibel
Data Center
Direct Detection
Distributed Feedback laser
Double Heterojunction Bipolar Transistor
Delay Interferometer
Dual Polarization
Dual Polarization-Quadrature Phase-Shift Keying
Driver
Digital Signal Processing
European Conference on Optical Communication
Electro-Optic
Electronic Time Division Multiplexing
Fiber To The Home
Gigabit Ethernet
High-Definition Multimedia Interface
High Definition Television
High-Performance Computing
Indium Phosphide
Lithium Niobate
Metropolitan Area Networks
Micro-Electro-Mechanical Systems
Multi-Mode Interference
Multi-Fiber Push-On
Mega Watt
Mach Zehnder Modulator nano meter
Non Return-to-Zero
Non Return-to-Zero Optical DuoBinary
Optical Orthogonal Frequency Division Multiplexing
On-Off Keying
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RZ
RZ-DPSK
SAS
SDM
SiGe
SMF
SOA
SOI
TEC
TIA
ToR
TWA
TWEAM
UHDV
UMZM
VCSEL
VDSL
WDM
PD
PHY
PIC
PMD
PON
QDR
QoS
RF
OpEx
OSNR
PAM
PBC
PBS
PCB
Operating Expenditure
Optical Signal-to-Noise Ratio
Pulse Amplitude Modulation
Polarization Beam Coupler
Polarization Beam Splitter
Printed Circuit Board
Photodiode
Physical layer
Photonic Integrated Circuit
Polarization Mode Dispersion
Passive Optical Network
Quad Data Rate
Quality of Service
Radio Frequency
Return-to-Zero
Return-to-Zero Differential Phase-Shift Keying
Slot Accounting System
Space-Division Multiplexing
Silicon Germanium
Single-Mode Fiber
Semiconductor Optical Amplifier
Silicon-On-Insulator
Thermo-Electric Cooler
Trans-Impedance Amplifier
Top of Rack
Travelling Wave Amplifier
Travelling Wave Electro-Absorption Modulator
Ultra High Definition Television
Unbalanced Mach-Zehnder Modulator
Vertical Cavity Surface-Emitting Laser
Very-high-bit-rate Digital Subscriber Line
Wavelength Division Multiplexing
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Table of Contents
2.3 Development of high-speed transceivers for 100 GbE telecom systems (System 3)................ 9
3.2 Opportunities in next-generation high-performance computing (HPC) systems ................... 11
5.2.3 100 Gb/s transceiver for 100 GbE in telecom networks (metro/regional) ..................... 30
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1.
Introduction
POLYSYS is an ambitious research project aiming at developing and integrating photonic and electronic components in order to provide direct 100 Gb/s connectivity without the use of parallel approaches or higher-order modulation formats. To achieve this goal, POLYSYS is relying on the use of ultra-fast polymer modulators and the development of ultra-fast InP electronics and photoreceivers. The modules that will be developed will be used in three different application areas:
1) Chip-to-chip interconnects for on board data connectivity within the same server-rack in data-centers.
2) Rack-to-rack interconnects between server-racks in data-centers.
3) Future 100 Gb/s Ethernet systems (100 GbE) in metropolitan area networks.
The present report represents a structured effort to identify the needs for higher capacity and the opportunities created in different parts of datacom and telecom networks for communication equipment (components, subsystems and systems) capable of operating at ultra-high speed. The studies included in this report go one step further making a first techno-economic analysis and a comparison study of POLYSYS technology with respect to the main technologies and techniques for short-reach optical interconnects and 100 GbE telecom links in metro networks. The comparison is made on the basis of the system simplicity, robustness, and performance, the number of photonic and electronic components required, and the fabrication cost taking into account the perspectives for the reduction of this cost under the assumption of wide commercialization and high-volume production of relevant components and systems. Finally, a study of the power consumption of
POLYSYS systems is made in order to compare the energy efficiency of the POLYSYS technology with the main alternative technologies today.
The structure of the present report is as follows:
Chapter 2: Summary of POLYSYS project objectives and main characteristics/specifications of
the modules and systems targeted within the project.
Chapter 3: Overview of the growth in the capacity needs in every part of communication
networks today, driven by a variety of bandwidth demanding applications, and explanation of how this growth is translated into need for high-bandwidth components and systems for chip-to-chip interconnects, rack-to-rack interconnects and metro links.
Chapter 4: Techno-economic analysis of POLYSYS technology using the criteria mentioned in
the previous chapters.
Chapter 5: Power consumption analysis of the POLYSYS systems.
Chapter 6: Summary of the findings of this study.
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2.
Project description and objectives
In the present chapter, the basic objectives of POLYSYS project and the characteristics of the devices/systems that POLYSYS is targeting at are described in brief.
POLYSYS develops components, devices and systems for direct connectivity at 100 Gb/s and beyond, using simpler on-off keying (OOK) modulation formats and direct detection (DD) schemes. To support this evolution path, POLYSYS relies on material systems and integration technologies for photonic and electronic circuits that can provide maximum speed of operation. More specifically, POLYSYS invests on electro-optic (EO) polymers for the development of optical modulators that are capable of
100 Gb/s operation, on InP optoelectronic circuits for the development of pin-photodetectors and photoreceivers with optoelectronic bandwidth in excess of 100 GHz, and on the InP-double heterojunction bipolar transistor (InP-DHBT) technology for the development of electronic circuits that can support electronic time division multiplexing (ETDM) and clock recovery functionalities and can operate directly at 100 Gb/s.
Furthermore, POLYSYS develops arrayed versions of these components in order to demonstrate 400
Gb/s connectivity and to show that Tb/s optical interconnects are feasible. The exploitation plan of
POLYSYS is straightforward and relies on a single most important historical fact in the development of transmission hardware: serial technologies have always overtaken more complex parallel approaches. The plan for the exploitation of POLYSYS technology and devices involve both datacom and telecom applications. More specifically, the targeted transmitters and receivers will be used for the realization of a chip-to-chip interconnect operating at 100 Gb/s (System 1), a 4x100 Gb/s active optical cable (AOC) for rack-to-rack interconnects in modern data-centers (system 2), and a highspeed 100 Gb/s transceiver for metro network telecom applications (system 3). More details on the architecture and the targeted characteristics of the POLYSYS devices and systems are given below.
2.1
Development of integrated optical interconnects directly at 100 Gb/s (System 1)
System 1 of POLYSYS refers to an integrated optical link for chip-to-chip interconnects inside high-
performance computing (HPC) systems [1]. The optical interconnect is capable of operating directly
at 100 Gb/s through the use of subsequent data aggregation steps, ETDM techniques and high-speed optoelectronic components. The general architecture of System 1 and the specific components that
are included in this architecture are depicted in Figure 1.
Figure 1 : Architecture of 100 Gb/s integrated optical interconnect (System 1 of POLYSYS).
Electrical data signals at 50 Gb/s (Data 1 and Data 2) serve as input for the 2:1 MUX unit, which performs the final aggregation step in order to create the 100 Gb/s electrical data signal that drives the EO polymer modulator. The latter is fed by the output of the DFB laser, which is butt-coupled to the polymer chip. The length of the waveguide at the output of the MZM determines the length and the power budget of the optical interconnect. At the other side, the 100 Gb/s optical signal is
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detected by an ultra-high speed InP pin-photodetector, which is also butt-coupled to the polymer board. The output electrical signal is then driven to the input of the 1:2 DEMUX unit with a transimpedance amplifier (TIA) at the front-end. The 100 Gb/s electrical signal is then amplified and demultiplexed into the two 50 Gb/s tributaries. Additional demultiplexing stages may be used to deliver time tributaries at lower aggregated rates (25 Gb/s, 12.5 Gb/s etc). Significant parameters that have to be taken into consideration include the optical coupling losses between the InP elements and the polymer boards (CL1 and CL2), the conversion gain (in V/W) of the pinphotodetector, the electrical coupling loss between the pin-photodetector and the TIA-DEMUX chip, and the input sensitivity of the TIA-DEMUX chip, which practically depends on the gain of the TIA and the input sensitivity of the DEMUX unit. Finally, it is noted that both the MUX and the DEMUX units require a 50 GHz electrical clock for proper operation.
2.2
Development of active optical cables at 100 and 4x100 Gb/s (System 2)
System 2 is an active optical cable (AOC) with 400 Gb/s total throughput, based on arrayed
modulators, pin-travelling wave amplifiers (pinTWA) photoreceivers and 1:2 DEMUX units. Figure 2
presents the architecture of the AOC consisting of two 2x100 Gb/s transmitter modules, a single
4x100 Gb/s receiver module, and a quad single-mode fiber (SMF) array that implements the spatial
multiplexing scheme for scaling the throughput from 100 to 400 Gb/s. The inset of Figure 2 presents
the artistic layout of the twin 2x100 Gb/s transmitter module consisting of two individual boxes. Each box represents a 200 Gb/s transmitter and consists of a single DFB laser butt-coupled to the polymer board, the polymer board itself involving a 1:2 multi-mode interference (MMI) coupler and two arrayed modulators, and the two electronic MUX and driving circuits for each one of the modulators.
Light from the output waveguides of the transmitter modules is coupled to the arrayed SMFs, connecting the two transmitter modules with the 4x100 Gb/s receiver of the system. The receiver consists of a monolithic 4x100 Gb/s array of pinTWA photoreceiver and two monolithic twin arrays of
1:2 DEMUX units. As per System 1, the MUX and DEMUX units of System 2 need to be fed with electrical clock signals at 50 GHz.
Figure 2 : Architecture of 4x100 Gb/s active optical cable (System 2 of POLYSYS).
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As already mentioned, the system has been designed as a high-throughput AOC that can be used for datacom applications, such as rack-to-rack interconnects inside modern data centers. The factors that limit the maximum length of the AOC relate to the achievable power budget and the chromatic dispersion. Lengths from a few meters up to several hundreds of meters (>700 m) are achievable and define the range of possible applications for this type of optical interconnect.
2.3
Development of high-speed transceivers for 100 GbE telecom systems (System 3)
Finally, System 3 corresponds to a 100 Gb/s transceiver for telecom applications in metropolitan area
networks. The architecture of the transceiver module is shown in Figure 3. The package consists of
two discrete parts; the first one accommodating the tunable 100 Gb/s transmitter and the second one accommodating the 100 Gb/s receiver with clock recovery functionality.
The wavelength tunability of the 100 Gb/s transmitter covers a total range of >15 nm in the 1550 nm area, and allows for using the module in complex wavelength division multiplexing (WDM) schemes with variable channel spacing. The potential for wavelength tunability relates to the replacement of the DFB laser in the transmitter module of System 1 with an InP gain chip that is butt-coupled to the polymer chip. A Bragg-grating at the input waveguide of the polymer chip provides a reflection peak at wavelength λB, and practically forms the end (semi-transparent) reflector of the laser cavity. The latter spans according to the description provided above over both the InP component and the polymer board. By thermally tuning the Bragg-grating, the reflection peak of the grating and thus the emission wavelength of the laser can be tuned over the wide range mentioned above (>15 nm).
Figure 3 : Architecture of 100 Gb/s tunable transceiver (System 3 of POLYSYS).
At the receiver side, the additional unit is the clock recovery unit that allows for recovering the 50
GHz clock signal from the detected 100 Gb/s data signal using high-speed InP-DHBT phase detectors and filters. The recovered clock serves as the synchronization signal for the proper operation of the
1:2 DEMUX chip. Although placed in different parts, the tunable transmitter and the receiver are accommodated inside a single gold-box package allowing for a reliable and compact 100 Gb/s transceiver solution.
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3.
Applicability of POLYSYS devices and systems
3.1
Growth of traffic and capacity demands
International network capacity growth remains brisk, increasing 40% in 2012. The pace of traffic growth and its impact on the topology of the Internet vary around the world.
TeleGeography’s annual survey of Internet backbone operators tracks Internet capacity deployments
as well as peak and average network traffic volumes [2]. The rate of capacity growth dropped in 2012
from 68% in 2008 to 40% in 2012 (Figure 4). While slower than in previous years, capacity growth remains robust: aggregate international bandwidth more than doubled in the past two years, from
37 Tb/s in 2010 to 77 Tb/s in 2012.
Figure 4 : International Internet bandwidth from 2008 to 2012 [1].
Of the 77 Tb/s of international Internet capacity, 25 Tb/s are deployed on interregional links, while
52 Tb/s connect countries within each of the major world regions. The highest capacity interregional route continues to be Europe-U.S. & Canada, which had 7.9 Tb/s of capacity in 2012, followed by
Asia-U.S. & Canada and Latin America-U.S. & Canada, which each had >6 Tb/s of capacity. While the three highest-capacity interregional routes are connected to the U.S. & Canada, international network capacity has become less centred on this region in recent years. The development of rich regional networks, coupled with a need for diversification, has reduced the share of international capacity connected to the United States & Canada from all regions except Latin America.
The combined effects of new Internet-enabled devices, growing broadband penetration in developing markets, higher broadband access speeds, and bandwidth-intensive applications, will continue to fuel strong Internet traffic growth. The fact that the cloud continues to grow is a significant factor propelling the increase in Internet traffic: “Cloud services” is a catchall phrase for a broad range of applications that can be delivered to end users’ devices from a central computing
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platform or server via the Internet. Cloud services are traditionally conceived as including such applications as corporate data processing and file storage, but in its broadest conception, the “cloud” can include popular consumer services such as Facebook, Twitter, YouTube, and Netflix. The rapid adoption of such services will continue to influence international traffic patterns as access to the major data centers used to deliver these services becomes more important. Some cloud services may only be located in major Internet hub cities due to the prevalence of more affordable power, space, and connectivity options, as well as more favourable regulatory environments.
Demand growth for services housed only in the major Internet hub cities will boost international traffic. However, other types of cloud services will only drive increased local demand requirements.
For example, data storage for financial establishments and enterprises may be legally required to reside within the institution’s home country, in which case no international traffic is generated. The impetus to push content closer to end-users serves as another countervailing factor against international traffic growth. In recent years, increased reliance on content delivery networks to move video content local caches has had a clear, dampening effect on long-distance Internet traffic growth.
In any case, all the indications show that we are at the threshold of the Zettabyte Era: despite the current economic recession, Cisco predicts that global IP traffic will experience a Compound Annual
Growth Rate (CAGR) of about 30% in the next 3 years, reaching 0.966 zettabytes/year by 2015 [3].
The seemingly insatiable appetite for bandwidth is being fuelled by the emergence of data-intensive end-user applications such as video streaming and mobile broadband, enabled by the massive amount of networked devices that are estimated to have surpassed the number of people on Earth.
The growth in traffic, however, does not correspond to an equal growth in service provider revenue,
as bandwidth for most new broadband applications has a lower price in €/bit [4]. Moreover,
additional resources come at the cost of rising power consumption and system size. Operators are therefore striving to respond to the pressures being exerted on network capacity in a way that reduces the cost per Gbit/s/km of transport CapEx and OpEx, and to do this in the most energyefficient and space-saving manner possible. The short-term road ahead seems obvious: 10G and 40G network assets must be efficiently leveraged by upgrading to compatible 100G channels to avoid fiber capacity exhaust and delay the deployment of new overlay networks for as long as possible.
3.2
Opportunities in next-generation high-performance computing (HPC) systems
HPC is probably the most bandwidth demanding application to date, as state of the art supercomputers are currently operating in the Petaflop range (e.g. IBM RoadRunner: 1.8 Petaflops,
Fujitsu K-computer: 10.8 Petaflop, IBM BlueWaters (2011): 20 Petaflops, IBM Sequoia: 10 Petaflops
Gb/s VCSELs. Today’s first ranked Top500 supercomputer, the K computer, actually consists of more
than 800 computer racks and an excess of 200,000 cables having a total length over 1,000 km [5].
Fuelled mainly by the transition of cabling from copper to high-speed optical in high-performance computers, and seeking lower connectivity costs and power consumption, the market is expected to grow to 466,000 units (FDR AOCs and lower speed) and $95 million by 2013 according to
LightCounting. On the other hand, it is estimated that given today’s standards, an Exaflop High
Performance Computer would require approximately 1 billion optical links per system. To address
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this urgent scaling issue, the leading HPC interconnect protocol (Infiniband) projects in its roadmaps
the need for 70 Gb/s data rate per channel by 2015 (Figure 5).
Figure 5 : Infiniband roadmap for bandwidth demands.
Power consumption and size appear as the main set of barriers in next‐generation Data Center (DC) and High‐Performance Computing (HPC) environments. The limited capacity and physical quantity of electrically wired interconnects is in contrast to the increased clock speeds and wiring densities inside machines, forming the main source of the bottleneck in information exchange across all hierarchical communication levels: rack‐to‐rack, backplane, chip‐to‐chip and even on‐chip. At the same time, parallelization in processing brings completely new requirements with respect to the traffic amounts that need to be exchanged within DCs and HPCs, essentially transforming computing into a reduce size networking environment. This reality has led to the accelerated penetration of the optical technology into short distance, inter‐ and intra‐rack transmission links of even less than 10
meters [8] to exploit the large bandwidth offered by optical transmission media [9].
Even so, data communication and power consumption are daunting issues in Data Centers and HPC environments. Predictions that were made back in 2008‐09 concluded that the 10 Pflops supercomputing machine of 2012 would require 5MWs of power and that the emergence of Exascale machines in 2020 will require a power of 20MWs, with 2020 datacom optics consuming 1mW/Gb/sec
[10]. These predictions were based on historical HPC industry trends that designated by that time a
10x increase in HPC computational power every 4 years, coming at the expense of 1.5x more cost and 2x more consumed power. Being in 2012, world’s current no. 1 Supercomputer reveals a situation even more dramatic than predicted: the K‐supercomputer has already reached the 10Pflops
performance, requiring however approximately 10MW of power [11] instead of the 5MW predictions
four years ago! This only implies that the use of optics at inter‐rack communication level is not enough for sustaining performance enhancements: Low‐energy photonic solutions have to penetrate at board‐to‐board and chip‐to‐chip data links, eventually also to intra‐chip, in order to avoid an explosion in energy consumption.
This statement was, however, early on recognized, as can be identified by the significant research efforts invested mainly in the US but also more recently in Europe in the field. A number of focused research initiatives, both in the US and Europe have highlighted the potential of optics when used in optochip and/or optical board‐level. The photonics roadmap for on‐board and board‐to‐board data communications has already proven its credentials to relax energy requirements while guaranteeing
high performance in data-center and HPC environments [12]. The main key challenge that has still to
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be tackled in order to release its massive adoption in commercial Printed Circuit Board (PCB) and optochip deployments is definitely cost, which is expected to be reduced with the choice of the proper technology platforms for each one of the possible applications.
3.3
Opportunities in next-generation data-centers
As already described in paragraph 3.1, new broadband applications are reshaping the Internet into a
content-centric network, causing the proliferation of data-centers. An example is real time event detection in video, which is used in applications such as surveillance, assisted care, and natural user interfaces. Incoming video is replicated to analysis modules, the results of which are sent to monitoring tasks that determine if an event is recognized. The data communication requirements between tasks are sharply different: the channels transmitting video data require much higher bandwidth than those transmitting results of the analysis tasks. Availability of high-speed access technologies like VDSL and FTTH has led to the mushrooming of many new web applications, from traditional search in online interactive maps to video streaming, social networking and cloud computing, with the vast majority of these WEB applications running in data-centers and offered free-of-charge.
More and more data is being stored in data centres for online use, leading to an increase in the number of data centres and the large number of servers in each one of them. The number of servers in the largest data centres is approaching 100,000, and there is increasing demand for bandwidth, particularly for applications such as video on demand, real time video processing, financial services,
medical imaging, storage and scientific computing [13]. Warehouse-scale mega-data-centers are
evidence of the evolution of the new internet paradigm with new data-centric applications like cloud computing, video streaming and social networking. For example, every second, 1.157 people begin watching a YouTube video. These social activities have lead to more than 500,000 data centers
worldwide [14]. Alongside the need to increase bandwidth there is growing awareness that power
consumption of computer networks cannot increase at the same rate as in the past, from the social
responsibility and cost perspectives in addition to power density management issues [15]. In 2006,
servers and data centres were estimated to consume 1.5% of the electricity in the US, doubling from
More recently data centres require faster access to stored data and we often find some storage colocated with compute nodes. However, for very large data sets and for back-up and redundancy, the data centre usually includes storage nodes, often disk arrays. In a supercomputer or data centre, data sets which can often be 100’s terabytes or petabytes in size must be transferred between computers from backing store to compute nodes. These transfers regularly take longer than the computation itself and limit application performance, especially when the compute node has limited
To cope with these requirements, optical technology has been put in the spotlight due to the unparalleled capacity of optical media. An accelerated penetration of optics into short-distance, inter- and intra-rack transmission links from a few centimeters to hundreds of meters or even a few kilometers has marked the new paradigm of optical interconnects.
More specifically, intra-rack (board-to-board) and inter-rack (rack-to-rack) communications are performed in modern data centers using active optical cables (AOCs). AOCs have been endorsed by many vendors in optical networking components (Finisar, Avago, Intel, Tyco and other.) currently
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focusing on the data center market. The projection for 2015 is that fiber will cover 60% of cabling in
data centers (Figure 6) [18] addressing a worldwide AOC market that will reach $1.9 billion [19].
AOCs are based on parallel optical links. They offer simple installation in harsh data-center environments and broad support to protocols such as Fibre Channel, Infiniband, SAS, and Ethernet.
Effort is put today on the design of AOC solutions that are capable of supporting high-rate applications such as 100 GbE, Fibre Channel ≥32G and InfiniBand ≥40G. However, in order to support these cumulative data rates, the available 10 Gb/s-grade parallel-optics technology requires data transmission across multiple fibers simultaneously and a multi-fiber cable assembly (or array) is required. Factory-terminated 12 fiber MPO connectivity in today's installations provides the means to migrate to this multi-fiber parallel-optic interface and MPO-terminated backbone/horizontal cabling is simply installed into pre-terminated modules, panels or harnesses. A higher number of parallel fibres, though, scale linearly the number and cost of terminations as well as the fiber cost itself. On the other hand, as providers resort to warehouse-scale mega data centers, there is a
growing need for larger ranges. In March 2011 [20] IEEE project was approved as standard 802.3bg, a
40 Gb/s serial single-mode optical fiber standard (40GBASE-FR). It provides a reach of 2 km through migration from “traditional” 850 nm datacom wavelengths to 1310 nm and 1550 nm.
Figure 6 : Copper to fiber transition in the data-centers: state of the short reach optics market in data-centers.
3.4
Opportunities in next-generation metro/regional networks
The traffic the metro area has to aggregate and route towards the Internet backbone is doubling every 3 to 6 months, is transported across multiple protocols, and is growing in complexity as new services proliferate. In addition, today's edge metro and access network designers must also tackle
Quality of Service (QoS) issues. With more data flowing through systems at faster rates and from different sources, designers must develop network architectures that ensure the proper distribution of data in order to guarantee that services are not lost or experience a bad quality. With this high level of functionality required, more bottlenecks are occurring and more headaches are arising in today's metro system architectures. The migration from current 10G and 40G systems to 100G
Ethernet based solutions (100 GbE) is believed to provide a drastic solution in terms of bandwidth availability, efficient utilizations and flexibility for the current regional and metro networks.
With the 100 GbE standard ratified in June 2010, commercial deployment of 100G solutions, based mainly on coherent technology, is currently gaining momentum. Departing from the established industry metric that technology shifts occur when 4x the bandwidth arrives at 2.5x the price (a 38.5% improvement in cost/bit), carriers have overwhelmingly indicated a willingness to adopt 100G
2013 at which point 100G will start to dominate core network traffic. But it’s not just long-haul links that need upgrading: 100 Mb/s VDSL2 and 1-10 Gb/s WDM-PON access technologies boosting enduser rates will start to stretch the capacity of sub-600km fiber links deployed in regional and
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metropolitan networks. Lower-cost, reduced-range coherent linecards based on 100G standard aimed at this market are starting to be commercialized by vendors such as Transmode and Ciena
[22], [23]. After taking over in long-haul applications, 100G wavelengths will start to appear in
regional and metro networks as well. Alternative (direct detect) approaches are also developed for this reduced-range applications aiming to offer lower complexity and cost.
Figure 7 : Estimation of the 100G coherent module market (millions of $) presented at ECOC 2011 by Opnext.
3.5
Opportunities in other applications
Finally, new consumer-based products are seeking high-speed connectivity that can be delivered only by AOCs like PC interconnects, HDMI interfaces for HDTV and home theatres to name a few. As onchip performance of electronics continues to surge, there is a pressing need for commensurate upgrades in interconnection bandwidth, while this is exacerbated by the paradigm of distributed processing and the huge amounts of data in high definition video. For example, 3D HDTV needs 36
Gb/s while the new standard UHDV reaches up to 500 Gb/s [24]. This new situation marks the
transition of AOCs to consumer electronics and paves the way for optics communications in highvolume consumer markets. Consumer products can sustain a thriving industry since -contrary to the
20-year life standard of telecom markets- they have a 3-year life cycle expectation. This is the reason why consumer devices currently dominate revenues and innovations in the electronics industry, and extrapolating this situation to a converged photonics/electronics technology can create a sustainable, mass market for high bandwidth AOCs and components.
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4.
Techno-economic analysis
The techno-economic analysis in this section presents the perspectives of the POLYSYS modules to
take advantage of the opportunities already presented in chapter 3, and to address:
the capacity
the simplicity and
the cost reduction needs that are emerging in the different parts of today’s datacom and telecom networks. The characteristics of the POLYSYS modules that may provide a comparative advantage with respect to other solutions are to a great extent due to the specific technologies that have been elected for the development of POLYSYS devices. These technologies include:
the EO polymers for implementing the optical modulators and for serving as the base of the photonic integrated circuits
the InP technology for the photodetectors and the photoreceivers of the systems, and
the InP-double heterojunction bipolar transistor (InP-DHBT) technology for the electronic processing systems (MUX, DEMUX and clock recovery circuit) and drivers.
In the first two paragraphs of this section, a brief description of the individual technologies is provided. In the third and final paragraph of this section, we make the comparison between the
POLYSYS modules and the competitive (state-of-the-art) approaches taking into account the specific characteristics of the POLYSYS modules owing to the POLYSYS material platforms and system architecture.
4.1
Electro-optic polymer platform as a novel photonic integration platform
Over the past 10-15 years, photonic integration technologies have been the true enabler of complex photonic circuits for the generation, processing or reception of optical signals in compact optoelectronic modules. In order to do this, photonic integrated circuits (PICs) combine passive photonic structures (waveguides, couplers, different kind of filters, polarization handling elements etc), optical sources, gain elements, nonlinear elements (mainly SOAs or Kerr elements), or photodetectors/photoreceivers.
The material systems that are considered for multi-functional PICs include today four main platforms:
(a) the silica-on-silicon platform, (b) the Indium Phosphide (InP) platform, (c) the silicon-on-insulator
(SOI) platform, and (d) the optical polymers. POLYSYS is driving a substantial extension to the potential of the polymer technology by highlighting the possibility of the EO polymers in particular to act as a new integration platform. Before explaining the advantages and the new possibilities that are introduced by the EO polymer system, we provide a brief description of the four material systems, which are dominant today:
(a) Silica‐on‐silicon system allows for the hybrid integration of semiconductor active components
3
modulators [26] and photoreceivers [25] with passive photonic circuitry. Its main
advantages are associated with the low‐loss, precise waveguides and the versatility to manufacture multi‐component circuits. Main disadvantages, however, are the purely passive nature of the material system, which necessitates the hybrid integration of every active or electro-optic element, and the low index contrast that demands thick waveguides and long bending radii reducing in this way the integration density of the final device.
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(b) InP monolithic integration has become a proven photonic integration system after the success of
Infinera [27]. The InP platform facilitates integration in a single process of DFB lasers, fast
modulators, receivers and passive components allowing for dense, multifunctional PICs. Its disadvantages are the high propagation losses in InP waveguides (approximately 0.5 dB/cm), the complex fabrication processes that result in rapidly dropping yields as circuitry complexity increases, and for the same reason, the prohibitively high development costs of the technology unless a large number of products can be guaranteed.
(c) SOI is a relatively new system for photonic integration. It has attracted great interest as the silicon photonic circuits can be built using standard CMOS processes enabling (at least in principle) common
fabrication process, and the high refractive index contrast between the materials of SOI platform that allows for narrow waveguides and high integration density. Main disadvantages are the high propagation losses (up to 1 dB/cm), the lack of a laser source at 1550 nm and the relatively low‐speed of currently available silicon modulators.
(d) Optical polymers have emerged as an alternative, extremely low‐cost photonic integration platform. Transparent organic molecules can be spinned on almost every substrate and can be engineered in order to present low losses (~0.1 dB/cm) and a wide range of refractive index contrasts that allow for integration densities that could be higher than the SOI platform. Moreover, specific molecules possess an extremely high EO coefficient and appear as the ideal candidates for compact,
ultra‐high speed optical modulators [29]. However until now the polymer planar technology has not
been exploited as a multipurpose integration platform and the majority of the demonstrations have
been related either to discrete modulator components [30] or purely passive structures [31]. In this
sense POLYSYS is the first structured effort that aims at proving the polymer system as a multi‐purpose, low‐cost photonic integration platform. In more detail:
POLYSYS is introducing the EO polymer platform as a new material system to serve as the basis for complex PICs. The main advantage of this platform is the intrinsic availability of electro-optic phase
and amplitude modulators of highest speed (>100 Gb/s) [30]. POLYSYS is further developing the
technical potential to monolithically integrate complex passives such as couplers and filters, either in the form of Bragg-gratings or unbalanced Mach-Zehnder modulators (UMZM). At the same time, the project is developing simple and cost-effective techniques to hybridly integrate lasers sources, gain elements or waveguide-integrated pin-photodiodes in order to provide the availability of the main building-blocks for ultra-fast transceivers for short-reach optical interconnects and metro applications. Certain advantages of the new platform are the ease in the modulation at speeds as high as 100 Gb/s and beyond, also it offers relatively low coupling loss (<1.5 dB) between the polymer waveguides and the InP elements (lasers and photodiodes). A specific disadvantage on the other hand is the high propagation losses in the EO polymer waveguides (approximately 1 dB/cm).
Efforts to design and develop further passive elements like for example polarization coupling elements and other filter structures (e.g. micro-ring resonators, AWGs) will further support the vision of using the EO polymers as a powerful, multi-functional integration platform.
4.2
InP technology for high-speed photodetectors and electronics
POLYSYS is also investing on InP semiconductor technology for the implementation of the high-speed photodetectors and the driving/processing electronics. A short overview of the competing
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technologies and of the advantages that the choice of InP entails for the POLYSYS technology is provided below:
InP photodetectors: InP is the natural choice of optical engineers and researchers for photodetectors in the 1550 nm wavelength range. The most common alternative is the SiGe detector technology, which was developed in order to be compatible with standard CMOS processing and silicon photonics. However, the bandwidth of the SiGe photodetectors is still limited and the maximum
speed they can have does not exceed 40 Gb/s [32]. Waveguide integrated InP photodetectors is in
turn the choice for devices that are capable of operation at ultra-high speeds (100 Gb/s or beyond).
Devices based on this approach have been demonstrated either in the form of passive pinphotodetectors or in the form of photoreceivers with built-in post-amplification employing travelling-
wave amplifiers (TWA) [33]. POLYSYS relies on this technology and aims to go a step further
increasing the bandwidth, the responsivity of the devices, and developing quad-arrays of these devices with 400 Gb/s total capacity.
InP electronics: Figure 8 presents the main technology platforms for high-speed electronics focusing
on their comparison in terms of transistor transition frequency and breakdown voltage. InP technology, and in particular InP-DHBT technology appears as the ideal platform, as it is capable of ultra-high speed operation and at the same time capable of high breakdown voltages. Hence, it is capable of withstanding or providing high voltage amplitudes, and such high amplitudes are necessary in driving further electronic or photonic systems, as it is the case with the polymer modulators in POLYSYS.
Transistor transition frequency
(GHz)
Figure 8 : Semiconductor technologies comparison
A significant disadvantage of the InP-DHBT technology compared to CMOS or BiCMOS technology is the higher cost and the higher power consumption of the circuits. In the case of the power consumption, comparisons tend to be positive for the InP-DHBT circuits if the power consumption is normalized with the supported data rates (W/bit). In the case of cost, CMOS electronics still have an advantage due to their large volume production. However, if the target is operation at ultra-high
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speed and cost reduction through the radical reduction of the number of electronic and photonic transceivers, then InP-DHBT appears as the only viable solution today.
4.3
Transceivers and systems operating directly at 100 Gb/s
In the present paragraph, a first techno-economic analysis of POLYSYS 100 Gb/s transceivers and systems is presented. The analysis is application-specific discriminating among the three main application areas of 100 GbE technology that POLYSYS is introducing at the physical layer:
the chip-to-chip interconnects for high-performance computing (HPC) systems (in 4.3.1)
the active optical cables for rack-to-rack interconnects (in 0)
the 100GbE links for metro and metro/regional applications (in 4.3.3).
The analysis is made on the basis of comparison with the 100 GbE alternative solutions for the same type of applications. Comparison regarding the cost-effectiveness of the POLYSYS approach is made by taking into account the number of components that are required in the different approaches and the cost of the different technologies. Cost estimation for the fabrication of components using the different technologies is made in the present report in a qualitative manner using the terms high/medium/low. The perspectives for cost reduction for some of these components with the commercialization and the adoption of products are also described. A similar analysis regarding the
energy efficiency of the different approaches is presented in chapter 5 of the present document.
4.3.1
Chip-to-chip interconnects
The first system of POLYSYS (System 1) is an ambitious solution for on-board, chip-to-chip interconnects in HPC systems and data-centers. The need for high-capacity interconnects that extend the throughput of conventional electrical interconnects by transferring high data volumes between processors or memory units that are located centimetres away, has already been described in
paragraph 3.2. POLYSYS explores the implementation of an EO polymer chip-to-chip optical link, as a
forward looking application of its technology. The link provides 100 Gb/s connectivity and is a few centimetres long.
Required number of photonic and electronic components : The POLYSYS chip-to-chip link is implemented using a 1550 nm DFB laser, an RF-driver that additionally provides the 2:1 MUX functionality, an optical modulator, a single-mode waveguide of a few centimetres on the EO polymer platform, a photodiode and a DEMUX circuit that provides at the other end of the link the two demultiplexed 50 Gb/s electrical streams.
Cost/complexity of material systems and technology : Compared to other photonic technologies for optical modulators, optical polymers have significant advantages in terms of time and simplicity for the wafer preparation and processing. The cost of polymer modulators is still high, but wide commercialization of polymer-based transmitter modules in telecom and datacom markets is expected to significantly reduce this cost. On the other hand, InP photodetectors represent in general an expensive technology both in terms of time for wafer processing and price. However, they are the only practical solution for high-speed photodetectors. Finally, InP-DHBT represents a semiconductor technology that has not been widely adopted yet, and that still has a high cost.
However, similar to the case of polymer modulators, further commercialization of products and large-volume fabrication is expected to reduce the InP-DHBT fabrication cost.
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Network system specification : From a system point of view, the serial solution proposed by POLYSYS is the easiest and most straightforward way to transmit high volumes of data without employing complex modulation formats or further electronic processing. It provides the solution with the minimum number of photonic components, and high data density in the waveguides of the optical board. The main disadvantage is the need for additional stages of electrical MUX/DEMUX stages, which however do not contribute significantly to the complexity or the power consumption of the system. Chip-to-chip (on board) interconnects should be able to support propagation lengths of a few tens of centimetres, and for this reason the waveguides should have appropriately low optical losses.
Passive polymer waveguides can have an optical loss as low as 0.1 dB/cm. The EO polymer platform has, however, a much higher optical loss in the range of 1 dB/cm. Thus, its use would be suited only for very short interconnects with a total length of a few centimetres. In this sense the development of SYSTEM 1 is exploratory in nature, and without direct commercialization perspectives, at least for a wide variety for on-board interconnects.
In the following paragraph, the characteristics of the main alternative solutions for the implementation of chip-to-chip interconnects are described. These solutions include at first place the use of passive polymer boards with a large number of parallel multi-mode waveguides in combination with VCSELs and silicon-based photodetectors. In more detail:
Table 1 : Comparison of POLYSYS system and state-of-the-art alternative for on-board optical interconnects.
PCB technology
Optomodule in Terabus
(by IBM)
EO polymer integrated interconnect (by POLYSYS)
Multi-mode passive polymer Single-mode EO polymer
Number of lasers/modulators
Number of photodiodes
24
24
1
1
Number of high-power RF-drivers
Modulation format
Line-rate (Gb/s)
Total capacity (Gb/s)
24
NRZ-OOK
20
480
1
NRZ-OOK
100
100
Reach (cm) <100 <10
Current cost of technology Low High
VCSEL and silicon photodiode arrays in combination with polymer boards: Large companies like
IBM have revolutionized the field of on-board optical interconnects by developing arrays of VCSELs and photodiodes that are interconnected through parallel, low-loss polymer waveguides. Systems that have been developed within the framework of Terabus project include systems of 24 channels,
each one supporting 20 Gb/s line rate for distances of a few tens of centimetres [34]. Complex
integration technologies including 3D integration techniques are involved in order to facilitate the
driving of the transceivers and enable compact and functional circuits. Table 1 summarizes below the
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main characteristics of the POLYSYS technology and the main characteristics of the state-of-the-art systems described above for high-speed optical interconnects, and reveals the comparative advantages/disadvantages and the overall potential of POLYSYS technology for this field.
4.3.2
Active optical cables for rack-to-rack interconnects
The second system of POLYSYS (SYSTEM 2) constitutes an ambitious solution for the development of a high-capacity active optical cable (AOC) for rack-to-rack-interconnects in HPC systems and data centers. The total capacity of the AOC of POLYSYS will be 400 Gb/s, far beyond the current state-ofthe-art, and the transmission reach will be able to reach a distance in excess of 1 km, limited thereafter by the chromatic dispersion of the 100 Gb/s data stream and the optical power budget of the system.
The development of an AOC with these characteristics is considered as the application that fits in the best possible way to the characteristics of POLYSYS technology and has the highest potential for use in near future implementations of HPC systems and data-centers . The main points associated with the combination of the characteristics of the POLYSYS system and the urgent needs of modern data-centers, which contribute to the exploitation potential of the system are listed below:
1) The continuous increase in the bandwidth needed for communication between the top-of-rack
(ToR) Ethernet switches and the Ethernet switches in the higher level of the fabric hierarchy [35].
This communication is now based on 10 Gb/s or 40 Gb/s links, but the need for upgrading these links to 100 Gb/s is already here. The reach of these links should be in the order of a few tens of meters.
2) The adoption of optical circuit switching schemes in parallel with the conventional electronic packet switching schemes that are used for the core part of the switching fabric inside data-centers.
This adoption is driven by the fact that the largest part of the traffic between the ToR switches and the switches at the higher layer corresponds to west-east traffic between servers in different racks.
Moreover, during the execution of specific tasks, there is the need for a massive transfer of data between specific sets of servers that can be best served by means of direct optical links with ultrahigh bandwidth. In these cases, a re-configurable optical circuit switch that is based on micro-electromechanical systems (MEMS) technology can set up within ms these direct links, serving as the core element of the optical circuit switch fabric and circumventing the need to pass these huge (elephant) traffic patterns through the electronic packet switch fabric. This arrangement is schematically shown
restricted to any bandwidth limitations, ultra-high bandwidth transceivers with a total capacity up to
400 Gb/s can be used at ToR switches in order to serve these elephant patterns. Moreover, as the
ToR switches that are interconnected through the MEMS switch may be located at physically distant locations of many hundreds of meters, the optical links should be able to exhibit this reach.
3) The fact that POLYSYS AOC achieves this high throughput (fundamental data rate 100 Gb/s and through space multiplexing 400 Gb/s) based on low-complexity OOK modulation formats (i.e. without multi-level formats or need for coherent detection schemes based on complex and energy expensive digital electronics.
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Figure 9
: Hybrid packet-circuit (HyPaC) network architecture proposed by project c-Through [36]. The optical
circuit switch network (lower part) co-exists with the electronic packet switch network (higher part) in a hybrid architecture. The optical circuit switch network supports massive exchange of data between servers in different racks through direct optical paths established by means of a large (usually MEMS-based) optical switch. These optical paths may have a length of several 100s of meters and the need for multiple 100 or even 400 Gb/s transceivers, and represent an excellent field for the exploitation of POLYSYS AOC technology. Schematic taken
Required number of photonic and electronic components : The AOC will rely on the use of serial 100
Gb/s NRZ-OOK modulation and the implementation of a space-division multiplexing (SDM) scheme using a lane of 4 parallel fibers and 4 input/output waveguides at its transceivers. More specifically, the system will have two 2x100 Gb/s transmitters, each one of them using two parallel MUX-DRV circuits and two parallel polymer modulators running at 100 Gb/s and feeding the two output waveguides of each module. At the other end of the system, a quad array of pinTWA receivers and
DEMUX circuits will enable the final recovery of the eight 50 Gb/s signals at the output ports of the receiver module. A single laser source will be responsible for feeding each pair of optical modulators through the use of a monolithically integrated 1:2 MMI coupler on each polymer board.
Cost/complexity of material systems and technology : As already described in the analysis for the
chip-to-chip interconnects in paragraph 4.3.1, the cost of polymer modulators, InP photodetectors
and InP-DHBT electronics is still high. However, the use of InP photodetectors is the only practical solution for high-speed photodetectors in the 1550 nm range. On the other hand, the cost of polymer modulators and InP-DHBT electronics is expected to drastically fall with broader commercialization of products based on these technologies (high volume production).
Network system specification : The simplicity of the serial solution for 100 Gb/s is given, and the extension to the 4x100 Gb/s through parallelization and use of four independent single-mode fibers
(SMF) is straight forward. The POLYSYS system does not require any means for optical multiplexing/demultiplexing or any means for digital signal processing (DSP) at the receiver side, which would be particularly unattractive for AOCs. The reach of the transmission is expected to be above 1 km without any means for dispersion compensation. This range of transmission reach is appropriate for most applications. Transmission distances in excess of 3-5 km that may be needed for specific inter-data-center applications of AOC will be difficult to be accommodated. Experimental testing with the actual devices will indicate the actual transmission reach limits, dictated by the chromatic dispersion and the optical power budget.
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In the following paragraphs, the characteristics of the main alternative solutions for the implementation of high-capacity AOCs are described. These solutions include at first place highly parallel solutions based on 10x10 Gb/s, 10x12.5 Gb/s or 12x12.5 Gb/s products using vertical cavity
surface emitting lasers (VCSELs) [37]-[38], 4x25 Gb/s products using DFB lasers and MZMs [39], and
very recently 4x25 Gb/s systems based on polarization multiplexing and 4-level pulse amplitude
modulation (4-PAM) [40]. In more detail:
Parallel solutions based on 10x10 Gb/s lanes: Companies like Finisar, Hitachi, Fitel Photonics
Laboratory [37]-[38] have already released products that are based on the integration of VCSEL and
photodiode arrays and the use of multi-mode fibers for interconnects in the range of 100 m. The number of the individual components (VCSELs, RF-drivers, PDs), but the cost of the silicon-based components is low, especially when 850 nm operation. Depending on the exact number and line rate of the parallel spatial channels, the total capacity may be up to 150 Gb/s, thus being able to support
Infiniband 12xQDR, 100G Ethernet, and other datacom and HPC applications.
Parallel solutions based on 4x25 Gb/s lanes:
100 GbE connectivity has been presented by Molex [39]
using a DFB laser at 1490 nm, a quad array of MZMs, a quad array of RF drivers, a quad array of InP photodetectors, four individual SMFs, and NRZ-OOK modulation format. The upgrade to the 25 Gb/s line rate represents a major step that results in a significant reduction in the number of components.
The use of external modulators and SMFs result in turn in a significant increase in the transmission reach, which can be in this case up to 4 km. The cost of the materials compared to the 10x10 Gb/s solution is higher, but compensated for by the significant reduction of the number of required components as explained above.
100 GbE connectivity based on a DP-4-PAM system: Very recently, research groups from Denmark and Germany introduced the combination of polarization multiplexing and higher order 4-PAM
modulation with VCSELs for optical interconnects with 100 m reach [40]. The solution requires only a
single driver, a single VCSEL and a single photodiode per polarization, but the polarization multiplexing/demultiplexing and the additional amplitude levels used to reach the total capacity of
100 Gb/s add in system complexity with impact also on cost, power consumption and ease in further scaling capacity using arrayed components.
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Table 2 : Comparison of POLYSYS system and main alternatives for high-speed AOCs for rack-to-rack optical interconnects.
10x10 Gb/s solutions
4x25 Gb/s solutions
DP-4-PAM
4x100 Gb/s
POLYSYS
Number of modulators
Number of photodiodes
Number of high-power
RF-drivers
10
10
10
4
4
4
2
2
2
4
4
4
Polarization mux/demux NO NO YES NO
Higher-order formats/
Additional processing
SMF
Line-rate (Gb/s)
NO
NO
10
NO
YES
25
YES
(comparators)
YES
25
NO
YES
100
Total capacity (Gb/s)
Reach (km)
100
0.1
100
<4
100
0.1
400
>1
Current cost of material technology
Very Low Low Very Low High
Table 2 summarizes above the main characteristics of the POLYSYS technology and the characteristics
of the alternative systems described above for high-speed optical AOCs, and it reveals the expected potential of POLYSYS technology to innovate in this application field.
4.3.3
Metro/regional networks
The third system of POLYSYS (System 3) aims to demonstrate an alternative solution for physical layer (PHY) implementation of 100 GbE in metropolitan area networks (MAN). As presented in
paragraph 2.3, the basis of this solution is the use of serial 100 Gb/s data transmission relying on
NRZ-OOK modulation format and electronic time-division (de)multiplexing (ETDM) stages in the electronic part of the transceivers. The first demonstration of a similar approach goes back to 2010, where 100 Gb/s transmission over a 42-km dispersion managed link was demonstrated as a field-trial using an InP travelling wave electro-absorption modulator (InP-TWEAM), an InP photodiode and InP-
DHBT electronics [41]. POLYSYS aims to reduce the cost and advance the performance, the reach and
the functionality of such a system by introducing the polymer technology for the optical modulator of the system, by investing on the hybrid integration of the laser source with the optical modulator, and by investing on the hybrid integration/co-packaging of the photonic with the electronic piece-parts of the transceivers.
The schematic of the 100 Gb/s transceiver has been presented in Figure 3. The transmitter part
consists of the polymer board, the electronic MUX-DRV chip which implements the 2:1 multiplexing and driving functionalities, and the gain chip, which constitutes together with the polymer Bragggrating the tunable laser source. The receiver part contains on the other hand the pinTWA receiver, the clock recovery unit and the 1:2 DEMUX unit. As illustrated, the transmitter has two 50 Gb/s data
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inputs and a 50 GHz clock input, while the receiver delivers the two recovered 50 Gb/s signals at the two output ports for further demultiplexing by the subsequent DEMUX stages of the system.
Required number of photonic and electronic components : The 100 Gb/s transceiver of POLYSYS represents the ideal solution as far as the number of photonic components is concerned, since it employs a single laser source, a single optical modulator and a single photodetector. The benefits in
terms of simplicity, power consumption (to be presented in detail in chapter 5), ease in use and
pigtailing costs are obvious. As far as the electronic components are concerned, the architecture of the transceiver requires again the minimum number of drivers and clock recovery units (only 1 in either case for 100 Gb/s operation). The module includes also a single 2:1 MUX (integrated with the modulator driver) and a single DEMUX, but in order to be compatible with 25 Gb/s electronic interfaces, it would require two additional 2:1 MUX circuits and two additional 1:2 DEMUX circuits.
Cost/complexity of material systems and technology : As already described in the analysis for the
chip-to-chip and rack-to-rack interconnects in paragraphs 4.3.1 and 0, the cost of polymer
modulators, InP photodetectors and InP-DHBT electronics is still high. However, the use of InP photodetectors is the only practical solution for high-speed photodetectors in the 1550 nm range. On the other hand, the cost of polymer modulators and InP-DHBT electronics is expected to drastically fall with broader commercialization of products based on these technologies (large volume production).
Network system specification : The simplicity of the serial solution for 100 Gb/s is given. The POLYSYS system does not require any means for optical multiplexing/demultiplexing or any means for digital signal processing (DSP) at the receiver side. On the other hand, the spectral efficiency of the system is relatively low, as the system is based on binary OOK modulation. The reach of the transmission is expected to be in the range of 80-100 km over dispersion managed links.
In the following paragraphs, the characteristics of the main alternative solutions for the implementation of 100 GbE systems for metro networks (transmission reach <200 km) are described.
These solutions include at first place the dual-polarization quadrature phase-shift keying (DP-QPSK)
100G, the return-to-zero differential phase-shift keying -3 amplitude shift keying (RZ-DPSK-3ASK), and the optical orthogonal frequency division multiplexing (O-OFDM) with non return-to-zero optical duobinary (NRZ-ODB) coding. In more detail:
DP-QPSK: DP-QPSK is the modulation format of choice for long-haul transport and can provide a
are concerned with regional distances shorter than 600 km, DP-QPSK is not considered as a cost
effective solution. Figure 10 presents the layout of a typical DP-QPSK transmission system revealing
the complexity of this system due to the use of polarization multiplexing and coherent detection, which adds by default in the complexity and the power consumption of the system. The optical part of the transmitter consists of two IQ-modulators (4 MZMs), which necessitate the use of 4 RF-drivers
(to be compared with the single modulator and the single driver of the POLYSYS system), while a polarization beam coupler (PBC) at the output of the transmitter takes care of the polarization multiplexing of the circuit. At the receiver side passive photonic components (polarization beam splitter-PBS and 90 o
optical hybrids) are responsible for the polarization demultiplexing and the driving of the optical components in the photodetector array (8 photodetectors in total). Although the optoelectronic components and the electrical circuits are 25 GHz components and can be fabricated using lower cost LiNbO
3
(modulators), lower bandwidth InP (photodetectors) and CMOS
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technologies (electronics), the total system cost and complexity from the use of a large number of piece parts is high. On the other hand, the spectral efficiency of the system is higher, the transmission reach is unlimited (within the scale of metro/regional networks), and the coherent detection gives the additional possibility for propagation without dispersion management.
Figure 10 : Coherent intradyne DP-QPSK system.
RZ-DPSK-3ASK: DPSK-3ASK can be implemented using standard 40G components, and can be combined with RZ pulse carving to increase the optical signal-to-noise ratio (OSNR) and the polarization mode dispersion (PMD) performance of the system.
Figure 11 : Direct Detect RZ-DPSK-3ASK transmission system.
Figure 11 shows a typical RZ-DPSK-3ASK system and reveals the significant reduction in the
complexity compared to DP-QPSK due to the non-coherent nature of the system. However, as the system involves both phase and (multi-level) amplitude modulation, complex encoding is required.
Moreover a second modulator is employed at the transmitter side for pulse carving, whereas at the receiver side, a delay interferometer (DI), three photodetectors, two direct detection receivers and the corresponding electronic decoder circuit are required, representing a significant increase in the complexity of the system compared to the simpler in nature serial 100 Gb/s transmission based on
NRZ-OOK. The spectral efficiency of the system can be higher, though, and the transmission reach can be in excess of 100 km.
OFDM with NRZ-ODB: Multi-carrier solutions can also be implemented using direct detection receivers and allowing low baud rates running over the individual carriers. Compared to single-carrier approaches, the system allows the use of low-bandwidth components but necessitates the use of longer arrays of modulators and receivers. This scheme can be combined with ODB to implement a
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100 GbE transmission solution with spectral efficiency up to 1 bit/s/Hz and transmission distances in
Table 3 : Comparison of POLYSYS system and main 100G system for metro-network links.
DP-QPSK RZ-DPSK-3ASK OFDM with ODB POLYSYS
Number of modulators
Number of photodiodes
Number of high-power
RF-drivers
Coherent detection
4
8
4
Yes
2
3
2
No
4
4
4
No
1
1
1
No
Overall system complexity
Achievable spectral efficiency (bits/s/Hz)
Very high
2
High
1
High
1
Very low
~0.2
Current cost of material technology
Low Low Low High
Further modulation formats can be used for the physical layer (PHY) of 100 GbE systems by exploiting different combinations of RZ and NRZ schemes, by using non-coherent approaches for QPSK systems
(resulting in DQPSK formats) or by using dual carrier approaches [42]. Table 3 summarizes below the
main characteristics of the POLYSYS system and of the alternative systems described above for 100
GbE metro links, and reveals the expected potential of POLYSYS technology to innovate in this application field.
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5.
Energy efficiency
As widely known and already described in section 3 of the present document, energy efficiency is a
characteristic of components, subsystems and systems with increasing significance in modern datacom and telecom systems. This significance is related to the fact that power consumption is in many cases the limiting factor for scaling throughput and functionalities. In the present section, we present an analysis of the power consumption that should be expected by the POLYSYS systems and modules.
5.1
Using high aggregation rates and minimizing the number of required transceivers
As it was mentioned in the analysis of section 4 in the case of cost, any reduction in the power
consumption of POLYSYS technology compared to alternative approaches should be expected to originate from the use of higher aggregation rates in POLYSYS links, and thus from the use of a lower number of optical transceivers. In the next paragraph, the power consumption of the three POLYSYS systems is estimated and compared to current approaches for 100G connectivity at board level, rackto-rack level and metro networks.
5.2
Estimation of power consumption of POLYSYS devices/systems: Comparison with state of the art devices/systems
The calculation of the power consumption in the present paragraph is based on the power consumption specifications of the individual electronic and optoelectronic building blocks of each transceiver device. In more detail:
5.2.1
100 Gb/s Integrated optical interconnect for chip-to-chip connectivity
System 1 of POLYSYS is a chip-to-chip interconnect for optical on-board connectivity, which operates directly at 100 Gb/s thanks to the availability (within POLYSYS) of high-speed optical and electronic
components. The main building blocks of System 1 were presented in paragraph 2.1 and include the
DFB laser, the MUX-DRV chip of the modulator, the polymer modulator with its bias thermal phaseshifter, the pin-photodiode, the TIA-DEMUX electrical circuit at the back-end of the photodiode, and the thermo-electric cooler (TEC) that is responsible for keeping the temperature constant within a
power consumption of System 1, according to the system specifications that have been defined by
POLYSYS partners within the project. As it is presented in this table, the total power consumption of the integrated optical link turns out to be approximately 8 W, and its normalized value 80 mW/Gbps.
Major part of the power consumption id due to the operation of the electronic components MUX-
DRV chip and TIA-DEMUX chip, as well as the operation of the TEC, and can be further minimized with the optimization of the design of these units.
ICT-POLYSYS 28 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
Table 4 : Power consumption of individual components and total system in-the-box (System 1)
DFB laser (W) 1
MUX-DRV chip (W)
Bias phase shifter of MZM
(W)
Pin-photodiode without
50 Ohm termination (W)
TIA-DEMUX (W)
3.8
< 0.02
0.02
Total power consumption
(W)
8
2.15
Normalized consumption
(mW/Gbps)
80
TEC (W) 1
Alternative solutions based on parallel optics and use of low power consumption drivers and VCSELs, are able to achieve approx. 20mW/Gbps with good performance margins. It is expected though that the potential for further optimization of POLYSYS components will allow to reduce the power dissipation and making the POLYSYS interconnects advantageous in specific applications.
5.2.2
4x100 Gb/s active optical cable for rack-to-rack interconnects
System 2 of POLYSYS is an AOC targeting at connectivity of 400 Gb/s total throughput between server racks placed up to 1-2 km away from each other. Compared to System 1, it represents the scaling in the number of components and the total throughput by a factor of 4. Different types of components are used however for the detection of light (pinTWA receivers) and the demultiplexing at the back-
end of the receivers (twin-DEMUX circuits). Table 5 summarizes the contributions of the individual
building blocks to the total power consumption of System 2, according to the system specifications that have been defined by POLYSYS partners within the project. For this system, the total power consumption is approximately 33 W, and its normalized value 82 mW/Gbps, i.e. similar to the case of
System 1. In this case, apart from the pure electrical components, the pinTWA receivers contribute significantly to the total power consumption due to the presence of the integrated TWAs.
Table 5 : Power consumption of individual components and active optical cable in total (System 2).
Single DFB laser (W)
2 x MUX-DRV chips (W)
2 x Bias of MZM (W)
1
2 x 3.8
2 x 0.02
Total power consumption
(W)
32.88
Single TEC (W) 1
2x100 Gb/s transmitter in total (W)
9.64
4 x pinTWA (W)
2 x twin-DEMUX (W)
4 x 2
2 x 2.8
Normalized consumption
(mW/Gbps)
(400 Gb/s throughput)
82.2
4x100 Gb/s receiver in total (W)
13.6
Alternative solutions based on parallel optics and use of low power consumption drivers and VCSELs, are able to achieve approx. 20mW/Gbps with good performance margins, however these solutions can support transmission distances in the range of only 300 m, thus excluding a large part of the possible applications that AOC may have in inter-rack communications.
ICT-POLYSYS 29 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
5.2.3
100 Gb/s transceiver for 100 GbE in telecom networks (metro/regional)
Finally, System 3 of POLYSYS is a novel design of 100 Gb/s transceiver for 100 GbE systems in metro network applications. The system includes the transmitter of System 1 with the additional functionality of wavelength tunability through the thermal tuning of the reflection peak of a polymer
Bragg-grating. At the receiver side of the transceiver, the clock recovery circuit is the additional element that allows for the operation of the receiver without the supply of the synchronized clock
from an external signal generator source. Table 6 summarizes the contribution of the individual
building blocks. The total power consumption is approximately 10 W and the normalized consumption approximately 102 mW/Gbps. The higher normalized power consumption in this case is due to the additional wavelength tuning possibility, which allows for adjusting the wavelength of the metro-link within a 17-nm range. This possibility is particularly attractive for flexible/reconfigurable
WDM metro network architectures.
In order to compare this power consumption level, one has to take into account the corresponding power consumption of a typical 100 GbE system based on DP-QPSK coherent technology, which is today in excess of 1000 mW/Gbps due to the exceptionally high power consumption of the ASIC circuits that implement the DSP processing after the coherent detection of the signal. The perspectives for improving the energy efficiency of the DSP circuits with the adoption of 40 nm
CMOS technology are good, but the normalized power consumption of POLYSYS approach should be still 7-8 times lower than the corresponding one in DP-QPSK systems.
Table 6 : Power consumption of individual components and tunable 100 Gb/s transceiver in total (System 3).
Laser including the tuning mechanism (W)
MUX-DRV circuit (W)
1.8
3.8
Total power consumption
(W)
10.22
Bias of MZM (W) 0.02 pinTWA (W)
DEMUX
Clock-recovery subsystem
(W)
TEC (W)
2
1.4
0.2
1
Normalized consumption
(mW/Gb)
102.2
ICT-POLYSYS 30 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
6.
Conclusions
The present deliverable has constituted an effort to systematically define the application areas that
POLYSYS technology may target at, and to provide an analysis of the advantages that POLYSYS technology may have in terms of simplicity, cost and power consumption compared to state-of-theart solutions.
The three application areas of POLYSYS include the chip-to-chip interconnects, the rack-to-rack interconnects and the metropolitan area network links, all of them experiencing significant growth and attracting intense research efforts due to the growth of capacity demands in all parts of communication networks, including data-centers and HPC systems. In all three cases, the availability of components of ultra-high speed allows for the use of high aggregate rates with obvious advantages in terms of simplicity and number of optical transceivers. Compared to alternative solutions, POLYSYS technology provides a straightforward evolution path that radically reduces the level of parallelism in current architectures and provides a viable evolution path for further scaling the throughput of systems.
Direct comparison of the envisioned POLYSYS devices with today’s commercial products would not be fair, as the cost of fabrication would be substantially higher for the POLYSYS main building blocks due to the limited commercial uptake of the respective technologies (polymer modulators, InP-DHBT electronics). It is expected though that further commercialization of products and large-volume fabrication will reduce this cost making the POLYSYS approach a most cost-effective one.
In terms of energy efficiency, the POLYSYS approach has a certain advantage compared to the alternative ones for metro networks. For chip-to-chip and rack-to-rack interconnects, the power consumption of POLYSYS systems is currently higher than what has been demonstrated by VCSEL based systems, however the POLYSYS approach offers extended reach beyond 1Km while VCSEL based optical links can only currently achieve up to 300m. The extended reach offered by the
POLYSYS approach is of particular relevance as the size of the data centers increases.
There are also a number of applications in which it is a plus to limit the number of optical fibers used for a particular link and in all these scenarios high speed serial links like those being developed in
POLYSYS are particularly attractive for the simplicity and reduced size.
Further progress on the techno-economic analysis of POLYSYS technology will be described in Year 3 deliverables. These are D7.4 (Standardization of POLYSYS integration technology and manufacturability plan) in M32 and D7.5 (Final plan for the use and dissemination of foreground) in
M36.
ICT-POLYSYS 31 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
References
[1].
POLYSYS Annex I - "Description of Work"
[2].
GLOBAL INTERNET GEOGRAPHY EXECUTIVE SUMMARY (2012), TeleGeography Research, www.telegeography.com
[3].
"Entering the Zettabyte Era," CISCO White Paper, June 1, 2011.
[4].
"Open IP Networks for Innovation and Profit: How Carriers, Content and Applications are Changing
Network Business Models to Add Value, Generate Revenue and Improve Efficiency," Juniper White Paper,
2010.
[5].
http://www.top500.org/
[6].
Dieter Bimberg, “Future Trends in Data and Computer Communication”, International Scientific Advisory board Skolkovo Foundation.
[7].
N. Ledentsov “Drivers of the market of electronic components: The increasing role of intrasystem links”,
Rusnanotech 2010 Forum, Moscow, November 1-3, 2010.
[8].
Y. Taira et al, “High Channel‐Count Optical Interconnection for Servers”, IEEE Proceedings of ECTC 2010,
Art. No. 5490959.
[9].
D. Qian et al, 101.7‐Tb/s (370×294‐Gb/s) PDM‐128QAM‐OFDM Transmission over 3×55‐km SSMF using
Pilot‐based sed Phase Noise Mitigation”, OFC2011, Paper PDPB5.
[10].
J. A. Kash et al, “Optical Interconnects in Exascale Supercomputers”, IEEE Phot. Soc. 2010 Proceedings
2010, pp. 483‐484.
[11].
http://www.datacenterknowledge.com/archives/2011/06/20/new‐top‐500‐champ‐the‐k‐supercomputer/
[12].
J.A.Kash et al, “Optical Interconnects in Future Servers ”, OFC 2011, Paper OWQ1
[13].
www.intel.com/research/platform/sp/hybridlaser.htm
[14].
http://www.cablinginstall.com/index/display/article-display/5320044184/articles/cabling-installationmaintenance/news/data-center/data-center-power-cooling/2011/12/Emerson-infographic-sizes-up-datacenters-in-2011.html
[15].
M. Glick, "Optical interconnects in next generation data centers: an end to end view" IEEE Hot
Interconnects 2008.
[16].
L. A. Barroso, J. dean, U. Holzle, “Web search for a planet: the Google cluster architecture” IEEE Micro,
March/April 2003, vol.23, N.2, pag.22-28.
[17].
“Report to congress on server and data center eEnergy efficiency”, US Envinronmental Protection Agency
ENERGY STAR, august 2007.
[18].
Lisa Huff, “State of the Short-Reach Optics Market”. OFC/NFOEC 2011, OMV5.
[19].
Global Information Inc., "Active Optical Cabling Markets: 2011 and Beyond" by Communications Industry
Researchers, Inc.
[20].
"IEEE P802.3bg 40Gb/s Ethernet: Single-mode Fibre PMD Task Force", IEEE 802. April 12, 2011. Retrieved
June 7, 2011.
[21].
The Fast Approaching 100G Era," Infonetics Research white paper, July 2010.
[22].
Transmode announces standards-based coherent 100G strategy for metro and regional networks ,"
Transmode press release, September 13, 2011.
[23].
Optical Connections Industry News - [Online] (2011, October): http://www.ecocexhibition.com/node/13456/bnr
[24].
N. Ledentsov “Drivers of the market of electronic components: The increasing role of intrasystem links”,
Rusnanotech 2010 Forum, Moscow, November 1-3, 2010
[25].
http://www.ict-apache.eu
ICT-POLYSYS 32 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
[26].
http://www.cablinginstall.com/index/display/article-display/5320044184/articles/cabling-installationmaintenance/news/data-center/data-center-power-cooling/2011/12/Emerson-infographic-sizes-up-datacenters-in-2011.html
[27].
V. Lal et al, “Multi-Channel Coherent PM-QPSK InP Transmitter Photonic Integrated Circuit (PIC)
Operating At 112 Gb/s Per Wavelength”, Postdeadline Paper PDPC7, OFC 2011, Los Angeles, CA,
USA.
[28].
http://www.helios-project.eu/
[29].
M.
Lee, H. E. Katz, C. Erben, D. M. Gill, P. Gopalan, J. D. Heber, D. J. McGee, “Broadband
Modulation of Light by using an Electro-Optic Polymer,” Science 298 , 5597, pp. 1401-1403,
November 2002.
[30].
Hao Huang, Jeng-Yuan Yang, Yang Yue, Yongxiong Ren, Scott R. Nuccio, Raluca Dinu, Devang
Parekh, Constance J. Chang-Hasnain, and Alan Willner, “100-Gbit/s Amplitude and Phase
Modulation Characterization of a Single-Drive, Low-Vπ Polymer Mach-Zehnder Modulator,”
Proc. OFC/NFOEC’12, OW4F.5 (2012).
[31].
J. Park, T. Lee, D. Lee, S. Kim, W. Hwang, Y. Chung, “Widely‐tunable Coupled‐Ring‐Reflector Filter
Based on Planar Polymer waveguide,” IEEE Photon.. Technol. Lett., vol. 20, 12, Jun 2008.
[32].
Papichaya Chaisakul, Delphine Marris-Morini, Giovanni Isella, Daniel Chrastina, Xavier Le Roux et al., “Ge/SiGe multiple quantum well photodiode with 30 GHz bandwidth,” Appl. Phys. Lett. 98,
131112 (2011); doi: 10.1063/1.3574539
[33].
http://www.hecto.eu/
[34].
C. L. Schow et. al., “A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical
Transceiver Module Based on a Single “Holey” CMOS IC”, IEEE/OSA J. Lightwav. Technol., vol. 29, no. 4, Feb. 2011.
[35].
Nathan Farrington et al, “Helios: A Hybrid Electrical/Optical Switch Architecture for Modular
Data Centers,” SIGCOMM’10, August 30–September 3, 2010, New Delhi, India.
[36].
Guohui Wang et al, “c-Through: Part-time Optics in Data Centers,” SIGCOMM’10, August 30–
September 3, 2010, New Delhi, India.
[37].
http://www.finisar.com/products/active-cables/C.wire
[38].
T. Tokoro et. al., “Engineering a 150 Gbit/s optical active cable to meet the needs of the data center environment”, in Proc. OFC 2011, 6-10 Mar. 2011.
[39].
http://www.molex.com/molex/products/family?key=quad_small_formfactor_pluggable_plus_q sfp_interconnect_solution&channel=products&chanName=family&pageTitle=Introduction
[40].
http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2012-PDP5D.10
[41].
J. Li, C. Schubert, R.H. Derksen, R. Makon, V. Hurm, A. Djupsjöbacka, M. Chacinski, U.
Westergren, H.-G. Bach, G.G Mekonnen, A.G. Steffan, R. Driad, H. Walcher, and J. Rosenzweig,
“112 Gb/s Field Trial of Complete ETDM System Based on Monolithically Integrated Transmitter
& Receiver Modules for Use in 100GbE,” Proc. ECOC’10, P4.03 (2010).
[42].
http://www.advaoptical.com/en/resources/white-papers/100gbe-the-future-of-ethernet.aspx
ICT-POLYSYS 33 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
List of Figures
ICT-POLYSYS 34 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
List of Tables
ICT-POLYSYS 35 D7.3 Report on applicability and techno-economic analysis of POLYSYS subsystems
