DC–DC converter without electrolytic capacitors for renewable
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IEEE TRANSACTIONS ON SUSTAINABLE ENERGY High Step-up Converter without Electrolytic Capacitors for Renewable Energy Applications Yihua Hu, Member, IEEE, Wenping Cao, Senior Member, IEEE, Bing Ji, Member, IEEE, Xiangning He, Fellow, IEEE, James Kirtley, Fellow, IEEE Abstract—Traditional electrolytic capacitors used in power converters are bulky, unreliable and short in their service life. This paper proposes the use of film capacitors in a high step-up DC-DC converter for renewable energy applications including photovoltaics and fuel cells. The converter is of a three-phase modular structure and six pulse rectifiers are employed to reduce the output voltage ripple. The primary side of the converter includes three interleaved inductors, three main switches and an active clamp circuit. Therefore, the input capacitor can be eliminated and the input current is greatly reduced. The zero voltage switching is achieved during the switching transition for all the active switches so that the switching losses can be reduced greatly. Magnetic energy stored in the leakage inductance is recovered and the reverse-recovery issue associated with diodes is effectively addressed by the leakage inductance of a built-in transformer. The proposed converter is justified by simulation and experimental tests on a 1000W prototype. Index Terms—DC-DC converter, electrolytic capacitor, fuel cells, modularization, photovoltaics, power loss. I. INTRODUCTION R ENEWABLE energy is high on the international and national agendas. Photovoltaics (PVs) and fuel cells are two prominent examples and their output is typically low voltage direct current (DC). In these applications, high step-up DC-DC converters with low cost and high reliability are highly desired [1]-[5]. However, large electrolytic capacitors are generally used at the front-end and the output terminal of the converter [2], in order to minimize the current and voltage ripples. These capacitors require galvanic isolation [7] and provide only a limited service life, especially in the PV microinverter at outdoor conditions [6]. Voltage gain is also a key performance indicator for DCDC converters. In the literature, a variety of isolated high stepup topologies to increase the voltage gain are reported [8]-[14]. Among these is an interesting concept of isolating inter-cell transformer and interleaved technology [14]. Nonetheless, due to its multi-cell structure, the bridge circuit suffers from a breakthrough risk and the voltage stress of switching devices is high on the high voltage side. In [15], a group of interleaved Flyback converters with three winding coupled inductors are developed but their current ripples are also high. Thereby new topologies are proposed in [16]-[17] to lower input current ripples while still achieving a high voltage gain. Their *** drawback lies in a need for an input capacitor (small) and an output capacitor (large). On the contrary, a symmetrical rectifier configuration is used [18] to decrease the output current ripple but the current ripple on the primary side structure is high. This work is set out to achieve the high voltage gain and low output ripples without the use of electrolytic capacitors, by proposing a new topology which combines the features of electrical isolation and modular structure so as to improve the reliability and cost-effectiveness. II. PRINCIPLE OF OPERATION The proposed three-phase interleaved converter without electrolytic capacitors is presented in Fig. 1, where S1, S2, S3 are the main switch devices, Sc1, Sc2 and Sc3 are clamp switches. The switch devices also form a three-phase bridge. The capacitor Cc and the switches Sxxx are employed to clamp the switch devices and to realize soft switching. For the three coupled inductors L1, L2 and L3, their primary windings are interleaved connected with each other and their secondary windings are star connected for a high output voltage gain. The winding turns of the coupled inductors are represented by n1 (primary) and n2 (secondary), respectively, and the turns ratio N is derived from n2/n1. The coupling reference of L1, L2 and L3 are marked with “*”, “○” and “□”, respectively. LLK1, LLK2 and LLK3 denote the leakage inductances of the coupled inductors; Do1-Do6 are the rectifier diodes; Co is the output filter capacitor. There are six operating stages during one switching period. The equivalent circuits for each stage are presented in Fig. 3 and explained in detail as follows. L3 * Vin Sc3 L3a n1 L2 L2a n1 L1 Sc2 Sc1 S3 S2 S1 L1b n2 n2 L3b Cc Do1 LLk1 L1a n1 Do3 Do5 L2b n2 Co LLk2 R V out * LLk3 Do2 Do4 Do6 Fig. 1 The proposed DC-DC converter without electrolytic capacitors. IEEE TRANSACTIONS ON SUSTAINABLE ENERGY L3a n1 L3 * Vin Sc3 L2 L2a n1 L1 L1b n2 n2 L3b Cc S3 LLk1 L1a n1 Sc1 Sc2 S1 S2 Do1 Do3 Do5 L2b n2 Co R Vout Co R Vout LLk2 * LLk3 Do2 Do4 Do6 Do1 Do3 Do5 (a) Stage 1 [t0~t1] L3 * Vin L3a n1 Sc3 L2 L2a n1 L1 Sc2 Sc1 S2 S1 L1b n2 n2 L3b Cc S3 LLk1 L1a n1 L2b n2 LLk2 * LLk3 Do2 Do4 Do6 Do1 Do3 Do5 (b) Stage 2 [t1~t2] L3 * Vin L3a n1 L2 L2a n1 L1 Sc3 Sc2 Sc1 S3 S2 S1 LLk1 L1a n1 L1b n2 n2 L3b Cc L2b n2 Co LLk2 R Vout * LLk3 Do2 Do4 Do6 (c) Stage 3 [t2~t3] L3 * Vin L3a n1 L2 L2a n1 L1 Sc3 Sc2 Sc1 S3 S2 S1 L1b n2 n2 L3b Cc Do1 LLk1 L1a n1 Do3 Do5 * Vin L3a n1 Co LLk2 R Vout * LLk3 L2 L2a n1 L1 Sc3 Sc2 Sc1 Do2 S3 S2 S1 Do1 LLk1 L1a n1 L1b n2 Do3 Do5 Co R Vout Co R Vout * Do2 Do4 Do6 Do1 Do3 Do5 (e) Stage 5 [t4~t5] L3 * Vin Sc3 L3a n1 Sc2 L2 L2a n1 Sc1 Cc S3 S2 L1 S1 LLk1 L1a n1 L1b n2 n2 L3b L2b n2 LLk2 * LLk3 Do2 Do4 Do6 (f) Stage 6 [t5~t6] Fig. 3 Six operating stages of the proposed converter. Vin Vout 1 D (t t1 ) LLK 1 (1) Vin Vout (2) 1 D iLK 2 iLK 2(t2 ) (t t1 ) LLK 2 By Kirchhoff’s current law (KCL), the current on the secondary side of L3 is given by (rewrite i3=) (3) iLK 3 iLK 1 iLK 2 0 LLk2 LLk3 iLK 1 N N Do4 Do6 L2b n2 n2 L3b Cc B. Stage 2 In this stage, the main switches S1 and S3 turn on and the active clamp switch Sc2 is in on state. At t1, the current in the primary of L1 and L3 increases whilst that of L2 falls below zero. During this stage, L1 and L2 work in forward mode, L3 works in flyback mode, and the rectifier diodes D02, D04 and D05 conduct. The secondary windings of L1 and L3 are series connected to charge the output for high voltage gain; these of L2 and L3 are also series connected to charge the output for lowering the output voltage ripple. The current in the secondary windings of L1 and L2 can be expressed by Eqs. 1 and 2. L2b n2 (d) Stage 4 [t3~t4] L3 A. Stage 1 Before t0, the main switch S1 and the clamp Switch Sc1 are in off state and the common clamp capacitor Cc is resonant with the leakage inductance of L1. From t0 onwards, the voltage of Sc1 increases from zero and zero voltage switching (ZVS) is realized on the clamp switch Sc1. The turn-on signal of the main switch S1 is given in this period when its parasitic diode is in on state, and S1 turns on with ZVS. Meanwhile, the main switch S2 turns off and its parasitic capacitor Cs2 is charged by the magnetizing current of L2. Due to its parasitic capacitance, the main switch S2 turns off with ZVS. In this period, the switching voltage of the main switch S2 reaches the level of Cc and the parasitic diode of Sc2 conducts. The voltage of the main switch S2 is clamped to the voltage of Cc. The primary-side current of L2 begins to decrease and that of L1 begins to increase. L2 and L3 work in forward condition and L1 in flyback condition. Corresponding rectifier diodes D01, D04 and D06 conduct. C. Stage 3 At t2, Sc2 turns off and the clamp capacitor Cs2 is resonant with the leakage inductance of L2. While the voltage across the parasitic capacitance of the main switch decreases, the voltage of Sc2 increases from zero, and ZVS is realized on Sc2. The turn-on signal of S2 is given when its parasitic diode is in on state and S2 turns on with ZVS. The main switch S3 turns off, and then its parasitic capacitor Cs3 is charged by the magnetizing current of L3. In this period, the voltage of the main switch S3 reaches the voltage of Cc and that of the main switch S3 is clamped to the voltage of Cc3. L1 and L2 work in forward mode and L3 works in flyback mode. The antiparallel diode of Sc3 and D02, D04 and D05 all conduct. The secondary windings of L1 and L3 are series connected to charge the output for a high voltage gain and these of L2 and L3 also series connected to charge the output and to reduce the output voltage ripple. IEEE TRANSACTIONS ON SUSTAINABLE ENERGY D. Stage 4 In this stage, S1 and S2 turn on; the active clamp switch Sc3 is in on state. At t3, the primary current of L1 and L2 increases while that of L3 decreases. The antiparallel diode of Sc3 conducts. In this interval, L1 and L3 are in forward mode and L2 in flyback mode. The secondary windings of L1 and L2 are series connected to charge the output capacitor Co through D02 and D03 and these of L3 and L2 are series connected to charge Co through D03 and D06. The secondary currents of L1 L3 and L2 are thus given by Eqs. 4,5 and 3, respectively. V N in Vout (4) 1 D iLK 1 iLK 1(t3 ) (t t3 ) LLK 1 iLK 3 N Vin Vout 1 D (t t3 ) LLK 3 (5) State 4 [t3-t4]: At t3, S1 turns OFF and S3 turns ON, which turns Do2 ON. The primary side of coupled inductor L1 charges the battery by S3. During this state, L2 operates in the Forward mode and L1 operates in the Flyback mode to transfer energy to the load. When S1 turns ON and Do2 turns OFF, a new switching period begins. In mode 2, the battery transfers energy to the load, as shown in Fig. 44(a). It indicates the nighttime operation of the standalone system. The circuit works as the Flyback-Forward converter, where S3 and S4 are the main switches, Cc, S1 and S2 form an active clamp circuit. When the load is disconnected, the standalone system enters into mode 3. The PV array charges battery without energy transferred to the load due to the opposite series connected structure of coupled inductor, as shown in Fig. 4(b). S1 and S2 work simultaneously and the topology is equivalent to two paralleled buck-boost converters. E. Stage 5 The clamp switch Sc3 turns off at t4. Then Cc is resonant with the leakage inductance of L3. The voltage across Sc3 increases from zero and ZVS is achieved on Sc3. S3 is turned on when its parasitic diode is on and S3 is on with ZVS. At t4, S1 turns off, and then its parasitic capacitor is charged from the magnetizing current of L1. In this period, the switching voltage of S1 is clamped by Cc; L1 and L3 are in forward mode; and L2 is in flyback mode. Furthermore, the second sides of L1 and L2 are series connected to charge Co through D02 and D03 and these of L2 and L3 are also series connected to charge Co through D03 and D06. Vgs1 Vgs1 Vgs3 Vgs2 Vgs4 Vgs2 Vgs2 Vgs1 iL2a iL1a iL1a iL2a ib iS1 vds1 vds1 iS1 vDo2 vDo2 iDo2 iDo2 t0 t2 t1 t4 t3 Fig. 3 Signal waveforms of the proposed converter under mode 1. Cs1 S1 Cs3 Do **************. Cs2 S2 S4 L Lk Do1 Co1 n2 + + - (1) (2) State 3 [t2-t3]: At t2, S2 turns ON, which makes the two coupled inductors work in the Flyback state to store energy again, and Do2 is reverse-biased. The energy stored in Co1 and Co2 transfers to the load. At t3, the leakage inductor current decreases to zero and diode Do1 turns off with zero-current switching operation. S3 + VB n2 n1 * Do2 • * Vo - Cs4 L1 L2 Co2 (a) Mode 2 Cs1 S1 Cs2 S2 Cs3 Do S4 L Lk Do1 Co1 n2 + + Cc - S3 n1 * (a) [t0-t1] - n1 NVB 1 D N VB N (VB ) D D Vpv Vab Cc Vpv According to the voltage balance law, DVPV (1 D)VB Ro L1 Ro + VB Vo - Cs4 n1 • L2 n2 * Do2 Co2 (b) Mode 3 (b) [t1-t2] Fig. 4. Converter operating modes. (c) [t2-t3] III. PERFORMANCE ANALYSIS AND FEEDBACK LOOP DESIGN (d) [t3-t4] Fig. 2 Four operating states of the proposed converter in mode 1. In order to realize flexible energy flow, the modulation strategy is proposed by combing PWM with PS. Firstly, the iL1a iL1a iL2a iL1a iL2a t t IEEE TRANSACTIONS ON SUSTAINABLE ENERGY (a) Case 1: 0<φ<φ crit1 1S1 S33 Case 3: φ crit2<φ<φ crit3 (c) D S1S1 1 S22 S44 t Case 2: φ crit1<φ<φ crit2 (b) D with duty ratio and FS needs to be relationship of voltage gains S S S researched. In the following analysis, S1 andS S2 share the same S S duty ratio, D, meanwhile, S3 and S4 are applied to the same duty ratio. The gate signals for S1 and S3 are complementary, as well V as for S2 and S4. 2 iL2a S33 S S2 φ S1 S2 S2 SS 4 4 φ NVB/D NVB/D ab Vab iLk t A. Analysis of Circuit Performance (D>0.5) When the duty cycle D>0.5, there are five operating cases i i for analysis, as shown in Fig. 5. t In case 1, the phase shift angle is between 0 and φcrit1. From (d) inductor Case 4: φ current, <φ<φ the waveform of the leakage the secondary side of the coupled inductor is equivalent to a discontinuous conduction mode (DCM) of a Buck converter. When φ=φcrit1, the current pulses A and B is in a boundary conduction mode. iLk t L1a iL1a L2a iL2a crit3 D S1S1 S4 φ Fig. 5. Five operational cases for D > 0.5. For pulse A, the current decreases to the minimum value and increases to zero during the time period of (1-D)Ts, The D D S S S S S decrementStime is equal Sto Tscrit1 / 2 andSthe incrementS time S1 1S1 S4 φ S2 SS 44 (a) Case Case 1: 1 0<φ<φ (a) L2a S4 φ S2 S2SS22 S S133 S SS22 crit2 S33 crit3 1 1 1 33 1 4 S4 2 2 4 4 2 NVB/D NV NV B/D B/D Vab crit2 S22 4 φ NVB/D crit1 D S1S1 S1 SS 44 S4 S 4 t 2: φ <φ<φ Case 3: φ <φ<φ TheCase secondary side of the coupled inductor(c)is equivalent to D S S two Buck converters connected in parallel SSat the DCM SS S S S S SS S S ratio S operational condition. The corresponding equivalent duty φ φ of the buck converter is φ/2π. According to NVthe/D equation of voltage gain of Buck converter in DCM, the output voltage can V be expressed as: (b) crit1 D S33 S1S1S t L1a iL2a t S1 NVB/D Lk iL1a iL2a S4 S4 ab iLk iL1a S1 S33 S22 4 φ NVB/D t SS 44 1S1 1 S 44 is (1 D crit1 / 2 )Ts . Following the voltage-second balance V (3), the critical phase angle can be determined in (4). Vo NVB crit1 Ts t (1i D crit1 )Ts D 2 2 2 (3) Vout i crit1 D (1 i D) t N VB (4) Vab iLk S33 S S33 S22 NVB/D Vab D S1S1 (e) Case 5 Case 5: φ crit4<φ<2π (e) crit4 S33 S S22 S t Vab B Vab ab iLk iLk iLk t t iL1a iL1a t t : 0<φ<φ crit1 D S33 S1 S S4 S 4 Case 2: (d) φ2 (b) Case S S133 S SS 44 S4 φ D S1S S1 1 SS22 SS 44 iLk S4 S4 S2 S4 2 φ Vab iLk t t t t t iL2a (a) φ <φ<φ crit2 d)crit1 Case 4: φ crit3<φ<φ crit4 i S4 S 4 S2 SS 4 4 φ S33 SS 1 S33 φ crit2 S33 33 S22 1S1 11 2 2 S 44 S33 t V NV B crit1 o (1 D) DLk 2 2 Lk (c) Case 3: φ Case 2: φ crit1<φ<φ crit2 Case 5: φ crit4 <φ<2π 2 33 iLk t t iL1a Lk L1a t (d) Case 4 t crit2 <φ<φ crit3 1 2 4 4 B (d) Case 4: φ crit3<φ<φ crit4 Case 5: φ crit4<φ<2π (7) (8) S S In case 3, the PS angle ranges from φcrit2 to φcrit3. SThe duty SS S S ratio of the secondaryS sideφ equivalent Buck converter stays constant at the value of 1-D, and the voltage gain stands the NV /D V highest, therefore, the critical point, φcrit3, and the corresponding voltage can be expressed as Eqs. 9 and 10. With i the increase in PS angle, the voltage declines. φcrit3 is t the boundary point between DCM and CCM. In this case, the i output voltagei cannot be controlled by PS angle, as shown in t Eq.11. 5: φ <φ<2π crit 3 (e) 2Case crit 2 (9) ab (e) t iL2a D S1S1 NVB/D t S4 S4 NVB/D NVB/D L1a Vab iL2a S1 S22 4 t SS22 iL2a t crit4 crit3 t (b) (e) iLk t iLk NVB/D Vab NVB D t V NV t B (1 D) o crit 2 DLk i 2 Lk 2 S1 S2 S2 t (c) Case 3 D S1S1 S 4 2 Lk 1i 1 2 R T o s ( / 2 ) / 2 i ab Case 1: (c)0<φ<φ Casecrit1 3: φ crit2<φ<φ crit3 D S1S1 S2 iL2aL2a 2 (5) t In case 2, the phase shift angle is between φcrit1 and φcrit2. (e) Case 5: φ <φ<2π Case 3: φ <φ<φ The(c) phase shift angle φcrit2 is the boundary point from D DCM, which can be continuous conduction mode (CCM) to SS SS S S S S S S S determined by (6). The voltage equation at φcrit1 and φcrit2 can SS S S φ be expressed as (7) and (8). NV /D V 4 (1 D) N VB crit 2 D Vout (6) iL1a iL1a iL1a iL2a iLk t L2a B Vab iLk iL1a iL1a φ Vab t t 4 4 NVB/D NVB/D NV B/D NV B/D Vab SS22 DD S1S S11S1 S1 S33 S S1 S33 S S4 φ S22 S Case 4: φ crit3<φ<φ crit4 crit1 <φ<φ crit2 (b) D S1S1 iL2a iLk L1a iL1a iL2a iL2a Vo 2 t L2a crit4 2 IEEE TRANSACTIONS ON SUSTAINABLE ENERGY D SS1 SS33 SS22 φ V D NVB / D (1S1 D) o (1 SS1crit 3 ) Lk 2 Lk 2 iLk S4 φ S2 SS44 2 Vo 2 4 2 Lk Vab Ro Ts (1 D) 2 / 2 1 1 NVB/D Vab SS33 1 (10) SS22 φ NVB D 1 3 2 4 B B iLk Vo 2 4 2 Lk Ro Ts (1 / 2 )D2 / 2 (14) SS2 B. Analysis of Circuit Performance (D<0.5) SS4 φ Similarly, there are five operating cases when the duty cycle D<0.5. The respective waveforms are shown in Fig. 6. 2 4 Vab D SS1 SS33 SS22 φ iLk tt S4 φ S2 (b) case 2: φcrit1 (c)(a) case 3: φ <φ<φ crit2 crit3 case 1: 0<φ<φ (c) Case 3 crit1 DD SSS1 SS11 S42 S SSS S3333 S1 S4 φ SS44 φ SS22 D D S SSS111 S4 φ SS1 1 SS44 SS22 NVB/D NVB/D S4 SS22 SS44 Lk iiLk t t (b) 2:4:φφcrit1 <φ<φcrit2 (d)case case crit3<φ<φ (d) Case 4 crit4 D SS11 φ SS22 SS44 (e) case φ (c) case 3: φ5: crit2 S1 SS33 S4 S4 NVB/D NVB/D Vab SS33 D SS1 S1 SS22 SS44 SS33 SS22 S4 φ iLk S1 SS4 4 t t NVB/D NVB/D (e) (e) caseCase 5:Vφcrit4 5 <φ<2π ab <φ<φcrit4 (d) case 4: φVcrit3 Vab φ Vab ab iLk iLk S1 S3 SSS 3 NVB/D Vab Vab tt D SS1 S1 SS44 iLk NVB/D Vab crit1 SS33 SS33 SS22 S4 φ S2 iLkiLk t NVB Dcase (e) φcrit4<φ<2π (a) case 1: 5: 0<φ<φ SS1 SS4 4 SS44 NVB/D In case 5 (φcrit4 <φ<2π), the duty ratio of secondary side equivalent Buck converter is 1-φ/2π. The output voltage can be expressed as iiLk Lk (d) case 4: φcrit3<φ<φ 1 crit4 1 SS22 S4 SS22 φ D SS1 SS11 VV abab VVabab t2 SSS3S333 NVB/D 3 2 4 Vab SS44 (11) In case 4, the PS angle ranges from φcrit3 to φcrit4. The leakage inductor current is still higher than zero before next iLk voltage pulse. φcrit4 is the boundary point between DCM and t CCM. The voltage gain stands as the highest, therefore, thecrit2 (b) case 2: φcrit1 <φ<φ case 1: 0<φ<φcrit1 critical(a) point, the critical point φcrit4 and the corresponding D D voltage can be expressed as Eqs. 12 and 13.SSSD1 SS S1 SS1 S11 SS333 SS3 2 SS2 SS4 SS4 SS22 crit 4 S4 crit1 SS2 SS4 (12) 4 φ φ φ crit 4 Vo NV (1 ) (1 D) NV /D NV 2 /D DLk 2 Lk (13) 1 DD SSSS11 S1 NVB/D ab Fig. 6. Five operating cases under D < 0.5. iLk iLk t (a) case 0<φ<φ (a) 1: Case 1 crit1 SS33 DD SSSS11 S1 SS44 S4 φ S2 SS3SS 333 SS44 SS22 S1S1 SS22 φ SS44 NVB/D NVB/D 1 S4 NVB/D t (b) case(b) 2: φcrit1 <φ<φ 2 crit2crit4 (d) case 4:Case φcrit3<φ<φ 0<φ<φcrit1 SS33 D SS11 S1 SS22 crit3<φ<φcrit4 S4 S1 SS33 φ SS44 SS22 S4 NVB/D NVB/D Vab iLk t t (e) case 5: φcrit4<φ<2π 4 B VabVab iLk iLk 3 2 Vab Vab t For case 1 (0<φ<φcrit1), considering the waveform of the iLk leakage inductor current, t the secondary side of coupled inductor equivalent to a DCM Buck converter, the (b) case 2: φcrit1is<φ<φ crit2 (c) case 3: φcrit2<φ<φcrit3 corresponding duty ratio is D=φ/2π. D D Vo 2 S SS1 SS11 SS3 SS33 1 S1 D crit1 N VB S4 SS22 SS4 SS44 SS2 S4 (15) φ φ NVB 2 Vo 2 NV /D NV /D B D 4 2 Lk 1 1 2 Ro Ts ( / 2 ) / 2 (16) In case 2 (φcrit1<φ<φcrit2), the current of leakage inductor is still above zero beforet next pulse coming. The system t equations can be expressed as (c) case(e)3:case φcrit2<φ<φ 5: φcrit4crit3 <φ<2π N VB crit 2 4 Vo (17) Vo NVB crit1 D DLk 2 2 Lk (18) iLkiLk t V NVB D o crit 2 DLk 2 Lk 2 (19) In case 3 (φcrit2<φ<φcrit3), the duty ratio of secondary winding equals to D. The system equations are t IEEE TRANSACTIONS ON SUSTAINABLE ENERGY crit 3 2 crit 2 (20) V NVB D o (1 crit 3 ) DLk 2 Lk 2 2 Vo 2 1 1 4 2 Lk Ro Ts D 2 / 2 Vpv (21) Vo 2 MPPT loop Vo In case 5 (φcrit4<φ<2π), the duty ratio of secondary winding can be expressed as 1-φ/2π. The output voltage is 2 4 2 Lk 1 1 Ro Ts (1 / 2 ) 2 / 2 NVB D (25) From the above analysis, the duty cycle D is the control variable to balance the PV voltage and battery voltage, and φ is employed to control secondary output voltage. The twofreedom control approach makes the solar energy, battery and load fully controllable. One condition should be applied to achieve decoupled control performance, which can be expressed as 0<φ<φcrit2 and φcrit3 <φ<2π. If the condition is not satisfied, the secondary output voltage is determined by the switching duty cycle rather than the phase shift angle, as presented in Eqs. 11 and 22. In mode 1, the primary side is equivalent to an interleaved Buck-Boost, which operates in the continuous conduction mode due to the asymmetrical complementary operation of the switching devices (S1, S3) and (S2, S4), and the operation of the second side follows Buck converter, where the corresponding duty ratio can be controlled by phase shift angle except for case 3. C. Feedback Loop Design (D>0.5) In mode 1, S1 and S3 complementarily conduct, and the on/off operation of S2 and S4 is complementary. When the output energy of PV array is lower than the load power, the battery should supply the required energy to sustain output power. The primary side of the proposed converter can be equivalent to a bidirectional buck-boost converter, while the secondary side can be equivalent to a Buck converter in discontinuous conduction mode. The maximum power point tracking (MPPT) can be implemented by adjusting duty cycle of switching devices. The output voltage can be controlled by PS of the primary side bridge arm, which can be approximated to adjust the duty cycle of Buck converter of secondary side to realize output voltage regulation. The control block diagram of the proposed three-port converter for PV-battery hybrid power generation system is illustrated in Fig. 7. C S1 S3 C S2 S4 0.8· Vpv_open NVB D (22) In case 4 (φcrit3<φ<φcrit4), the current of leakage inductor is still above zero. The system equations can be expressed as crit 4 2 crit1 (23) crit 4 Vo NVB (1 ) D DLk 2 2 Lk (24) PI Phase Shift PI Vo_ref φ Output voltage control loop Fig. 7. Diagram of the proposed control scheme. In the MPPT loop, the PV voltage can be regulated to follow the optimal operating point, which is initially assigned to 80% of the open circuit voltage of the PV array. The optimal operating point can be determined by the outer MPP Tracker, which has been broadly investigated in prior works [34]. The PV voltage regulation loop is an effective feature to improved MPPT performance as claimed in [35]. In the output voltage control loop in Fig. 7, the phase angle is the control variable. The phase angle of the carrier waveform for modulation is shifted to realize output voltage loop control. The mode can be switched smoothly by the proposed control method because of the block diode of PV input, mode 1 can be transferred to mode 2 by changing D>0.5 to D<0.5, furthermore, the mode can be switched from 1 to 3 by controlling the phase shift angle between S1 and S2. IV. SIMULATION AND EXPERIMENTAL RESULTS Both simulation and experimental test are conducted to evaluation the proposed system and control scheme. The system parameters for evaluation are listed in Table I. TABLE I PARAMETERS OF THE PROTOTYPE CONVERTER Parameter Do1-Do2 S1-S4 N = n1:n2 Cc Switching Frequency Battery voltage Load resistance Co1-Co2 Step-up ratio Product/Value BYW99W200 FDP047AN 1:2 100V/100μF 20KHz 12V 90Ω 250V/470μF 6.25 A. Simulation Results Simulation is carried out in PSIM environment to establish the relationship of phase shift angle and output voltage, and to testify the proposed control strategy in MPPT and output voltage control. Fig. presents the simulation results indicating the phase shift angle control and output voltage response at D>0.5 and D<0.5. The voltage gain can be divided into five cases which coincide with the theoretical analysis. In case 1, 2, 4, and 5, the output voltage is controllable by the phase shift while in case 3, the output voltage cannot be controlled by phase angle, as in IEEE TRANSACTIONS ON SUSTAINABLE ENERGY Eqs. 11 and 22. When D<0.5, the relation becomes more linear than that for D>0.5. Case 1 Case 2 Case 3 Case 4 Case 5 80 70 Vo(V) 60 50 40 30 operation enters mode 2. In mode 3 (Fig. 13), S1 and S2 are applied with the same duty ratio without a phase shift angle. Therefore, the energy is transferred only from the PV array to the battery. The output voltage becomes zero due to the reverse series connection of the second side of the coupled inductor. Fig. 14 illustrates the measured converter efficiency. It can be seen that the maximum efficiency of this converter is 91.3% at 200W and the rated efficiency is approximately 90%. 20 0 50 100 150 200 250 300 350 400 iin 10A/div Phase shift angle (°) (a) D > 0.5 Case 1 Case 2 Case 3 60 Case 4 Case 5 iLK 2A/div 50 Vo(V) 40 30 iB 10A/div 20 10 (a) Case 1 (φ=30°) 0 0 50 100 150 200 250 300 350 400 iin 10A/div Phase shift angle (°) (b) D < 0.5 Fig. 8. Simulation results for phase shift angle control. B. Experimental Results The proposed inverter topology and control scheme are implemented in a 250W prototype (see Fig. 9) with a Texas Instruments TMS320F28335 controller. Experimental tests are conducted with a PV array simulator (Agilent Technology E4360A) to obtain the steady-state waveforms of the proposed converter in different operating cases. Fig. 10 illustrates waveforms of the input current (iin), battery current (iB) and the second side of the coupled inductor current (iLK), for the phase angle shift under different cases. Fig. 11 shows the regulation performance of the converter. Using the phase shift modulation, the output voltage is controlled at the constant 80V level. Meanwhile, the duty cycle control of PWM regulates the PV voltage at 12.8V, which represents the operating point of MPP of the PV array simulator. Controller iLK 2A/div iB 10A/div (b) Case 2 (φ=120°) iin 10A/div iLK 2A/div iB 10A/div (c) Case 3 (φ=180°) iin 10A/div iLK 2A/div Load iB 10A/div Battery (d) Case 4 (φ= 240°) Fig. 10. Current waveforms for different cases (D >0.5 mode 1). Converter Uout (50V/div) Source iLK (5A/div) Fig. 9. Experimental setup of the proposed converter test system. Modes 2-3 are also tested with the results presented in Figs. 12 and 13. Fig. 12 shows the current waveforms with the phase shift for different cases when D<0.5. Under this condition, the battery discharges energy to the load and the blocking diode prevents the reverse current into the PV array. The converter UPV (10V/div) 20μS/div (a) Output voltage 100 IEEE TRANSACTIONS ON SUSTAINABLE ENERGY 95 Efficiency (%) Uout (50V/div) iB (5A/div) UPV (10V/div) 85 80 100 150 200 250 Power (W) 20μS/div (b) PV voltage 90 Fig. 14. Experimental results for the converter efficiency. Fig. 11. Experiment results of voltage regulation performance. step-up capability interfacing the PV array, the battery storage, and the isolated consumption. Three operating modes are V. CONCLUSIONS analyzed and have shown the effective operation of the This paper has presented an isolated three-port DC-DC proposed topology for PV applications. converter for standalone PV systems, based on an improved From simulation and experimental test results, it can be seen Flyback-Forward topology. The converter can provide a high that the output voltage and the PV voltage can be controlled i (10A/div) i (10A/div) i (10A/div) by the phase shift and PWM respectively. independently The decouple control approach is a simple and effective way to i (2A/div) achieve the regulation of output voltage and PV voltage, which is important for the MPPT operation of standalone PV power i (2A/div) i (2A/div) systems. In addition to developing simulation models, a 250W i (10A/div) i (10A/div) i (10A/div) converter is prototyped and tested to verify the effectiveness of the proposed converter topology and control scheme. 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