AN1872
APPLICATION NOTE
AVOIDING MOSFET FAILURES DURING START-UP IN DC-DC
BUCK CONVERTERS FOR COMPUTER POWER SUPPLIES
M. Melito, G. Belverde
1. ABSTRACT
This application note aims at describing how a failure mechanism can occur during the start-up
sequence in a dc-dc buck converter working in a multiphase power supply for motherboard.
Investigations have been done due to random failures of high-side MOSFETs experienced by a
customer. A failure mode test has been done in order to simulate customer application setup and
problem understanding. The last paragraph explains how to avoid these failures.
2. INTRODUCTION
The microprocessors recently introduced in the market, demand high current power supply together with
very low output voltage level. Buck converters are the most used ones for this kind of applications and a
very low Ron MOSFET replaces the schottky diode. In order to provide high load current, multi phase
converters are used. A dedicated controller performs the synchronization between each phase and
between the high and the low side MOSFET of each single phase.
The designer has to take particular care in choosing the power switches, the driver, the controller and the
layout to maximize the efficiency and to avoid the possibility that cross conduction occurs, due to the high
voltage slew rate during switching. The last MOSFET generation has reached the goal of being very
rugged against the dV/dt stress by optimizing the Cgd/Cgs ratio but it can happens that in a particular
condition this ruggedness seem not to be enough. The converter fails even if the applied stress is well
inside the guaranteed maximum ratings.
This work aims at understanding some converter failures during start-up sequence related to a 3-phase
VRM model using distributed driver stages with discrete controller and driver, but the obtained results are
of more general validity.
February 2004
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3. PROBLEMS DESCRIPTION
Fig. 1 depicts the simplified schematic showing the converter power stage. It is worth notiicing that Vdd
Power identifies the power source of the VRM; the voltage supplying the control circuitry, referred to as
Vdd Logic and whose value is 6.1V, is obtained through a series regulator implemented with discrete
components.
Figure 1: Simplified Schematic
At start-up, when power is supplied to the converter, Vdd Power increases, as fig.2 shows, due to the
charging of the input capacitors. During this phase, i.e. until the supply voltage reaches the under voltage
lockout, the control circuitry should keep low both the high side gate and the low side one; after that the
high side device should be allowed to start switching with 180° phase shift with respect to the low side
one. The Vdd Power rise should not have any consequence on the gate voltage of the high-side switch.
On the contrary in the examined situation it happens that the Vdd Power rise greatly affects the
measured voltage of the high-side switch.
In fact despite the dV/dt is relatively low (less than 20V/mS), a gate-source voltage appears on the high
side switch, see figure 2. It represents a dangerous condition and it happens because the equivalent
gate-source impedance is not low enough to limit the voltage partition to a safe value. This is due mainly
to two causes: firstly the Cgd/Cgs ratio is close to 1 because of low VDS implied, see figure 3. Secondly,
according to the specifications reported in the data-sheet regarding the undervoltage lockouts, during the
start-up phase both the driver and the controller should remain OFF. The power switches should remain
OFF too. In the examined case this is not true: the control part of the converter seems not working
correctly thus leaving the source pins of the high-side switch connected by impedance not low enough or
even floating.
As a consequence there is a time interval (200 µs) when the high-side gate-source voltage is above the
threshold voltage. So the high side MOSFET realizes a low impedance path (see fig. 1) between the Vdd
Power bus (voltage is rising) from one side and the output capacitors (discharged) and the µP from the
other one. Series inductance L1 is unable to limit current so this can be a reasonable source of stress
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and failure for the MOSFET and the µP.
Figure 2: Waveform during Test
Figure 3: Typical Power MOSFET Capacitance Ratio as a Function of Drain-To-Source Voltage
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Figure 4: Start-up Waveforms with and without Gate Resistance
4. HOW TO AVOID FAILURES
We suspect that the driver may leave the MOSFET gate floating for the time duration of start-up; due to
the intrinsic capacitances of drain and gate, a current injection from drain to gate may occur that
increases the gate voltage until the MOSFET is turned ON. Placing a 3.3 KΩ resistor between gate and
source, in the high-side switch, could check the above hypothesis. Fig 4 summarizes the resulting startup waveforms with and without such resistor. It is to be observed that the value of RGate inserted is
enough to realize a dynamic connection of the gate to the source.
5. CONCLUSIONS
The failure of the high-side MOSFET and, consequently, of the processor in the main board is believed to
be caused by the driver; the solution envisaged may be to use another driver solution being able to force
the gate voltage of the high-side MOSFET to zero during start-up. In order to avoid failures in this
kind of applications, a resistor between gate and source is recommended.
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