Comparative Analysis of Single Stage CMOS
Operational Amplifier in Gate Driven and Bulk
Driven Mode
Abhishek Tiwari1, Varsha Bendre2 , Sheetal Bhandari3
abhishek.abhisandilya@gmail.com1, varshabendre22@gmail.com2, sheetalubhandari@gmail.com3
Department of Electronics and Telecommunication Engineering1, 2, 3
Pimpri Chinchwad College of Engineering, Pune, India 1, 2, 3
Abstract—This paper presents a comparative analysis for the design
of a single stage CMOS operational transconductance amplifier. The
motive behind applying input from the bulk terminal is to reduce
power consumption. Moreover, due to continuous downscaling of
CMOS technology, the threshold at the gate terminal has not
reduced with the rate at which the supply voltage is reduced.Due to
this, input at the gate terminal becomes equal to or more than the
supply voltage which further violates the condition of saturation. To
overcome this problem, input has been applied from the bulk
terminal rather than the conventional gate terminal. This results in
lower unity gain bandwidth under the same load condition.
However, when load condition is lessened, unity gain bandwidth
improves. The OP-AMP has been designed for gain-bandwidth of
greater than 5MHz and gain of 40 dB. The load applied at the output
is 10 pF. In gate driven mode, the design after simulation exhibits a
unity gain bandwidth of 6 MHz and gain of 37 dB with 880 positive
phase margin. In bulk driven mode, the design after simulation
exhibits a unity gain-bandwidth of 2 MHz and gain of 28 dB with
800 positive phase margin. Computer aided simulation analysis is
shown for each simulation. Designs have been carried out on
backend tool of mentorGraphics using tsmc 0.18 um CMOS
process and 1.8V power supply. Schematic simulations have
been carried out using “Pyxis Schematic” and simulations
have been done using “Eldo”.
Keywords—Analog Circuit, Low Voltage Low Power, Single
Stage CMOS Operational Amplifier, Transconductance.
I. INTRODUCTION
Over the last few years, the electronics industries have
exploded. Operational amplifiers are key elements in analog
processing systems. Operational amplifiers are an integral
part of many analog and mixed-signal systems. As the
demand for mixed mode integrated circuits increases for low
voltage low power opertion, the design of analog circuits such
as operational amplifiers (op-amps) in CMOS technology
becomes more critical [1].
Single stage CMOS operational transconductance amplifiers
play a very important role in the analog circuit design because
of their excellent performance as input amplifiers and the
straightforward application with the possibility of feedback to
the input. The classical single stage amplifier faces the
limitations of the nonlinearity of the transfer characteristic,
especially for large values of the differential input voltage
amplitude. The single stage amplifier circuit characterizes in
terms of self-bias capability, common-mode rejection, voltage
gain, and the gain-bandwidth product. In this paper, single
stage non conventional bulk driven operational
transconductance amplifier has been proposed and it has been
compared with its conventional gate driven counterpart on
various performance parameter. The need for applying input
from the bulk terminal is to reduce power and make the
circuit compatiable for low voltage low power operations.
II. OUTLINE OF PAPER
This paper is organized as follows. Section II presents the
single stage CMOS amplifier. Section III reviews the
comparision of single stage CMOS op-amp schematic design
in gate driven mode and bulk driven mode. Its specifications
are clarified and the formula or calculations for design of
single stage CMOS op-amp are briefly elaborated. Section
IV presents the separate simulation results for different
analysis. Section V focuses on comparative analysis of
performance parameters for gate driven and bulk driven
mode. Finally section VI ends with the conclusion and
future work.
III. SINGLE STAGE CMOS OPERATIONAL
AMPLIFIER
The single stage operational transconductance amplifiers are
one of the most versatile circuits used in analog circuits
design. These are widely used in the electronics industries
and are generally preferred over their single-ended
counterparts because of their better common-mode noise
rejection, reduced harmonic distortion, and increased output
voltage swing[1,2,3]. Single stage amplifiers are used to
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amplify analog as well as digital signals, and can be used in
various implementations to provide an output from the
amplifier in response to differential inputs. It is also very
compatible with integrated circuit technology and serves as
the input stage to most of operational amplifier [3,4,5,6,7].
They can be readily adapted to function as an operational
amplifier, a comparator, a sense amplifier and as a front-end
buffer stage for another circuit.
The single stage amplifier is often a building block or subcircuit used within high-quality integrated circuit amplifiers,
linear and nonlinear signal processing circuits, and even
certain logic gates and digital interfacing circuits. In recent
years, there has been an increasing demand for a system-onchip configuration (SOC) and reduction of power
consumption, in response to which the CMOS has been
widely used [4,8,9,10,11].
CMOS operational amplifiers are used for various
applications because a number of advantages can be derived
from these types of amplifiers, as compared to single-ended
amplifiers. Operational amplifiers are used where linear
amplification having a minimum of distortion is desired. A
fully single stage operational transconductance amplifier
circuit is a special type of amplifier that has two inputs and
one output. This device amplifies input signals on the two
input lines that are out of phase and rejects input signals that
have a common phase such as induced noise.
Fig.2 shows the schematic of a single stage CMOS
operational transconductance amplifier with an N-channel
input pair in bulk driven mode. In this circuit, the entire
operation remains the same as that of conventional gate
driven amplifier. However, the only difference is that input is
applied from the bulk terminal and channel is kept in strong
inversion region by connecting the gates of transistor M1 and
M2 to desired power supply.
IV. SINGLE STAGE CMOS OP-AMP SCHEMATIC DESIGN
A. GATE DRIVEN MODE
Fig.1 shows the schematic of an single stage CMOS
operational transconductance amplifier with an N-channel
input pair in gate driven mode. The inputs are applied to the
gate terminals of transistors M1 and M2 and their bulk
terminals are connected to ground in order to avoid body
effect. Transistors M3 and M4 are acting as current mirror
load. Transistors M5 and M6 are playing the role of
mirroring NMOS and biasing NMOS.
Fig: 2 Single Stage Op-Amp in Bulk Driven Mode
C. FUNDAMENTAL IMPLICATIONS
Listed below are the specification of custom design for single
stage operational transconductance amplifier. The same
specification is used in gate driven mode as well as in bulk
driven mode.
I: Custom Design Specification for Single Stage Op-Amp
Specification Names
Supply VDD
Gain
Gain Bandwidth
Power Dissipation
Slew Rate
ICMR (Max)
ICMR (Min)
Load
Process
Values
VDD= 1.8V
>= 40dB
>= 5MHz
=< 3m watt
5V/ µs
1.6V
0.9V
10 pF
0.18m
D. DESIGN METHODOLOGY
The transistors M1 and M2 are perfectly matched and always
work in saturation region. The behaviour of large signal
analysis is given as
Fig: 1 Single Stage Op-Amp in Gate Driven Mode
B. BULK DRIVEN MODE
VID = VGS1-VGS2 = (2iD1/ β)1/2 – (2iD2/ β)1/2 .......….(1)
and IDS1 = iDS1 –iDS2………………………………(2)
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So,
2
+ Iss/2 (βV ID/Iss -
β2V4ID/4I2ss)1/2 ……….......(3)
2
Iss/2 - Iss/2 (βV ID/Iss -
β2V4ID/4I2ss)1/2 … …...…..(4)
iDS1 = Iss/2
iDS2 =
Phase margin are calculated using DC operating point and
AC analysis.
The values given to implement AC-analysis are
• Start Frequency = 1 Hz
• Stop Frequency = 10 MHz
The above relationships are only useful for
VID < 2 (ISS/ β)1/2 .
The transconductance of the amplifier is
gm = (K1’ISSW1/4L1 )1/2 ……………………..………(5)
.
It is interesting to note that as ISS is increased , the
transconductance also increases.
E. Design Parameters
MODEL N NMOS , LEVEL : 53
+VERSION = 3.1 , TNOM =27 , VTH0 = 0.3725327
TOX = 4.1E-9 , NCH = 2.3549E17
VOFF = -0.0927546 , VSAT = 9.41167E4
MODEL P PMOS, LEVEL :53
+VERSION = 3.1 , TNOM =27 , VTH0 = - 0.3948389
TOX = 4.1E-9 , NCH = 4.1589E17
VOFF = -0.0942201 , VSAT = 1.910163E5
V. SIMULATIONS RESULTS
A. GATE DRIVEN MODE
1. DC Analysis
In DC Analysis , region of operation of circuit is determined .
Here in single stage operational transconductance amplifier ,
each transistor must be in saturation region. During DC
analysis, all AC relevant parts i:e capacitor, inductor etc are
set to zero. This analysis is important for producing
characteristics transfer curve.
3. Transient Analysis
During transient analysis , first an initial operating point is
calculated (based on DC values) and after that all momentary
voltages and current are computed as the results of a time
dependent non well behaved input voltage or current source
including the influence of capacitors
4. Tabular Analysis of Performance Parameters for Gate
Driven Mode
Mode
Gate
Driven
2. AC Analysis
In AC analysis we determine Phase margin, Gain and unity
gain bandwidth of the operational amplifier. Both Gain and
Tran.
Noise
900
nV
Gm
Gain
PM
35.14
uA/V2
37
dB
+ve
880
B. BULK DRIVEN MODE
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Power
Dissi.
126 u
Watt
GBW
6
MHz
1. DC Analysis
4. Tabular Analysis of Performance Parameters for Bulk
Driven Circuits
Mode
Bulk
Driven
Tran.
Noise
300
uV
Gm
32.33
uA/V2
Gai
n
28
dB
PM
+ve
800
Power
Dissi.
116 u
Watt
GBW
2
Mhz
V. COMPARATIVE ANALYSIS
Comparative Analysis of Parameters for Gate Driven and
Bulk Driven Mode.
2. AC Analysis
3. Transient Analysis
Operation
Mode
Trans
.
Noise
Gm
Gain
PM
Power
Dissipation
Gain
Band
Width
Gate
Driven
900
nV
35.14
uA/V2
37
dB
+ve
880
126 u
Watt
6
MHz
Bulk
Driven
300
uV
32.33
uA/V2
28
dB
+ve
800
116 u
Watt
2
Mhz
VI. CONCLUSION
We have made comparative analysis for singles stage CMOS
operational transconductance amplifier in gate driven mode
and bulk driven mode without any change in specification . In
both the mode, analysis is done with respect to its behaviour.
Simulation results confirm that there are definitely some
limitations in bulk driven mode as compared to gate driven
mode in terms of performance parameter. So, there is a need
of innovative topologies for its design in bulk driven mode so
that the resultant behaviour in bulk driven mode could
compete with performance parameters in gate driven mode.
The feasible topologies would be boon for low voltage low
power operations especially in medical applications for
remote areas and rural areas where power cut is major
problem .
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