STV9555
9.5 ns TRIPLE-CHANNEL HIGH VOLTAGE VIDEO AMPLIFIER
FEATURES
above is required, ensuring a maximum quality of
the still pictures or moving video.
Perfecly matched with the STV921x ST
preamplifiers, it provides a highly performant and
very cost effective video system.
Triple-channel video amplifier
Supply voltage up to 115 V
80V Output dynamic range
Perfect for PICTURE BOOST application
requiring high video amplitude
Pinning for easy PCB layout
Supports DC coupling (optimum cost saving)
and AC coupling applications.
Built-in Voltage Gain: 20 (Typ.)
Rise and Fall Times: 9.5 ns (Typ.)
Bandwidth: 37 MHz (Typ.)
Very low stand-by power consumption
Perfectly matched with the STV921x
preamplifiers
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DESCRIPTION
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PIN CONNECTIONS
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CLIPWATT 11
(Plastic Package)
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The STV9555 is a triple-channel video amplifier
designed in a 120V-high voltage technology and
able to drive in DC-coupling mode the 3 cathodes
of a CRT monitor.
The STV9555 supports PICTURE BOOST
applications where video amplitude up to 50V or
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ORDER CODE: STV9555
OUT1
OUT2
OUT3
GNDP
VDD
GNDS
GNDA
IN3
VCC
IN2
IN1
Version 4.0
September 2003
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1
Table of Contents
1
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9
INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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10 APPLICATION HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1
How to choose the high supply voltage value (VDD) in DC coupling mode . . . . . . . . . 12
10.2
Arcing Protection: schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.3
Arcing protection: layout and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.4
Video response optimization: schematics in DC-coupling mode . . . . . . . . . . . . . . . . . 14
10.5
Video response optimization: outputs networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.6
Video response optimization: inputs networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.7
Video response optimization: layout and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.8
AC - Coupling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.9
Stand-by mode, spot suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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10.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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11 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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STV9555
1
BLOCK DIAGRAM
OUT1 GNDP
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8
OUT2
10
OUT3
9
STV9555
VDD
GNDP
VDD
GNDP
VDD 7
VCC 3
VREF
6
1
GNDS
2
IN1 GNDA
IN2
PIN DESCRIPTION
Pin
Name
1
IN1
2
IN2
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Video Input (channel 2)
IN3
Video Input (channel 3)
GNDA
Ground Analog
GNDS
Ground Substrat
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GNDP
Function
Video Input (channel 1)
Low Supply Voltage
VDD
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IN3
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VCC
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High Supply Voltage
Ground Power
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OUT3
Video output (channel 3)
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OUT2
Video output (channel 2)
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OUT1
VIdeo output (channel 1)
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3
STV9555
3
ABSOLUTE MAXIMUM RATINGS
Symbol
4
Parameter
VDD
High supply voltage
120
V
Low supply voltage
16.5
V
VESD
ESD susceptibility
Human Body Model (100pF discharged through 1.5KΩ)
EIAJ norm (200pF discharged through 0Ω)
2
300
kV
V
IOD
Output source current (pulsed < 50µs)
80
mA
IOG
Output sink current (pulsed < 50µs)
80
mA
VIN Max
Maximum Input Voltage
VCC + 0.3
V
VIN Min
Minimum Input Voltage
- 0.5
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-20 + 150
°C
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Symbol
Junction-Case Thermal Resistance (Max.)
Rth (j-a)
Junction-Ambient Thermal Resistance (Typ.)
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Parameter
Rth (j-c)
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3
Unit
VCC
THERMAL DATA
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Value
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Value
Unit
3
°C/W
35
°C/W
STV9555
5
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Typ
Max
Unit
SUPPLY parameters (VCC = 12V, VDD = 110V, Tamb = 25 °C, unless otherwise specified)
VDD
High supply voltage
20
110
115
V
VCC
Low supply voltage
10
12
15
V
IDD
VDD supply current
VOUT = 50V
15
mA
IDDS
VDD stand-by supply current
VCC : switched off (<1.5V)
VOUT: low (Note 1)
60
µA
ICC
VCC supply current
VOUT = 50V
40
mA
STATIC parameters (VCC = 12V, VDD = 110V, Tamb = 25 °C)
DC outpout voltage
VIN = 1.90V
High voltage supply rejection
VOUT = 50V
0.5
Output voltage drift versus temperature
VOUT = 80V
15
Output voltage matching versus
temperature (Note 2)
VOUT = 80V
1
Video input resistor
VOUT = 50V
VSATH
Output saturation voltage to supply
I0 =-40mA (Note 3)
VSATL
Output saturation voltage to GND
G
LE
VOUT
dVOUT/dVDD
dVOUT/dT
d∆VOUT/dT
RIN
VREF
77
80
83
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mV/°C
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V
mV/°C
kΩ
VDD - 6.5
V
I0 =40mA (Note 3)
11
V
Video gain
VOUT = 50V
20
Linearity error
17 V<VOUT<VDD-15 V
Internal voltage reference
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5.6
8
%
V
Note 1: The STV9555 goes into stand-by mode when Vcc is switched off (<1.5V).
In stand-by mode, Vout is set to low level.
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Note 2: Matching measured between each channel.
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Note 3: Pulsed current width < 50µs
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STV9555
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
Min.
Typ
Max
Unit
DYNAMIC parameters (see Figure 1)
tR
Rise time
VDC=50V, ∆V=40VPP
8.3
ns
tF
Fall time
VDC=50V, ∆V=40VPP
10.3
ns
5
%
OSR
Overshoot, white to black transition
OSF
Overshoot, black to white transition
∆G
Low frequency gain matching (Note 4)
0
%
VDC = 50V, f=1MHz
5
%
BW
Bandwidth at -3dB
VDC=50V, ∆V=20VPP
37
MHz
tSET
2.5% Settling time
VDC=50V, ∆V=40VPP
15
ns
CTL
Low frequency crosstalk
VDC=50V, ∆V=20VPP
f = 1 MHz
50
CTH
High frequency crosstalk
VDC=50V, ∆V=20VPP
f = 20MHz
32
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OSPB
VDC=50V, ∆V=60VPP
Rise/fall time
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Overshoot white to black or black to white
VDC=50V, ∆V=60VPP
transition
Note 4: Matching measured between each channel.
dB
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DYNAMIC parameter in PICTURE BOOST condition (Note 5)
tPB
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12
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9
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Note 5: PICTURE BOOST condition (video amplitude at 50V or above) is used in some applications when displaying
still picture or moving video. In this condition the high level of contrast improves the pictures quality at the
expense of the video performances (tR, tF and Overshoot) which are slightly deteriorated.
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Figure 1. AC test circuit
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VCC
12V
110V
3
7
VDD
VDC
OUT RP = 200 Ω
1
11
IN
8
VREF
STV9555
CL=8pF
GNDP
5
GNDA
∆V
STV9555
6
THEORY OF OPERATION
6.1
General
The STV9555 is a three-channel video amplifier supplied by a low supply voltage: VCC (typ.12V) and a
high supply voltage: VDD (up to 115V).
The high values of VDD supplying the amplifier output stage allow direct control of the CRT cathodes (DC
coupling mode).
In DC coupling mode, the application schematic is very simple and only a few external components are
needed to drive the cathodes. In particular, there is no need of the DC-restore circuitry which is used in
classical AC coupling applications.
The output voltage range is wide enough (Figure 2) to provide simultaneously :
– Cut-off adjustment (typ. 25V)
– Video contrast (typ. up to 40V),
– Brightness (with the remaining voltage range).
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In normal operation, the output video signal must remain inside the linear region whatever the cut-off,
brightness and contrast adjustments are.
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Figure 2. Output signal, level adjustments
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VDD
(A) Top Non-Linear Region
Linear region
15V
Blanking pulse
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(B) Cut-off Adjust. (25V Typ.)
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(C) Brightness Adjust. (10V Typ.)
(D) Contrast Adjust. (40V Typ.)
Video Signal
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(E) Bottom Non-Linear Region
17V
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STV9555
6.2
Output voltage
A very simplified schematic of each STV9555 channel is shown in Figure 3.
The feedback network of each channel is integrated with a typical built-in voltage gain of G=20 (40k/2k).
The output voltage VOUT is given by the following formula:
VOUT = (G+1) x VREF - (G x VIN)
for G = 20 and VREF = 5.6V, we have
VOUT = 117.6 - 20 x VIN
Figure 3. Simplified schematic of one channel
VDD
40k
2k
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IN
OUT
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VREF
GNDA
GNDP
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STV9555
7
POWER DISSIPATION
The total power dissipation is the sum of the static DC and the dynamic dissipation:
PTOT = PSTAT + PDYN.
The static DC power dissipation is approximately:
PSTAT = (VDD x IDD )+ (VCC x ICC)
The dynamic dissipation is, in the worst case (1 pixel On/ 1 pixel Off pattern):
PDYN = 3 VDD x CL x VOUT(PP) x f x K (see Note 6)
where f is the video frequency and K the ratio between the active line and the total horizontal line duration.
Example:
for VDD = 110V, VCC = 12V,
IDD = 15mA, ICC = 40mA,
VOUT = 40 VPP, f = 35MHz,
CL = 8pF and K = 0.72.
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We have:
PSTAT = 2.13 W and PDYN = 2.66 W
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Therefore:
PTOT = 4.79W.
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Note 6: This worst thermal case must only be considered for TJmax calculation. Nevertheless, during the average life
of the circuit, the conditions are closer to the white picture conditions.
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STV9555
8
TYPICAL PERFORMANCE CHARACTERISTICS
VDD=110V, VCC=12V, CL=8pF, RP=200Ω, ∆V=40VPP, unless otherwise specified - see Figure 1
Figure 4. STV9555 pulse response
Figure 5. VOUT versus VIN
tr= 8.3ns
Overshoot = 5%
STV9555 Vout vs Vin
120
100
Vout (V)
80
60
40
20
0
tf= 10.3ns
Overshoot = 0%
0
1
2
3
4
Vin (V)
Figure 6. Power dissipation versus frequency
Vdd=110V
Power dissipation (W)
11
Vdd=100V
2.00
10
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30
Frequency (MHz)
(72% active time)
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10
Tf
9.5
9
50
bs
100
14
13
Tf
10
Tf
11
10
Tr
9
Tr
8
8
40
45
50
55
Offset (Vdc)
60
65
70
7
8
10
12
14
Load capacitor (pF)
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90
12
11
9
70
80
Case Temperature (°C)
Figure 9. Speed versus load capacitance
Speed (ns)
12
60
40
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Tr
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Figure 8. Speed versus offset
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0.00
Speed (ns)
10.5
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Speed (ns)
Vdd=90V
1.00
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11.5
5.00
3.00
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Figure 7. Speed versus temperature
6.00
4.00
5
16
18
20
STV9555
9
INTERNAL SCHEMATICS
Figure 10. RGB inputs
Figure 11. RGB outputs
VDD
VCC
OUT
IN
pins 1, 2, 4
pins 9, 10, 11
GNDS
GNDS
Figure 12. VDD
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VDD
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GNDS
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VCC
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GNDS
Figure 15. GNDA
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GNDA
GNDP
GNDS
GNDS
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STV9555
10
APPLICATION HINTS
10.1 How to choose the high supply voltage value (VDD) in DC coupling mode
The VDD high supply voltage must be chosen carefully. It must be high enough to provide the necessary
video adjustment but set to minimum value to avoid unecessary power dissipation.
Example (see Figure 2):
The following example shows how the optimum VDD voltage value is determined:
– Cut-off adjustment range (B) : 25V
– Max contrast (D) : 40V
Case 1:
10V Brightness (C) adjusted by the preamplifier :
VDD = A + B + C + D + E
VDD = 15V + 25V + 10V + 40V + 17V = 107V
Case 2:
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10V Brightness (C) adjusted by the G1 anode:
VDD = A + B + D + E
VDD = 15V + 25V + 40V + 17V = 97V
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10.2 Arcing Protection: schematics
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As the amplifier outputs are connected to the CRT cathodes, special attention must be given to protect
them against possible arcing inside the CRT.
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Protection must be considered when starting the design of the video CRT board. It should always be
implemented before starting to adjust the dynamic video response of the system.
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The arcing network that we recommend (see Figure 16) provides efficient protection without deteriorating
the amplifier video performances.
The total resistance between the amplifier and the CRT cathode (R10+R11) protects the device against
overvoltages. We recommend to use R10+R11 > 200 Ω.
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Spark gaps are strongly recommended for arcing protection.
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STV9555
Figure 16. Arcing protection network (one channel)
VDD
R19(**)
C12(*)
100nF/250V
33-40Ω
VDD
C24
4.7µF/150V
C18
100nF
D12
FDH400
OUT
L1
R10
STV9555
0.33µH
110Ω/0.5W
GNDS
CRT
110Ω/0.5W
D13
FDH400
C29(***)
0.22µF
A
R11
F1
Spark gap
200V
B
GNDP
GNDA
R29(***)
1-10Ω
(*): To be connected as close as possible to the device
(**): R19 must be mandatorily used
(***): Ground separation network
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10.3 Arcing protection: layout and decoupling
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Several layout precautions have to be considered to get the optimum arcing protection:
Sparkgap grounding: when an arc occurs, the energy must flow through the CRT ground without
reaching the amplifier. This is obtained by connecting the sparkgap grounding (point B) to the CRT
ground (socket) via a wide/short trace. Conversely the point B must be connected to the amplifier
ground via a longer/narrower trace.
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Grounding separation: In order to set apart the amplifer ground and CRT ground, the R29/C29 network (Figure 16) can be used.
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Amplifier grounding: The 3 grounds GNDS, GNDA and GNDP must be connected together as
close as possible to the device.
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STV9555
10.4 Video response optimization: schematics in DC-coupling mode
The dynamic video response is optimized by carefully designing the supply decoupling of the video board
(see Section 10.7), the tracks (see Section 10.7), then by adjusting the input/output component network
(see Section 10.5).
For dynamic measurements such as rise/fall time and bandwidth, a 8pF load is used (total load including
the parasitic capacitance of the PC board and CRT Socket).
When used in kit with the STV921x preamplifier from ST, the preamplifier bandwidth register (BW, register
13) must be set to minimum (o dec) for an application with t R/tF>5.5ns.
Figure 17. Video response optimization for one channel - DC coupling application
C11
4.7µF
C10(*)
100nF
C24
4.7µF
C12(*)
100nF
R19(***)
VCC
Reference
Input Network #1
OUT
R10
IN
OUT
R1(**)
51Ω
VDD
33-40Ω
STV9555
C1
1.5nF
STV921x
VDD
-
R11
CRT
110Ω 0.33µH 110Ω
VREF
GNDS
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C2
10pF
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GNDP
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Caution: For Application with Tr/Tf>5.5ns, the PreAmplifier bandwidth register (BW, Register 13)
must be set to minimum value (0 dec)
(*): To be connected as close as possible to the device
(**): R1 must be not be higher than 100Ω
(***): R19 must be mandatorily used
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2 other Input Networks (Network #2 and #3 below) can be used in replacement of the reference Input Network #1.
See Application note AN1510 for complete description.
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Input Network #2
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Input Network #3
L1
0.33µH
R1
82Ω
14/24
IN
C2
10pF
IN
R1
33Ω
C2
15pF
STV9555
10.5 Video response optimization: outputs networks
The output network (R10/L1/R11) is used to adjust the amplifier video performances. Once R10 and R11
resistors are set to protect the application against arcing (R10 + R11>200Ω), it is possible to increase the
bandwidth by increasing L1.
10.6 Video response optimization: inputs networks
The input network also plays an important role in the device dynamic behaviour. We recommend to use
the reference input network #1, which is described in Figure 17, but 2 other networks (#2 and #3) can be
used to better match the required performances and the video board layout. Refer to the application note
referenced AN1510 for the complete description of these input networks.
10.7 Video response optimization: layout and decoupling
The decoupling of VCC and VDD through good quality HF capacitors (respectively C10 and C12) close to
the device is necessary to improve the dynamic performance of the video signal.
Careful attention has to be given to the three output channels of the amplifier.
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Capacitor: The parasitic capacitive load on the amplifier outputs must be as small as possible.
Figure 9 from Section 8 clearly shows the deterioration of the tR/tF when the capacitive load
increases. Reducing this capacitive load is achieved by moving away the output tracks from the other
tracks (especially ground) and by using thin tracks (<0.5mm), see Figure 17.
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Cross talk: Output and input tracks must be set apart. The STV9555 pin-out allows the easy separation of input and output tracks on opposite sides of the amplifier (see Figure 21).
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Length: Connection between amplifier output and cathode must be as short and direct as possible.
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STV9555
10.8 AC - Coupling mode
The STV9555 can be used in AC-Coupling mode in kit with the TDA9207/9212 preamplifier from ST. As
for the DC-coupling mode, the STV9555 drives perfectly the video signal in PICTURE BOOST conditions.
A typical schematic is given on the Figure 18 below.
Figure 18. Video response optimization for one channel - AC coupling application
C11
4.7µF
C10(*)
100nF
C24
4.7µF
C12(*)
100nF
R19(***)
VDD
VCC
Reference
Input Network #1 (****)
STV9555
C1
1.5nF
TDA9207
OUT
C
OUT
IN
R1(**)
51Ω
VDD
33-40Ω
R10
-
L1
C1
R11
1µF
110Ω
+
C2
10pF
110Ω 0.33µH
VREF
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GNDS
GNDP
GNDA
Vrestore
Cut-off
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Caution: For Application with Tr/Tf>5.5ns, the PreAmplifier bandwidth register (BW, Register 13)
must be set to minimum value (0 dec)
(*): To be connected as close as possible to the device
(**): R1 must be not be higher than 100Ω
(***): R19 must be mandatorily used
(****): Input Networks #2 and #3 can be used as well
)
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The advantage of such an architecture is to use smaller VDD and therefore to have smaller power
consumption. This is due to the fact that the STV9555 provides only the video signal and not the cut-off
adjustment. The disadvantage is to have an application with more components (DC restore circuitry).
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Note that it is mandatory to keep the output video signal (point C) inside the linear area of the amplifier
(from 17V to VDD - 15V).
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STV9555
10.9 Stand-by mode, spot suppression
The usual way to set a monitor in stand-by mode is to switch-off the Vcc (12V).
The STV9555 has an extremely low power consumption (I DDS = 60 µA when VCC<1.5V) in stand-by mode
and the outputs are set to low level (white picture).
To avoid the display of a spot effect during the switch-off phase, it is necessary to adjust the G1 circuitry
(Resistors Rx and Cx, see Figure 19) to pull the G1 voltage to low value during a sufficient time duration.
Figure 19. Stand-by mode, spot effect
+80V
Cathode
0V
Case #1: Low Rx.Cx
A spot might appear during
the switch-off phase
-30V
G1
Case #2: High Rx.Cx
No spot effect
-120V
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Typical G1 generator circuitry
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-120V
G1
R1
Cx
Rx
-30V
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STV9555
10.10 Conclusion
Video response is always a compromise between several parameters. For example, the rise/fall time
improvement leads to the overshoot deterioration.
The recommended way to optimize the video response is:
1 To set R10+R11 for arcing protection (min. 200 Ω)
2. To adjust R20 and R10+R11.
Increasing their value increases the
tR/tF values and decrease the overshoot
3. To adjust L1
Increasing L1 speeds up the device but increases the overshoot.
4. To adjust the input network for the final dynamic tunning (e.g.: critical damping)
We recommend our customers to use the schematic shown on Figure 23 as a starting point for the video
board and then to apply the optimization they need.
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STV9555
Figure 20. STV9555/9553/9556 + TDA9210/STV9211 + STV9936S/P DC-coupling demonstration
board: Silk Screen and Trace
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STV9555
Figure 21. Outputs trace (from figure 19)
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Figure 22. CRT socket trace (from figure 19)
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s
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3.3V
C28 100nF
U3
VS
SCL
SDA
FBLK
TEST GOUT
DVSS BOUT
DVDD
14
15
16
10
11
12
AVDD 13
VCO
RP
AVSS
D8
R10
75Ω
STV9936S/P
R45 15kΩ
AVdd
R34 330Ω
R33 330Ω
R32 330Ω
7
6
5
4
3
2
1
VS
HS
HFLY
HEATER
G1
3.3V
18
19
20
10
9
8
7
6
Power
J16
1
2
3
4
5
6
7
8
C23
5V
R19 2.7kΩ
R17 51Ω
C36 1.5nF
R13 51Ω
5V
10pF
C25
C16
47µF/25V
C27
47µF/25V
ZD1
3.3V
3V0
R37 51Ω
47µF/25V
47µF/25V
C27
5V
100pF
SDA
100pF
ABL
BLK
110V
SCL
C13
C12
C15
R47 100Ω
11
J10
I2C
1
2
3
4
10pF
C24
C33 1.5nF 10pF
51Ω
C31 1.5nF
R9
C8
12V
47µF/25V
8V
R11 2.7Ω
R40 100Ω
R21 2.7kΩ
12
13
14
12V
8V
FBLK
SCL
SDA
OUT3
C5 100nF
15
OUT2 16
GNDP
TDA9210
OSD3
OSD2
OSD1
VCCA
GNDA
5 IN3
VCCP 17
OUT1
HS/CLP
BLK
C26
100pF
C1
100pF
C7
4
2
1
100nF
In3
In2
In1
1
2
3
Out1
HS1
R28 0Ω
R6
R14
R22
110Ω/0.25W
9
C21
10nF/250V
optional
L1
4.7µF/160V
R7
FDH400
J7
GND
FDH400
D13
FDH400
D9
R15
R23
G1
RK
B
G
R
D11
Heater
F1
200V
BK
F4
200V
GK
F2
200V
4.7nF/1kV
C20
100nF
J8
G2
12 GND
1 GND
30Ω/0.5W
R31
C19
4.7nF/2kV
CRT small neck
C14
9 H2
F3
1.5Ω
Wednesday October 3, 2001
Version 1.4
Rev.
C
EVALCRT52/STV955x demoboard (AB25)
STMicroelectronics
Monitor Business Unit - Video application
CMG - Imaging and Display Division (IDD)
12, rue Jules Horowitz - B.P. 217
38019 Grenoble cedex - FRANCE
1N4004
150Ω/0.25W
R27
0.33µH 110Ω/0.25W
L3
0.33µH 110Ω/0.25W
D12
FDH400
FDH400
L2
D7
D10 110V 0.33µH 110Ω/0.25W
110Ω/0.25W 110V
10
110V
C18
R29 39Ω
FDH400
D2
110V
110Ω/0.25W
11
10nF/250V
C10
110V
Out3
Out2
STV9555
U2
RadAB20
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Sync
J17
100µF/25V
100nF
L4 1µH
C22 100nF
C6 100nF
C37
R36 330Ω
IN2
ABL
IN1
U1
C9 100nF 4
GNDL
C4 100nF 3
2
C3 100nF 1
R4
2.7Ω
C2
R43
1MΩ
Vco R44 5.6kΩ C34 10nF
Rp
R16 2.7Ω
R12 15Ω
1N4148
D5 R8 15Ω
1N4148
D4
5V
R46 5.6kΩ C35 10nF
1N4148
1N4148
D6
5V
1N4148
Red
R5
75Ω
Green
8 OVDD ROUT 9
7
6
5
4 HFLY
3
2
1
1
2
3
4
5
6
D3
R3
75Ω
R2 15Ω
ABL
R25 100Ω
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100µF/25V
C32
L5 1µH
HFLY R41 100Ω
VS
R39 100Ω
SCL
R35 100Ω
R38 100Ω
SDA
video
J1
1N4148
Blue
D1
5V
BLK
3
Vcc
GNDA
5
7
Vdd
GNDP
R1 100Ω
GNDS
6
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HS
STV9555
Figure 23. STV9555/53/56 + STV9936 + TDA9210/STV9211 DC-coupling demo-board schematic
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STV9555
11
PACKAGE MECHANICAL DATA
11 PIN - CLIPWATT
V1
H3
H2
S
A
C
Shaded area ewposed from plastic body
Typical 30 µm
H1
V1
V2
L3
V1
V1
R2
L2
R
L1
R1
V
R3
D
R3
R3
LEAD#1
E
M1
G1
Millimeters
Min.
A
2.95
B
0.95
C
-
D
1.3
E
0.49
F
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F1
G
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H1
0.78
-
Typ.
3
)
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0.15
F
F1
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Max.
Min.
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Inches
Typ.
Max.
3.05
0.116
0.118
0.12
1.05
0.037
0.039
0.041
-
-
0.006
-
1.5
1.7
0.051
0.059
0.061
0.515
0.55
0.0.019
0.02
0.021
0.8
0.86
0.03
0.031
0.034
0.05
0.1
-
0.002
0.004 (6)
du
1.6
1.7
1.8
0.063
0.067
0.071
16.9
17
17.1
0.665
0.669
0.673
-
12
-
-
0.472
-
H2
18.55
18.6
18.65
0.73
0.732
0.734
H3
19.9
20
20.1
0.783
0.787
0.791 (5)
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G
M
Dimensions
G1
c
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B
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L
17.7
17.9
18.1
0.696
0.704
0.712
L1
14.35
14.55
14.65
0.564
0.572
0.576
L2
10.9
11
11.1
0.429
0.433
0.437(5)
L3
5.4
5.5
5.6
0.212
0.216
0.22
M
2.34
2.54
2.74
0.092
0.1
0.107
M1
2.34
2.54
2.74
0.092
0.1
0.107
R
1.45
-
-
0.057
-
-
STV9555
Millimeters
Dimensions
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
R1
3.2
3.3
3.4
0.126
0.13
0.134
R2
-
0.3
-
-
0.012
-
R3
-
0.5
-
-
0.019
-
S
0.65
0.7
0.75
0.025
0.027
0.029
V
10deg.
10deg.
V1
5deg.
5deg.
V2
75deg.
75deg.
Note 5: “H3 and L2” do not include mold flash or protrusions
Mold flash or protrusions shall not exceed 0.15mm per side.
Note 6: No intrusions allowed inwards the leads
Critical dimensions:
Lead split (M1)
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Total length (L)
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STV9555
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of
STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as
critical components in life support devices or systems without express written approval of STMicroelectronics.
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The ST logo is a trademark of STMicroelectronics.
© 2003 STMicroelectronics - All Rights Reserved
Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent.
Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard
Specifications as defined by Philips.
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