Analog Design Using
gm/Id and ft Metrics
Bernhard E. Boser
boser@eecs.berkeley.edu
Copyright © 2011 Bernhard Boser
B. E. Boser
Analog design using gm/Id and ft metrics
1
Overview
• Traditional analog design methodologies typically require iteration
– “Square Law” design equations are inaccurate for submicron devices
– Depend on poorly defined parameters: mCox, Vth, Vdsat, …
– Difficult to achieve an “optimum” (e.g. minimum power)
• gm/Id-based design
– Links design variables (gm, ft, Id, …) to specification (bandwidth, power)
– Employs design charts to accurately size transistors
B. E. Boser
Analog design using gm/Id and ft metrics
2
Motivation: A design example
Specifications:
• Small signal gain:
• Bandwidth:
av = vo/vi = 5
B ≥ 10MHz
• Source resistance:
Rs = 1MW
• Load capacitance:
CL = 5pF
• Minimum power dissipation
B. E. Boser
Analog design using gm/Id and ft metrics
3
Design Approaches
Design equations (Square-Law model)
VGS  VTH 
g m  mCox WL VGS  VTH 
Id  21 mCox
W
L
2
CGS  CoxWL
etc.
...
Difficulties
• Sub-micron transistors are not well
described by these equations
• Non-obvious relation of model
parameters to design specification
• Leads to many iterations
• What is the minimum power, anyway?
B. E. Boser
Analog design using gm/Id and ft metrics
4
Natural Variables for Analog Design
Id
• Transconductance
VGS
• Current
VDS
• Efficiency
• Capacitance
• Transit frequency
vgs
B. E. Boser
Cgs
id
gm
Id
gm/Id
Cgs, …
ft = gm/2pCgs
vds
Analog design using gm/Id and ft metrics
5
Example
Design constraints
av  gmR
L
• Low frequency gain
1
1
1
1
p 

in R C
2p B
s gs
• Pole at input
• Pole at output
p


out R C
2p B
L L
Specifications:
• Small signal gain:
• Bandwidth:
av = vo/vi = 5
B ≥ 10MHz
• Source resistance:
Rs = 1MW
• Load capacitance:
CL = 5pF
CGS 
1
2p BRs
minimize Id
• Minimum power dissipation
B. E. Boser
gm  2p BCL
Analog design using gm/Id and ft metrics
6
Design Constraints and Objectives
Design constraints
Design objectives
1. High current efficiency
gm  2p BCL  1.57 mS
CGS 
1
 16 fF
2p BRs
minimize Id
to minimize power
2. Small Cgs  high fT
to meet bandwidth
constraint
B. E. Boser
Analog design using gm/Id and ft metrics
gm
Id
gm
ft 
2p Cgs
7
Transit Frequency fT
fT versus gm/Id tradeoff
Compromise
• high gm/Id for low power
• high ft for low Cgs
15.7 GHz
Design choice
14 V-1
NMOS (simulation)
B. E. Boser
Analog design using gm/Id and ft metrics
• Maximum Cgs to meet
specification at
minimum power:
• minimum ft
• minimum L
• maximum gm/Id
ft ,min 
g m,min
2p Cgs,max
 15.7 GHz
8
Transistor Current Efficiency gm / Id
g m Id
5
10
[ V 1 ]
15
20
Low
gm/Id
High
gm/Id
400m
200m
2
•
Strong Inversion
•
•
Poor current efficiency
Low output voltage range
•
•
g m Id
133m
100m
[V]
High ft
Small transistor
B. E. Boser
Analog design using gm/Id and ft metrics
•
Weak Inversion
•
•
Good current efficiency
(low Vdsat )
High output voltage range
•
•
Low ft
Large transistors
9
Completing the Design: Transistor Sizing
gm
 14 V 1 and fT  16 GHz
Id
gm
Id 
 112 m A
g m Id
12.4 A/m
Id
A
 12.4
(from chart)
W
m
I
W  d  9 mm
Id W
B. E. Boser
14 V-1
Analog design using gm/Id and ft metrics
10
Verification: (1) Bias
B. E. Boser
Analog design using gm/Id and ft metrics
11
Verification: (2) Specification
• Bias is as designed
• Gain and bandwidth
slightly below spec
• Design ignored
transistor ro and selfloading
• Adjust by choosing a
slightly higher ft
B. E. Boser
Analog design using gm/Id and ft metrics
12
Summary
Silicon
SPICE Model
“Square Law”
based design
gm/Id
based design
Complicated
Complicated
Simple
gm/Id & ft
Physics
Equations
“Square Law”
Charts
(BSIM, PSP, …)
Equations
(process specific)
• Accurate
• Good for verification
• Unsuitable for
design
B. E. Boser
•
•
•
•
Popular (textbooks)
Poor accuracy
Requires iterations
Difficult to achieve
optima
Analog design using gm/Id and ft metrics
• Good accuracy
• Simple equations
• Transistor data
from charts
13
NMOS Transit Frequency fT
B. E. Boser
Analog design using gm/Id and ft metrics
14
PMOS Transit Frequency fT
B. E. Boser
Analog design using gm/Id and ft metrics
15
Extrinsic Capacitances Cgd and Cdd
NMOS
B. E. Boser
PMOS
Analog design using gm/Id and ft metrics
16
NMOS Current Density
B. E. Boser
Analog design using gm/Id and ft metrics
17
PMOS Current Density
B. E. Boser
Analog design using gm/Id and ft metrics
18
NMOS Intrinsic Gain gm ro
B. E. Boser
Analog design using gm/Id and ft metrics
19
PMOS Intrinsic Gain gm ro
B. E. Boser
Analog design using gm/Id and ft metrics
20
Intrinsic Gain gm ro
NMOS
B. E. Boser
PMOS
Analog design using gm/Id and ft metrics
21
OTA Design Example
Cf
CL
Cs
+
vid
-
+
vod
Cs
CL
Specifications
• Voltage gain
• Dynamic range
• Settling accuracy
Cf
• Settling time
•
Switched capacitor gain stage
(switches not shown)
•
Applications: A/D converters, filters, …
B. E. Boser
Analog design using gm/Id and ft metrics
Av = 2
DR ≥ 72dB
ed ≤ 100ppm
ts ≤ 10ns
22
Circuit Topology
VDD
MP1a
MP1b
MPB
vod
Vom
- Vod +
Vip
Vop
vid
Vim
MN1a
MN1b
Cf
IT/2
IT
vi
Cs
vx
vo
Ro
Cx
•
•
•
Fully differential OTA
Common mode and
cascodes (for gain) not shown
B. E. Boser
Analog design using gm/Id and ft metrics
•
•
Co
CL
Gmvx
Differential mode half circuit
Large & small signal models
23
Design Flow
1. Determine feedback factor
2. Determine CL to meet dynamic range requirement
3. Determine gm to meet settling requirement
4. Pick transistor characteristics based on analysis
– Channel length L
– Current efficiency gm/ID (or ft)
5. Determine bias currents and transistor sizes
–
–
ID (from gm and gm/ID)
W (from ID/W, current density chart)
B. E. Boser
Analog design using gm/Id and ft metrics
24
(1) Feedback Factor
Cf
vi
Cs
vx
vo
Ro
Cx
•
•
Open feedback loop
b
Co
CL
Gmvx
vx
Cf


v o Cf  Cs  Cx
1
1  Av 
Cx is amplifier input capacitance (Cgs + …)
Cx
Cf
– Small Cx  large feedback factor b
– Large Cx  low transistor ft requirement  higher gm/Id  reduced current
– Typically Cx = (⅓ … 1) x (Cs + Cf) (shallow optimum)
B. E. Boser
Analog design using gm/Id and ft metrics
25
(2) Dynamic Range
Output resistance: R 
4kTgpgmp
MP
R
vo
Noise density:
1
bg mn
v o2,n
 g mp Id 
R
 4kT g g mn  1 


f
 g mn Id  1  j RCLtot
MN
bvo
4kTgngmn
CLtot
Sampled noise:
v o2,n
Id

g mn
Id
for low noise
1 kT  g mp 

g 1

b CLtot  g mn 
with
CLtot  CL  1  b  Cf
1V 2
2 o,max
v o2,n
Dynamic range:
DR 
Minimum load capacitance:
CLtot  2kT
B. E. Boser
g mp
choose
PMOS
g  g mp
1
b  g mn
Analog design using gm/Id and ft metrics
 DR
 2
 Vo,max
26
2
(3) Settling
Dynamic Error ed(t)
Cf
Static Error e0
1
0
Gm
Vstep
e d  e  ts / 
0.8
Cs
Cin
Vout
Vout/Vout,ideal
Vin(t)
CL
0.6
for single pole
response
0.4
0.2
0
0
2
4
6
t/
8
10
Settling time ts
Step response: v out (t )  Vstep

Cs T0

 1  e  t /
Cf 1  T0
ideal
response
static
error
Solve for transconductance:
B. E. Boser

with  
CLtot
b g mn
dynamic
error
g mn
CLtot ln ed

b ts
Analog design using gm/Id and ft metrics
27
(4) Transistor Channel Length, gm/Id and ft
NMOS
PMOS
180 nm
250 nm
Ln,min reduces power
12 V-1
8 V-1
gmp/Id < gmn/Id (noise)
ft
19.7 GHz
3.78 GHz
Id/W
18.7 A/m
7.06 A/m
L
gm/Id
Cgsn < Cs + Cf
• Reduce gm/Id of NMOS if Cgsn < Cs + Cf
• ft and Id/W obtained from charts
B. E. Boser
Analog design using gm/Id and ft metrics
28
(5) Bias Currents and Transistor Sizes
ota1.mcd
B. E. Boser
Analog design using gm/Id and ft metrics
29
Verification: (1) Test Bed
OTA
B. E. Boser
OTA in Feedback Loop
Analog design using gm/Id and ft metrics
30
Verification: (2) Bias
So far, so good …
B. E. Boser
Analog design using gm/Id and ft metrics
31
Verification: (3) Dynamic Range
perfect!
B. E. Boser
Analog design using gm/Id and ft metrics
32
Verification: (4) Settling Time
• Dynamic settling error target met
• Large static error ~10%
B. E. Boser
Analog design using gm/Id and ft metrics
33
Openloop Gain
• Openloop gain only Avo ~ 50
• To = b Avo = 11
• Add cascodes to increase
low frequency gain
B. E. Boser
Analog design using gm/Id and ft metrics
34
Generic gm/Id-based Design Flow
1. Determine gm from design objectives (dynamic range, bandwidth, …)
2. Pick L
– Short channel  high ft (high speed)
– Long channel  high intrinsic gain, good matching, …
3. Pick gm/ID or ft
– Large gm/ID  low power, large signal swing
– Small gm/ID  high ft (high speed)
4. Determine ID (from gm and gm/ID)
5. Determine W (from ID/W, current density chart)
• Adapt to design specifics
B. E. Boser
Analog design using gm/Id and ft metrics
35
Acknowledgements
• Prof. Boris Murmann
• Prof. Paul Gray
• Prof. Ali Niknejad
• Prof. Elad Alon
• Many generations of students
B. E. Boser
Analog design using gm/Id and ft metrics
36