VI. Transistor Amplifiers
6.1
Introduction
In this section we will use the transistor small-signal model to analyze and design transistor
amplifiers. There are two issues that we need to discuss first: 1) What are the important
properties of an amplifier? and 2) How can we add a signal to the bias in a real circuit?
6.1.1
Amplifier Parameters
ii
R sig
In Section 1, we showed that the response of a two-port
network is completely determined if we solve the simple
circuit shown. This solution is uniquely summarized by
three parameters:
v sig
io
+
+
−
vi
+
vo
Amplifier
−
RL
−
1) The ratio of vo /vi which is called the voltage transfer function of the circuit. For voltage
amplifiers, vo /vi = const and is called the amplifier voltage gain (or gain for short):
Voltage Gain:
Av =
vo
vi
In general Av depends on the load, RL . A special case is the “open-loop” gain in which
RL → ∞ (called open-loop gain as io = 0):
Open-loop Gain:
Avo
voc
vo =
= vi
vi RL →∞
2) As the combination of the two-port network (amplifier)
and the load is a two-terminal network, it can be modeled by its Thevenin equivalent. Furthermore, as this
combination does not contain an independent source, it
reduces to a resistor, called the input resistance:
Input Resistance:
Ri =
R sig
v sig
+
−
ii
io
+
+
vi
vo
Amplifier
RL
−
−
vi
ii
In general Ri depends on the load, RL .
3) The combination of the amplifier and the input (vsig
and Rsig ) is also a two-terminal network and can be
modeled by its Thevenin equivalent. We denote the
Thevenin resistance of this combination as Ro .
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
R sig
v sig
+
−
ii
io
+
+
vi
vo
−
Amplifier
RL
−
6-1
In order to calculate Ro we need to set the independent voltage source vsig = 0 and compute
the equivalent resistance seen between the output terminals, i.e.,
vo Ro = − io vsig =0
Output Resistance:
(Thevenin Resistance)
In general Ro depends on Rsig .
The Thevenin voltage source of the amplifier/input combination, VT , is the open-circuit
voltage, voc , and is related to the open-loop gain of the amplifier:
VT = voc = vo |RL →∞ = Avo vi
Therefore, the load “sees” a Thevenin equivalent circuit with VT = Avo vi and RT = Ro .
Combining models of the input and output ports, we arrive at a model for an amplifier which
consists of three circuit elements as is shown below (left).
ii
Ro
+
vi
io
R sig
+
−
A vo v i
vo
v sig
+
−
−
−
Ro
+
+
Ri
ii
vi
io
+
Ri
+
−
−
A vo v i
vo
RL
−
The amplifier circuit model allows us to solve any amplifier configuration if we know values
of Avo , Ri and Ro (similar to using Thevenin Theorem to “label” any two-terminal network
with RT and VT ). For example, we can find the overall voltage gain of the amplifier, vo /vsig ,
as (see figure above right):
vo
RL
=
Avo
vi
Ro + RL
Ri
vi
=
vsig
Ri + Rsig
vi
vo
Ri
Ri
RL
vo
=
×
=
× Av =
× Avo ×
vsig
vsig
vi
Ri + Rsig
Ri + Rsig
Ro + RL
We see that the open-loop gain Avo is the maximum value for the amplifier gain Av . In
addition, to maximize vo /vsig , we need Ri → ∞ and Ro → 0. A good voltage amplifier,
thus, is designed to have a “large” Ri and a “small” Ro (i.e., Ri ≫ Rsig and Ro ≪ RL ). A
voltage-controlled voltage source is an ideal voltage amplifier as Ri → ∞ and Ro = 0.
We will use this amplifier model later to find parameters of multi-stage amplifiers (Sec. 6.4)
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-2
6.1.2
Capacitor Coupling
As discussed before, a constant bias voltage should be added to the signal to ensure that the
MOS is always in saturation or the BJT is in active. There are two ways to accomplish this
task.
1) “Direct Coupling:” For a multi-stage amplifier, the biasing scheme can be set up such
that the bias voltage of each stage matches the bias voltage of the following stage. Usually,
bias with two voltage supplies is used such that for the first amplifier stage, VG = 0 for MOS
(or VB = 0 for BJT). Integrated circuit chips use direct coupling scheme in order to avoid
using capacitors which take a lot of space on the chip. Because of the need to match bias
voltages between stages, biasing becomes a difficult design problem.
2) “Capacitive coupling:” Since a capacitor becomes an open circuit for bias (DC voltages
& currents), it can be used to couple the signal to the circuit as is shown below for a MOS
amplifier.
C
v gs
+
−
V DD
V DD
RD
RD
iD
ID
C
c1
+
RG
V GS
−
C
+
+
v gs
v DS
+
c2
v ds
+
−
c1
Real Circuit
_
id
c2
C
+
+
RG
V GS
_
C
+
v GS
_
RD
v gs
+
V GS
−
_
Bias Circuit
V DS
0
_
_
+
−
c1
RG
C
c2
+
+
v ds
v ds
_
_
+
v gs
_
Signal Circuit
The circuit to the left above shows a practical implementation of this scheme. For bias
(middle circuit above), capacitors will be open circuit and, thus, the bias voltages and
currents remain confined to the transistor and do not propagate to the signal or the load
sides. In the signal circuit (right circuit above), if the signal is an AC signal, capacitors
would act as impedances and allow the signal to enter and exist the transistor amplifier.
Impedance of a capacitor, |ZC | = 1/(ωC), depends on the frequency. As a result vo /vi will
also depend on frequency and, in general, the amplifier would not behave linearly for an
arbitrary signal (which includes many frequencies). However, at high enough frequencies,
the impedance of a capacitor becomes very small and the capacitor effectively becomes a sort
circuit. For frequencies higher than this value, vo /vi will be independent of frequency and
the linear behavior of the amplifier is recovered. The frequency at which we can ignore the
impedances of the coupling capacitors is called the lower cut-off frequency of the amplifier.
In order to ensure a linear behavior for an amplifier, it is always operated above its cut-off
frequency where the coupling capacitors can be ignored (i.e., can be approximated as short
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-3
circuit). As such, amplifier properties (gain, Ri & Ro ) are calculated assuming coupling
capacitors are short. Calculation of the lower cut-off frequency is discussed in Section 6.3.
You will see in ECE 102 that the gain of a transistor amplifier also drops at high frequencies
and there is an upper cut-off frequency. As such, the range of frequencies that an amplifier
will behave linearly is called the “mid-band.”
As the capacitive coupling scheme confines bias voltages in each stage, biasing is simpler
with this method. On other hand, DC signals cannot be amplified.
6.1.3
Analysis of Transistor Amplifier Circuits
Analysis of a transistor amplifier circuit follows three steps as we need to address several
issues: bias, linear response (to small signals), and the impact of coupling capacitors.
Bias:
1) Zero out the signal and replace capacitors with open circuits. Compute transistor bias
point parameters.
2) Compute gm and ro (and rπ for BJT) from bias point parameters.
Mid-band Small Signal Response:
1) Draw the signal circuit (e.g., ground bias voltage sources, open bias current sources).
2) Assume capacitors are short circuit.
3) Inspect the circuit and simplify. If you identify the circuit as a prototype circuit, you can
directly use the formulas for that circuit. Otherwise, replace the transistor with its small
signal model and solve for Av , Ri and Ro .
Frequency-response: Coupling and bypass capacitors introduce poles at low frequencies. In
Section 6.3, we will introduce a method to estimate the lower cut-off frequency of an amplifier.
ECE102 includes a more thorough review of the amplifier frequency response.
There are many practical implementation for single-transistor amplifiers due to a variety of
biasing possibilities. However, the signal circuit for a signal-transistor amplifier generally
reduces to one of four “fundamental amplifier configurations” (4 for BJT and 4 for MOS).
As discussed in the class (see lecture slides), solution of these fundamental configurations can
be used to find the gain of any transistor amplifier. You will see in ECE102 that the input
and output resistances can be found using “elementary R forms.” These formulas allows one
to compute properties of any amplifier readily and are used extensively in ECE102.
Since we are only focusing on discrete and simple amplifier configurations in this course,
amplifier parameters are computed directly from the circuit in the following sections in
order to provide more examples of solving signal circuits with transistor small-signal models.
Notes:
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-4
1) Small-signal models of PNP and NPN transistors (or PMOS and NMOS transistors) are
similar. Thus, the formulas derived below can be used for either case.
2) The small-signal model of a BJT is similar to that of a MOS with the exception of the
additional resistor rπ (the input terminals in a MOS is open circuit). As such, we expect
that formulas for MOS amplifiers would be the same as those of BJT amplifiers if we set
rπ → ∞.
3) For MOS circuits, we can use the common approximation gm ro ≫ 1 as
gm =
2ID
,
VOV
ro ≈
VA
ID
→
g m ro =
2VA
≫1
VOV
typically gm ro is 50 or more.
4) For BJT circuits, we can also use the common approximation gm ro ≫ 1 as
gm =
IC
,
VT
ro =
VA + VCE
VA
≈
IC
IC
→
g m ro =
VA
≫1
VT
typically gm ro is several thousands. In addition, gm rπ = β ≫ 1
5) In many text books (e.g., Sedra & Smith), the formulas for BJT amplifiers are given in
terms of β & re (instead of gm & rπ ) where
re =
1
rπ
=
gm
β
with re typically in 10s or 100 Ω range. Here we keep the gm form so we that can see the
comparison to MOS amplifiers.
6) Some manufacturer spec sheet for BJTs (e.g., spec sheet for 3N3904) use the older notation
(hybrid π model) for BJT which are hf e ≡ β, hre ≡ rπ , and hoe ≡ 1/ro
6.2
Discrete Single-transistor Amplifiers
In this section, we will compute the amplifier properties of four discrete single-transistor
amplifiers. Solution is done for the “most general” version of the signal circuit. As we will
see in the problem section, formulas developed here can then be used to find the amplifier
parameters for a variety of circuits.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-5
6.2.1
Common-Drain and Common-Collector Amplifiers
Common-Drain or Source Follower Configuration
Circuits shown below are the generic signal circuits of a common-drain amplifier (i.e., we
have “zeroed” out all bias sources). The circuit to the left is the NMOS version and the
circuit to the right is the PMOS version. Because NMOS and PMOS small-signal models
are identical, both circuits will give the same signal response. As such, from now on we will
only show the signal circuits for NMOS transistors.
R sig
vsig
vi
C c1
R sig
vsig
C c2
+
−
vo
Ri
RG
RS
Ro
vi
C c1
C c2
+
−
vo
Ri
RL
RG
RS
RL
Ro
In this circuit, the input signal is applied at the gate and the output is taken at the source.
As the drain is grounded (for signal), it is the common terminal of input and output. Thus,
this circuit is called the common-drain amplifier.
It is important to realize that as a transistor can be biased in many ways, several “complete”
circuits (i.e., including bias elements) will reduce to the above “signal” circuit form of a
common-drain amplifier. Some examples are given below (vsig and Rsig in the input are not
shown for simplicity).
VDD
RG1
vi
VSS
VDD
vi
RS
C c1
C c2
RG2
RS
C c2
vo
vi
RL
RL
− VDD
RG = RG1 k RG2
C c2
vo
RG → ∞,
Cc1 → ∞,
I
vo
RL
− VSS
RG → ∞, RS → ∞,
Cc1 → ∞,
Exercise: Draw the signal circuit of the above three circuits and show that they reduce to
the generic discrete common-drain amplifier circuit above.
We now proceed with the signal analysis by replacing the MOS with its small-signal model.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-6
Using node-voltage method (there is one
node, vo ):
Node vo
vi i i
R sig
vsig
+
−
G
D
+
Ri
vgs = vi − vo
vo
vo
vo
+
+
− gm vgs = 0
RS
ro R L
vo
− gm (vi − vo ) = 0
ro k R S k R L
ii
gmvgs
ro
vgs
_
vo
S
RG
RL
RS
Ro
vo
gm (ro k RS k RL )
=
vi
1 + gm (ro k RS k RL )
As can be seen, the gain of this amplifier is less than but close to 1. Because vs = vo ≈ vi ,
i.e., signal voltage at the MOS source terminal follows the input signal vi , this configuration
is also called the Source Follower.
Finding Ri is easy as current ii flows in RG and vi = RG ii (see circuit). Therefore, Ri =
vi /ii = RG . Note that if RG were not present (see middle and left circuits on the example
complete circuits of the previous page). Ri → ∞.
To find Ro we need to zero out vsig and compute the Thevenin Equivalent resistance seen at
the output terminals. Because of the presence of the controlled source, we need to attach a
vx voltage source to the circuit and compute ix to get Ro = vx /ix .
We see from the circuit that vg = 0 and vgs = −vx . Thus:
vx
vx
vx
vx
vx
ix =
+
− gm vgs =
+
+
ro R S
ro RS 1/gm
1
1
vx
=
k R S k ro ≈
k RS
Ro =
ix
gm
gm
R
sig
vi
G
vsig
+
D
gmvgs
ro
vgs
_
ix
S
RG
+
−
RS
vx
Ro
In summary, the general properties of the common-drain amplifier (source follower) include
a voltage gain ≤ 1, a large input resistance (which can be made infinite in some biasing
schemes) and a small output resistance. This type of circuit is called a “buffer” and is
often used when there is a mismatch between input resistance of one stage and the output
resistance of the previous stage (see Sec. 6.4). Additionally, iL = io ≫ ii as vo /vi ≈ 1 while
Ri ≫ Ro . As such, this circuit can be used to amplify the signal current (and power) and
drive a load (used typically as the last stage of an amplifier circuit).
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-7
Common-Collector or Emitter Follower Configuration
Circuits shown are the generic signal circuits of a common-collector amplifier (i.e., we have
“zeroed” out all bias sources). The circuit to the left is the NPN version and the circuit to
the right is the PNP version. Because NPN and PNP BJT small-signal models are identical,
both circuits will give the same signal response. As such, from now on we will only show the
signal circuits for NPN BJT transistors.
R sig
vsig
C c1
vi
R sig
vsig
C c2
+
−
vo
Ri
RB
RE
Ro
vi
C c1
C c2
+
−
vo
Ri
RB
RL
RE
RL
Ro
In this circuit, the input is applied at the base and the output is taken at the emitter. As
the collector is grounded (for signal), it is the common terminal of input and output. Thus,
this circuit is called the common-collector amplifier.
As can be seen this configuration is analogous to the MOS common-drain amplifier. Similarly
to the MOS case, the BJT can be biased in many ways. Several “complete” circuits (i.e.,
including the bias elements) will reduce to the above “signal” form of a common-collector
amplifier. Some examples are given below.
VCC
RB1
vi
VEE
VCC
vi
RE
C c1
C c2
RB2
RE
C c2
vo
vi
RL
RL
− VCC
RB = RB1 k RB2
C c2
vo
RB → ∞,
Cc1 → ∞,
I
vo
RL
− VEE
RB → ∞, RE → ∞,
Cc1 → ∞,
We now proceed with the signal analysis by replacing the BJT with its small-signal model.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-8
Using node-voltage method (there is one
node, vo ):
vi i i
R sig
vsig
+
−
B
C
+
Ri
Node vo
iπ
vπ = vi − vo
vo
vo
vo − vi
vo
+
+
+
− g m vπ = 0
RE
ro R L
rπ
i1
vπ
gm vπ
ro
rπ
_
vo
E
RB
RL
RE
Ro
The last two terms in the above equation can be simplified by noting 1/rπ = gm /β:
β+1
gm
vo − vi
+ gm (vo − vi ) = gm (vo − vi )
≈ gm (vo − vi )
− gm vπ = (vo − vi ) ×
rπ
β
β
Substituting back in the node equation, we get:
vo
vo
vo
+
+
+ gm (vo − vi ) = 0
RE
ro R L
vo
+ gm (vo − vi ) = 0
ro k R E k R L
gm (ro k RE k RL )
vo
=
vi
1 + gm (ro k RE k RL )
The gain of the common collector amplifier is less than 1, but usually very close to 1 because
of the large BJT gm . This configuration is also called the Emitter Follower.
To find Ri = vi /ii , we note that by KCL ii = i1 + iπ and
vi
vo
vi − vo
=
× 1−
rπ
rπ
vi
vo
1
gm (ro k RE k RL )
1−
=
=1−
vi
1 + gm (ro k RE k RL )
1 + gm (ro k RE k RL )
vi
iπ =
rπ + gm rπ (ro k RE k RL )
vi
vi
vi
=
+
ii = i1 + iπ =
RB rπ + β(ro k RE k RL )
RB k [rπ + β(ro k RE k RL )]
iπ =
Ri = RB k [rπ + β(ro k RE k RL )]
Note that when emitter degeneration biasing is used, we need to have RB ≪ (1 + β)RE . In
this case, Ri ≈ RB (similar to the common-drain amplifier in which Ri = RG ). If RB is not
present, the input resistance would be very large (MΩ level).
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-9
To find Ro we need to zero out vsig and compute the Thevenin Equivalent resistance seen at
the output terminals.
We attach a voltage source vx to the circuit and compute ix to get Ro = vx /ix .
R sig
vi
B
vsig
C
+
vπ
gm vπ
ro
rπ
_
vx
vx
vx
ix =
+
− g m vπ +
ro R E
rπ + RB k Rsig
ix
E
RB
+
−
RE
vx
Ro
vπ can be found by the voltage divider formula (below). Substituting the expression for vπ
in the above expression for ix , the last two terms of the ix can be simplified as:
rπ
rπ + RB k Rsig
vx
vx
g m rπ v x
vx
ix =
+
+
+
ro RE rπ + RB k Rsig rπ + RB k Rsig
vπ = −vx ×
vx
vx
(β + 1)vx
+
+
ro RE rπ + RB k Rsig
vx
ix =
ro k RE k (rπ + RB k Rsig )/(1 + β)
ix =
R o = R E k ro k
rπ + RB k Rsig
(1 + β)
In summary, the general properties of the common-collector amplifier (emitter follower)
include a voltage gain close to unity, a large input resistance and a small output resistance
(similar to the common-drain amplifier). Thus, emitter follower is also used as a buffer or
for amplifying the signal current (and power) and drive a load.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-10
6.2.2
Common-Source and Common-Emitter Amplifiers
Common-Source Configuration
Circuit shown is the generic signal circuit of
a common-source amplifier (i.e., we have “zeroed” out all bias sources).
In this circuit input signal is applied at the gate and the
output is taken at the drain. As the source is
grounded (for the signal), it is the common terminal of input and output. Thus, this circuit is
called the common-source amplifier.
If source degeneration biasing is used for the
common-source configuration, a resistor RS
should be present. A “by-pass” capacitor is typically used so that the signal by-passes RS , effectively making the source grounded for the signal
as is shown. For bias, this capacitor is open and
RS provides source degeneration.
RD
C c2
R sig
vsig
vo
C c1
vi
+
−
RL
Ro
Ri
RG
RD
C c2
R
vsig
vo
C c1
vi
sig
+
−
RL
Ro
Ri
RG
RS
CS
We replace the MOS with its small-signal model.
vi i i
R sig
vsig
+
−
G
+
ii
Ri
RG
vo
D
gmvgs
ro
vgs
RD
_
RL
Ro
S
Inspecting the circuit, we find Ri = vi /ii = RG .
To find the gain, we note that vi = vgs . Furthermore, ro , RD , and RL are in parallel and by
KCL a current of gm vgs flows in ro k RD k RL (from the ground to vo ) as is shown. Then:
vi
Ohm Law:
vo = −gm vgs (ro k RD k RL )
vo
= −gm (ro k RD k RL )
vi
D
G
+
RG
vo
gmvgs
r o || RD || RL
vgs
_
S
gmvgs
The negative sign in the gain formula is indicative of a 180◦ phase shift in the output signal.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-11
To find Ro we need to zero out vsig and compute the Thevenin Equivalent resistance seen at
the output terminals (circuit below left). Examination of the circuit shows that vgs = vi = 0.
Thus, the controlled source gm vgs becomes an open circuit (circuit below right) and the
output resistance can be found by inspection to be Ro = RD k ro .
R
sig
vi
G
vsig
+
RG
G
D
gmvgs
ro
vgs
D
+
_
RD
gmvgs
ro
vgs = 0
Ro
RD
_
Ro
S
S
In summary, the general properties of the common-source amplifier include a large voltage
gain, a large input resistance (and can be made infinite with some biasing schemes) but a
medium output resistance.
Common-Emitter Configuration
Circuit shown is the generic signal circuit of
a common-emitter amplifier (i.e., we have “zeroed” out all bias sources).
In this circuit
the input signal is applied at the base and the
output is taken at the collector. As the emitter is
grounded (for the signal), it is the common terminal of input and output. Thus, this circuit is
called the common-emitter amplifier.
If emitter degeneration biasing is used for this configuration, a resistor RE should be present. Similar to the MOS common-source amplifier, a “bypass” capacitor is typically used so that the signal by-passes RE , effectively making the emitter
grounded for the signal as is shown.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
RC
C c2
R sig
vsig
vi
vo
C c1
+
−
Ro
RL
Ri
RB
RC
C c2
R
vsig
vi
sig
vo
C c1
+
−
Ro
RL
Ri
RB
RE
CE
6-12
We replace the BJT with its small-signal model.
vi i i
R sig
vsig
+
−
i1
Ri
RB
iπ
B
+
vπ
_
vo
C
gm vπ
RC
ro
rπ
RL
Ro
E
Inspecting the circuit, we find Ri = vi /ii = RB k rπ .
To find the gain, we note that vi = vπ . Furthermore, ro , RC , and RL are in parallel and by
KCL a current of gm vπ flows in ro k RC k RL (from the ground to vo ) as is shown. Then:
vi
Ohm Law:
vo = −gm vπ (ro k RC k RL )
vo
= −gm (ro k RC k RL )
vi
+
RB
vπ
_
vo
C
B
gm vπ
r o || RC || RL
rπ
gm vπ
E
The negative sign in the gain is indicative of a 180◦ phase shift in the output signal.
To find Ro we need to zero out vsig and compute the Thevenin Equivalent resistance seen at
the output terminals (circuit below left). Examination of the circuit show that vπ = vi = 0.
Thus, the controlled source gm vπ becomes an open circuit (circuit below right) and the
output resistance can be found by inspection to be Ro = RC k ro .
R sig
vi
B
vsig
C
+
RB
vπ
_
C
gm vπ
gm vπ = 0
ro
rπ
RC
ro
Ro
E
RC
Ro
E
In summary, the general properties of the common-emitter amplifier include a large voltage
gain, a “medium” input resistance and a “medium” output resistance.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-13
6.2.3
Common-Source and Common-Emitter Amplifiers with Degeneration
Common-Source Configuration with a Source Resistor
This circuit is the generic signal
circuit of a common-source amplifier with degeneration (i.e., with a
In this circuit the
source resistor).
input signal is applied at the gate and the
output is taken at the drain similar to a
common-emitter amplifier.
RD
C c2
R
vsig
sig
vo
C c1
vi
+
−
RL
Ro
Ri
RG
RS
We replace the MOS with its small-signal model.
Using node-voltage method (there are
two nodes, vo and vs ):
R
vsig
vi i i
sig
+
−
+
ii
Ri
Node vs :
Node vo :
G
vs − vo
vs
+
− gm vgs = 0
RS
ro
vo − vs
vo
+
+ gm vgs = 0
RD k RL
ro
vs
vo
+
=0
RS RD k RL
vo
D
gmvgs
ro
vgs
_
RD
Ro
RL
S
RG
RS
where the last equation is found by summing the first two. Substituting for vgs = vi − vs in
the first equation and computing vs we get:
vs
vs − vo
+
− gm (vi − vs ) = 0
RS
ro
vs vo
vs
+ −
− g m vi + g m vs = 0
R S ro ro
ro + R S + g m ro R S
vo
vs ×
−
− g m vi = 0
R S ro
ro
vs
[ro + RS (1 + gm ro )] ×
− v o − g m ro v i = 0
RS
Substituting for vs /RS in terms of vo from our node equations above, we get:
−[ro + RS (1 + gm ro )] ×
vo
− v o − g m ro v i = 0
RD k RL
gm ro (RD k RL )
vo
=−
vi
RD k RL + ro + RS (1 + ro gm )
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-14
The gain equation can be simplified by dropping 1 compared to gm ro in the denominator:
gm ro (RD k RL )
gm (RD k RL )
vo
≈−
=−
vi
R D k R L + ro + g m ro R S
1 + gm RS + (RD k RL )/ro
Compared to a CS amplifier with no RS , the amplifier gain is substantially reduced with the
presence of RS . However, the gain has become much less sensitive to changes in gm .
Inspecting the circuit we find Ri = vi /ii = RG , similar to a common-source amplifier.
To find Ro , we set vsig = 0 and compute the Thevenin Equivalent resistance seen at the
output terminals. We attach vx voltage source to the circuit and compute ix (circuit below
left). Examination of the circuit shows that vg = vi = 0 (gate is grounded). As such vgs is
the voltage across resistor RS (see circuit below right).
R sig
vi
ix
G
vsig
+
gmvgs
vgs
_
ro
RD
Ro
G
+
−
vx
S
+
D
gmvgs
_
RS
ix
RD
Ro
+
−
vx
S
iy
RG
ro
vgs
iy
RS
_
vgs
i y _ gmvgs
+
In circuits like this in which a resistor is directly attached between the terminals of vx (RD
in this case), it is easier to compute the current iy first:
By KCL, a current of iy −gm vgs should flow in ro and iy should flow in RS . Since vgs = −RS iy :
KVL :
KCL:
vx = ro (iy − gm vgs ) + RS iy
vx = ro (iy + gm RS iy ) + RS iy = iy (ro + gm ro RS + RS )
vx
= ro + RS + gm ro RS = ro + RS (1 + gm ro ) ≈ ro + gm ro RS = ro (1 + gm RS )
iy
vx
vx
vx
vx
ix =
+
=
+
RD
iy
RD ro (1 + gm RS )
vx
Ro =
= RD k [ro (1 + gm RS )]
ix
In summary, source degeneration has led to an amplifier with a lower gain which is less
sensitive to transistor parameters.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-15
Common-Emitter Configuration with an Emitter Resistor
Circuit shown is the generic signal circuit
of a common-emitter amplifier with degeneration (i.e., with a emitter resistor). Note
that the input is applied at the base and
the output is taken at the collector similar
to a common-emitter amplifier.
RC
C c2
R
vsig
vo
C c1
vi
sig
+
−
RL
Ro
Ri
RB
RE
We replace the BJT with its small-signal model.
vi i i
R sig
vsig
Using node-voltage method (there
are two nodes, vo and ve ) and substituting for vπ = vi − ve , we get:
+
−
iπ
B
+
vπ
Ri
_
Node vo :
gm vπ
ro
rπ
RC
Ro
RL
E
RB
Node ve :
vo
C
RE
ve − vi ve − vo
ve
+
+
− gm (vi − ve ) = 0
RE
rπ
ro
vo
vo − ve
+
+ gm (vi − ve ) = 0
RC k RL
ro
Adding the two node equations gives:
ve
vo
ve − vi
+
+
=0
RE RC k RL
rπ
→
ve
vo
vi
=−
+
R E k rπ
R C k R L rπ
We now substitute for ve in Node vo equation. Noting that 1/ro ≪ gm :
vo
1
vo
vo
vo
+
− ve
+ g m + g m vi ≈
+
− g m ve + g m vi = 0
R C k R L ro
ro
R C k R L ro
"
#
vo
vo
vo
vi
+ g m vi = 0
+
− gm (RE k rπ ) −
+
R C k R L ro
R C k R L rπ
The above equation can be solved to find the gain as:
gm (RC k RL )
vo
=−
vi
1 + (gm + 1/rπ )RE + (1 + RE /rπ )(RC k RL )/ro
gm (RC k RL )
vo
≈−
vi
1 + gm RE + (1 + RE /rπ )(RC k RL )/ro
Where we used gm ≫ gm /β = 1/rπ to simplify the denominator of the gain formula.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-16
For discrete BJT amplifiers, RC ≪ ro (thus RC k RL ≪ ro ) and the third term in denominator can be ignored. In this case,
vo
gm (RC k RL )
RC k RL
≈−
=−
vi
1 + g m RE
RE + 1/gm
which is the expression often used. Note that the amplifier gain is reduced with the presence
of RE but it has become substantially less sensitive to any change in β (only through 1/gm
term which is usually ≪ RE ).
To find Ri , we define R1 = vi /iπ . Then, by KCL:
ii =
vi
vi
vi
vi
+ iπ =
+
=
RB
RB R1
RB k R1
Ri = vi /ii = RB k R1
Since iπ = vπ /rπ , we calculate vπ in terms of vi from our node equations. Starting from
Node vo equation:
vo
vo − ve
+
+ gm (vi − ve ) = 0
RC k RL
ro
vo
vo ve
vo
vo
+
− − g m ve + g m vi ≈
+
− g m ve + g m vi = 0
R C k R L ro ro
R C k R L ro
Where we ignored ve /ro term compared to gm ve term (because gm ro ≫ 1). Since vπ = vi −ve :
gm vπ = gm (vi − ve ) = −vo
"
#
vo
1 + (RC k RL )/ro
1
1
= g m vπ = vi × −
×
+
R C k R L ro
vi
RC k RL
Substituting for (vo /vi ) from the gain equation of the previous page (2nd equation from the
bottom, before β ≫ 1 approximation), we get:
1 + (gm + 1/rπ )RE + (1 + RE /rπ )(RC k RL )/ro
vi
=
vπ
1 + (RC k RL )/ro
RE
g m RE
vi
=1+
+
vπ
rπ
1 + (RC k RL )/ro
R1 =
vi
1
vi
βRE
=
×
= R 1 = rπ + R E +
iπ
rπ v π
1 + (RC k RL )/ro
"
βRE
R i = R B k rπ + R E +
1 + (RC k RL )/ro
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
#
6-17
For discrete BJT amplifiers, RC ≪ ro (thus RC k RL ≪ ro ) and Ri ≈ RB k [rπ + βRE ].
To find Ro , we set vsig = 0 and compute the Thevenin Equivalent resistance seen at the
output terminals. Because of the presence of the controlled source, we need to attach vx
voltage source to the circuit and compute ix . Calculation is similar to that of the commonsource amplifier with RS . Calculations are left as an exercise (Hint: one should replace
′
RS in the common-source with RS case with RE
= RE k (rπ + RB k Rsig and use vπ =
′
−iy RE rπ /(rπ + RB k Rsig ). In the limit of RB k Rsig ≪ βro (a very good approximation),
the output resistance is given by
"
R o = R C k ro
βRE
1+
rπ + RE + RB k Rsig
!#
For all practical cases, the resistance in the bracket is very large and Ro ≈ RC .
In summary, emitter degeneration has led to an amplifier with a lower gain which is much
less sensitive to transistor parameters and a substantially larger input resistance.
6.2.4
Common-Gate and Common-Base Amplifiers
Common-Gate Configuration
Circuit shown is the generic signal circuit
of a common-gate amplifier . Note that
the input is applied at the source and the
output is taken at the drain. As the gate
is grounded (for signal), it is the common
terminal of input and output. Thus, this
circuit is called the common-gate amplifier.
RD
C
c2
vo
R sig
vsig
C
vi
c1
Ro
+
−
RL
RS
Ri
V DD
In some cases, the gate has to biased to
a DC value (for example using voltage divider circuit shown). However, since iG =
0, the gate remains grounded for the signal.
R G1
RD
C
c2
vo
Rsig
v sig
vi
+
−
C
c1
Ro
R G2
RL
RS
Ri
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-18
We replace the MOS with its small-signal
model. Using node-voltage method (there
is one node, vo ):
G
+
R sig
vi
_v =v
i
gs
_
D
i1
vo
gmvgs
ro
RD
RL
Ro
S
vsig
vgs = 0 − vi = −vi
ii
+
−
RS
Ri
vo
vo − vi
vo
+
+
+ gm (−vi ) = 0
RL RD
ro
vo
1 + g m ro
= vi ×
ro k R D k R L
ro
g m ro
vo
vo
≈ vi ×
→
= gm (ro k RD k RL )
ro k R D k R L
ro
vi
i1
To find Ri , it is easier to compute iY first. By KCL at node S, current iy + gm vgs will flow
in ro and current iy will flow in RD k RL . Thus:
vi = (iy + gm vgs )ro + iy (RD k RL ) = vi = iy ro − gm ro vi + iy (RD k RL )
ro + (RD k RL )
1 + (RD k RL )/ro
vi
=
≈
iy
1 + g m ro
gm
Ri = RS k
1 + (RD k RL )/ro
gm
To find Ro , we set vsig = 0 and compute the Thevenin Equivalent resistance seen at the
output terminals. Because of the presence of the controlled source, we need to attach vx
voltage source to the circuit and compute ix .
G
+
D
gmvgs
ro
vgs
R
sig
vi
ix
_
RD
Ro
G
+
−
+
vx
D
gmvgs
ro
vgs
_
RD
Ro
+
−
vx
S
S
vsig
i2
RS
ix
i2
RS
R
+
vgs
sig
_
Similar to previous cases, we start by calculating iy . By KCL, a current of iy − gm vgs should
flow in ro and iy should flow in RS k Rsig . Then, vgs = −vs = −(RS k Rsig )iy and
KVL :
vx = ro (iy − gm vgs ) + RS iy = vx = ro iy + gm ro (RS k Rsig )iy + (RS k Rsig )iy
vx
≈ ro (1 + gm (RS k Rsig ))
iy
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-19
KCL:
vx
vx
vx
vx
+
=
+
RD
iy
RD ro (1 + gm (RS k Rsig ))
vx
Ro =
= RD k [ro (1 + gm (RS k Rsig ))]
iX
ix =
In summary, the general properties of the common-gate amplifier include a large voltage
gain, a small input resistance and a medium output resistance (it has the same gain and
output resistance values as that of a common-source configuration but has a much lower
input resistance).
Common-Base Configuration
Circuit shown is the generic signal circuit
of a common-base amplifier . Note that
the input is applied at the emitter and the
output is taken at the collector. As the
base is grounded (for signal), it is the common terminal of input and output. Thus,
this circuit is called the common-base amplifier.
RC
C
c2
vo
R sig
vsig
C
vi
c1
RL
Ro
+
−
RE
Ri
V CC
R B1
In some cases, the base has to biased to
a DC value (for example using voltage divider circuit shown). In this case, a bypass capacitor is needed to keep the base
grounded for the signal.
C
Rsig
v sig
RC
C
c2
vo
B
vi
RL
Ro
C
+
−
c1
R B2
RE
Ri
We replace the BJT with its small-signal model. Comparing the small signal circuit of the
common base amplifier with that of a common-gate amplifier of the previous page, we see
that the two circuits are identical if we replace RS with RE k rπ (and RD with RC ). As such
we can use the results from the common-gate amplifier analysis to get:
vo
= gm (ro k RC k RL )
vi
1 + (RC k RL )/ro
R i = R E k rπ k
gm
Ro = RC k [ro (1 + gm (RE k rπ k Rsig ))]
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
B
+
R
vsig
− vi = vπ
_
vi
sig
+
−
Ri
vo
C
gm vπ
ro
rπ
RC
Ro
RL
E
RE
6-20
In summary, the common-base configuration has a large open-loop voltage, a small input
resistance and a medium output resistance (it has the same gain and output resistance values
as that of a common-emitter configuration but a much lower input resistance).
6.2.5
Summary of Amplifier Configurations
• The common-source (CS) and common-emitter (CE) amplifiers have a high gain and
are the main configuration in a practical amplifier. Ignoring bias resistors RG or RB , the
CS configuration has an infinite input resistance while the CE amplifier has a modest
input resistance. Both CS and CE amplifier have a rather high output resistance ro
and a limited high-frequency response (you will see this in 102).
• Addition of source or emitter resistor (degenerated CS or CE) leads to several benefits:
a gain which is less sensitive to temperature, a much larger input resistance for CE
configuration, a better control of amplifier saturation, and a much improved highfrequency response. However, these are realized at the expense of a lower gain.
• The common-gate (CG) and commons-base (CB) amplifiers have a high gain (similar
to CS and CE) but a low input resistance. As such, they are only used for specialized
applications. CG and CB amplifiers have an excellent high-frequency response. They
are typically used in combination with a CS or CE stage (such as cascode amplifiers)
• The source-follower and emitter-follower configurations have a high input resistance, a
gain close to unity, and a low output resistance. They are employed as a voltage buffer
and/or as the output stage to increase the current and power to the load.
Pages 6-25 and 6-26 include a summary of formulas for discrete transistor amplifiers. These
formulas are correct within approximation of gm ro ≫ 1 and β ≫ 1 both of which are always
valid. Many of these formulas can be simplified (before plugging in numbers) as they include
resistances that are in parallel and “typically” one is much smaller (at least by a factor
of ten) than the others. For example, in a common emitter amplifier, we often find that
RC ≪ RL and RC ≪ ro . Then, ro k RC k RL ≈ RC and the gain formula can be simplified
to Av = −RC /re .
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-21
6.3
Low Frequency Response of Transistor Amplifiers
Up to now, we have assumed that we are operating above a certain frequency such that the
coupling and by-pass capacitors would have low impedances (i.e., they were short circuit)
leading to a linear amplifier response (i.e., independent of frequency). This frequency is
called the lower cut-off frequency of an amplifier – an amplifier should be operated above
this frequency.
When we ignored capacitive affects, we found the amplifier parameters, vo /vi (or Avo ), Ri ,
and Ro which are called the mid-band parameters. These three parameters allows us to build
a model for our amplifier as is shown below (left figure) with
vo
Ri
RL
=
× Avo ×
vsig
Ri + Rsig
Ro + RL
R sig
ii
Ro
+
vsig
+
−
vi
−
io
R sig
C c1
Ri
+
−
Avo v i
vo
Ro
vsig
RL
+
−
vi
−
C c2
+
+
+
Ri
+
−
Avo v i
−
vo
RL
−
To find the lower cut-off frequency, fL , we should include impedances of coupling and by-pass
capacitors and solve the circuit in the frequency domain. This is a complicated analysis and,
even in simple cases, lead to large analytical expressions. Fortunately, we can get derive a
simple and reasonably accurate estimate of fL .
Let’s first consider a case with no by-pass capacitor – only coupling capacitors at the input
and at the output. Incorporating these capacitors in the circuit and using the amplifier
parameters we had calculated before, we arrive at the circuit above right. This circuit
should be solved in frequency domain (done here in phasor form). At the input:
Vi
Ri
=
Vsig
Ri + Rsig + 1/(jωCc1 )
Ri
1
Vi
,
=
×
Vsig
Ri + Rsig 1 − jωp1 /ω
2πfp1 = ωp1 ≡
1
(Ri + Rsig )Cc1
As can be seen, the coupling capacitor Cc1 introduced a low-frequency pole and the amplifier
gain falls at frequencies below this value. At the output:
Vo
RL
=
Avo Vi
RL + Ro + 1/(jωCc2 )
RL
1
Vo
,
= Avo ×
×
Vi
RL + Ro 1 − jωp2 /ω
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
2πfp2 = ωp2 ≡
1
(Ro + RL )Cc2
6-22
Similarly, the coupling capacitor CcC introduces a low-frequency pole and the amplifier gain
also falls below this frequency. Then:
Vo
Vi
Vo
=
×
Vsig
Vi
Vsig
Vo
Ri
RL
1
1
=
× Avo ×
×
×
Vsig
Ri + Rsig
Ro + RL 1 − jωp1 /ω 1 − jωp2 /ω
Note the first three terms are the mid-band gain of the amplifier ,vo /vsig , when capacitors
where assumed to be short circuit (see previous page). As can be seen, each capacitor has
introduced a pole.
One can show that each by-pass capacitors also generates a pole and the overall overall
frequency response of the amplifier is
vo
1
1
1
Vo
=
×
×
×
×·
Vsig
vsig
1 − jωp1 /ω 1 − jωp2 /ω 1 − jωp3 /ω
Figure below shows a typical frequency response of an amplifier with 3 capacitors.
To find fL , one should find the maximum
value of the amplitude of Vo /Vsig (which is
the mid-band gain, vo /vsig ), and then find the
frequency at which the gain is 3 dB below
this maximum value. This requires solution of
a high-order non-linear equation and is done
numerically (by PSpice). However, a simple
approximation for hand calculations (which is
surprisingly very good) is to set
fl ≈ fp1 + fp2 + fp3 + · · ·
6.4
Multi-stage Amplifiers
We had argued that we only need to solve a specific amplifier circuit once. With the amplifier parameters in hand, one can then find the response of a circuit which includes many
components.
To see this, let’s consider a 3-stage amplifier as is shown below.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-23
R sig
+
+
v sig
+
−
vi
−
Stage
1
+
+
Stage
v o,1 v i,2
−
+
+
Stage
v o,2 v i,3
2
−
−
vo
3
RL
−
−
Since the output terminals of stage 1 is attached to the input terminals of stage 2, we have
vo,1 = vi,2 . Similarly, vo,2 = vi, . We also note that vi = vi,1 and vo = vo,3 . Then:
vo,3
vo,3 vi,3 vi,2
vo
vo,3 vo,2 vo,1
vo
=
=
×
×
=
=
×
×
= Av3 × Av2 × Av1
vi
vi,1
vi,3
vi,2 vi,1
vi
vi,3
vi,2
vi,1
We also see that by definition, Ri = Ri,1 as vi = vi,1 and ii = ii,1 . Similarly, Ro = Ro,3 . We
can also find the overall gain of the circuit as (generalized to a n-stage amplifier):
Ri = Ri,1
Ro = Ro,n
vo
Ri
=
× Av1 × Av2 × Av3 × · · ·
vsig
Ri + Rsig
While the formulas above give the overall
response of the multi-stage amplifier, formulas for gain, Ri , and Ro for each stage
require knowledge of RL and RSig for that
particular stage. These can be found by
considering the stage j and replacing stage
j −1 and stage j +1 with their corresponding amplifier models as is shown below.
Comparing the resulting circuit with the
circuit which had solved for stage j (bottom figure), it is obvious that
+
Stage
j −1
Stage
j+1
−
R o,j−1
+
+
+
−
A vo v i
Stage
v i,j
j
−
v o,j
R i,j+1
−
R sig, j
+
+
v sig
Rsig,j = Ro,j−1
Stage
j
+
−
v i,j
−
Stage
j
v o,j
R L, j
−
RL,j = Ri,j+1
Therefore, since the gain and Ri formulas depend on RL , solution of a multi-stage amplifier
is started from the load side when RL of the the nth stage is known: RL,n = RL . (vo /vi )n and
Ri,n is calculated. Setting RL,n−1 = Ri,n , one can then proceed to stage n − 1 and compute
the gain and Ri . This is continued until the first stage is reached.
Since Ro depends on Rsig the procedure is reversed, i.e., we start from the first stage, compute
Ro,1 , set Rsig,2 = Ro,1 and proceed towards the load side.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-24
Summary of Discrete MOS Amplifiers•
Common Drain (Source Follower):
gm (ro k RS k RL )
vo
=
vi
1 + gm (ro k RS k RL )
R sig
vsig
C c1
vi
C c2
+
−
vo
Ri
Ri = RG
1
k RS
Ro ≈
gm
RG
Common Source:
RS
Ro
RL
RD
vo
= −gm (ro k RD k RL )
vi
Ri = RG
C c2
R
vsig
sig
vo
C c1
vi
+
−
RL
Ro
Ri
R o = R D k ro
fp3 =
RG
1
2πCs [RS k (ro + RD k RL )/(1 + gm ro )]
Common Source with Source Resistance:
gm (RD k RL )
vo
=−
vi
1 + gm RS + (RD k RL )/ro
RD
C c2
R sig
Ri = RG
vsig
Ro = RD k [ro (1 + gm RS )]
vo
C c1
vi
+
−
RL
Ro
Ri
RG
RS
Common Gate:
vo
= gm (ro k RD k RL )
vi
1 + (RD k RL )/ro
Ri = RS k
gm
Ro = RD k [ro (1 + gm (RS k Rsig ))]
RD
C
c2
vo
R sig
vsig
vi
C
c1
+
−
Ro
RL
RS
Ri
• fl = Σj fpj and fp1 = 1/[2πCc1 (Ri + Rsig )] and fp2 = 1/[2πCc2 (RL + Ro )]
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-25
Summary of Discrete BJT Amplifiers•
Common Collector (Emitter Follower):
R sig
vsig
gm (ro k RE k RL )
vo
=
vi
1 + gm (ro k RE k RL )
C c1
vi
C c2
+
−
Ri
RB
Ri = RB k [rπ + β(ro k RE k RL )]
R o = R E k ro k
RE
Ro
RL
rπ + RB k Rsig
1+β
Common Emitter:
RC
C c2
vo
= −gm (ro k RC k RL )
vi
R i = R B k rπ
R
vsig
sig
vo
C c1
vi
+
−
Ro
RL
Ri
RB
R o = R C k ro
fp3 =
vo
1
2πCe [RE k (1/gm + (RB k Rsig )/β)]
Common Emitter with Emitter Resistor:
RC
C c2
gm (RC k RL )
vo
≈−
vi
1 + gm RE + (1 + RE /rπ )(RC k RL )/ro
"
#
"
!#
βRE
R i = R B k rπ + R E +
1 + (RC k RL )/ro
R o = R C k ro 1 +
βRE
rπ + RE + RB k Rsig
R
vsig
vi
sig
+
−
Ro
RL
Ri
RB
RE
Common Base:
RC
vo
= gm (ro k RC k RL )
vi
1 + (RC k RL )/ro
R i = R E k rπ k
gm
vo
C c1
Cc2
vo
CB
Rsig
v sig
+
−
vi
Ro
Cc1
RB
RL
RE
Ri
Ro = RC k [ro (1 + gm (RE k rπ k Rsig ))]
fp3 = 1/[2πCb RCB ]
RCB ≡ RB k [rπ + (1 + β)(Rsig k RE )]
• fl = Σj fpj and fp1 = 1/[2πCc1 (Ri + Rsig )] and fp2 = 1/[2πCc2 (RL + Ro )]
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-26
6.5
Exercise Problems
Problem 1 to 12: Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
9V
9V
18k
9V
18k
22k
22k
1k
100k
vo
vo
1k
vo
vi 0.47 µF
0.47 µF
0.47 µF
vo
1k
0.47 µF
vi
vi 0.47 µF
vi 0.47 µF
22k
4V
1k
100k
100k
18k
− 5V
Problem 1
Problem 2
Problem 3
Problem 4
15V
34k
1k
100nF
4V
100
vi
vsig
0.47 µF
vo
vi
100k
+
−
5.9k
100k
4.3 mA
vo
4.7 µF
510
47 µF
− 5V
Problem 5
Problem 6
10V
5.9k
510
15V
47 µF
34k
1k
100nF
100
vsig
vi
4.7 µF
100
100nF
+
−
34k
1k
vsig
vo
100k
vi
vo
4.7 µF
100k
+
−
5.9k
510
− 5V
Problem 7
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
Problem 8
6-27
15V
34k
3V
1k
47 µF
2.3k
100nF
vi
100
vsig
vo
4.7 µF
100
100k
+
−
vsig
270
5.9k
vi
100nF
+
−
2.3k
vo
100k
47 µF
240
− 3V
Problem 9
Problem 10
3V
47 µF
1mA
100
2.5V
1k
vi
vo
vsig
100nF
+
−
vo
100nF
vi
2.3k
13k
100nF
100nF
100k
400
12k
− 3V
Problem 11
Problem 10
Problem 12
Problem 13-16. Find the bias point and amplifier parameters of this circuit (Vtn = 4 V,
Vtp = −4 V, µp Cox (W/L) = µn Cox (W/L) = 0.4 mA/V2 , and λ = 0.01 V−1 . Ignore the
channel-width modulation effect in biasing calculations.)
18V
1.3M
13V
10k
10k
0.47 µF
100
vsig
vi 0.47 µF
0.47 µF
vo
100k
+
−
100
vsig
500k
vo
vi
100k
+
−
− 5V
Problem 13
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
Problem 14
6-28
15V
13V
1.8M
10k
0.71mA
100nF
0.47 µF
vi
100
vsig
vo
100
vsig
100k
+
−
vi
vo
100nF
100k
+
−
1.2M
10k
1 µF
− 5V
Problem
15
Problem
16
Problem 18-24. Find the bias point and amplifier parameters of this circuit (Vtn = 1 V,
Vtp = −1 V, µp Cox (W/L) = µn Cox (W/L) = 0.8 mA/V2 , and λ = 0.01 V−1 . Ignore the
channel-width modulation effect in biasing calculations.
15V
9V
1.2M
10k
100nF
100
vsig
vo
vi
100
vsig
100k
+
−
10k
1 µF
vi
10k
100nF
100nF
+
−
1.8M
10k
vo
100k
− 6V
Problem 17
Problem 18
15V
10k
vo
vi
15V
1.8M
100nF
vo
100nF
vi
10k
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
1.8M
10k
1.2M
100nF
1.2M
Problem 19
10k
100nF
Problem 19
6-29
6.6
Solution to Selected Exercise Problems
Problem 1. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
9V
Bias: Set vi = 0 and capacitors open. Set vi = 0 and capacitors open.
Replace RB1 /RB2 voltage divider with its Thevenin equivalent. Assuming BJT in active,
18k
vi 0.47 µF
vo
RB = 18 k k 22 k = 9.9 kΩ
KVL:
VBB =
22
× 9 = 4.95 V
18 + 22
22k
1k
VBB = RB IB + VBE + 103 IE
9V
4.95 = 9.9 × 103 IE /(β + 1) + 0.7 + 103 IE
IE = 4.05 mA ≈ IC ,
KVL:
VBB
IC
= 20.3 µA
IB =
β
22k || 18k
9 = VCE + 103 IE
3
VCE = 9 − 10 × 4 × 10
1k
−3
=5V
Since VCE > VD0 = 0.7, assumption of BJT in active is correct.
Bias summary:
IE ≈ IC = 4.05 mA,
IB = 20.3 µA,
VCE = 5 vV 0.47 µF
i
Small-Signal: First we calculate the small-signal parameters:
IC
4 × 10−3
gm =
= 156 mA/V
=
VT
26 × 10−3
β
VA
150
rπ =
= 37.0 k
= 1.28 k
ro ≈
=
gm
IC
4 × 10−3
vo
Ri
22k || 18k
1k
Ro
Note that we could have ignored VCE compared to VA in the above expression for ro . Proceeding with the small signal analysis, we zero bias sources (see circuit). As the input is at
the base and output is at the emitter, this is a common-collector amplifier (emitter follower).
Using formulas of page 6-21 and noting RL → ∞, RE ≪ ro , and RE ≫ re :
152
gm (ro k RE k RL )
vo
=
≈1
=
vi
1 + gm (ro k RE k RL )
153
Ri ≈ RB k [rπ + β(ro k RE k RL )] = (9.9 k) k (1.28 k + 195 k) = 9.42 k (≈ RB )
rπ + RB k RSig
rπ
1
= 6.4 Ω (≈
=
)
1+β
β
gm
1
1
=
= 34.2 Hz
=
−6
2πCc1 (Ri + Rsig )
2π × 0.47 × 10 × (9.9 × 103 + 0)
R o = R E k ro k
fl = fp1
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-30
Problem 2. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
This is the same circuit as Problem 1 with exception of Cc2 and RL . The bias point is exactly
the same. As RE ≪ RL , the amplifier parameters would be the same except fl = fp1 + fp2 =
34.3 + 3.39 = 37.6 Hz.
Problem 3. Find the bias point and amplifier parameters of this circuit (Si BJT
with n = 2, β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
This circuit is similar to Problem 1 expect that the transistor
is biased with two voltage sources (values are chosen to give
approximately the same bias point).
Bias:
4V
vi
0.47 µF
vo
Set vi = 0 and capacitors open:
1k
0 = VBE + 103 IE − 5
BE-KVL:
IE = 4.3mA ≈ IC ,
100k
− 5V
IB =
IC
= 21.5 µA
β
4V
vi
4 = VCE + 103 IE − 5
CE-KVL:
VCE = 9 − 103 × 4.3 × 10−3 = 4.7 V
Bias summary:
IE ≈ IC = 4.3 mA,
IB = 21.5 µA,
1k
− 5V
VCE = 4.7 V
Small-Signal: First we calculate the small-signal parameters:
vi
0.47 µF
IC
4.3 × 10
gm =
=
= 165.4 mA/V
VT
26 × 10−3
VA
150
β
= 1.21 k
ro ≈
=
= 34.9 k
rπ =
gm
IC
4.3 × 10−3
vo
−3
1k
100k
Proceeding with the signal analysis, we zero bias sources (see circuit). As the input is at the
base and output is at the emitter, this is a common-collector amplifier (emitter follower).
The difference with Problem 1 is that there is no RB (RB = ∞) which affects Ri only.
Av =
gm (ro k RE k RL )
161
=
≈1
1 + gm (ro k RE k RL )
162
Ri ≈ RB k [rπ + (1 + β)(ro k RE k RL )] = ∞ k (1.21 k + 194 k) = 195 k
rπ
1
rπ + RB k RSig
= 6.0 Ω (≈
=
)
1+β
β
gm
1
1
=
= 3.39 Hz
=
−6
2πCc2 (RL + Ro )
2π × 0.47 × 10 × (100 × 103 + 6)
R o = R E k ro k
fl = fp2
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-31
Problem 5. Find the bias point and amplifier parameters of this circuit (Si BJT
withβ = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
This circuit is similar to the circuit of Problem 3 except that the transistor is biased with a current source.
4V
vi
0.47 µF
vo
Bias: Set vi = 0 and capacitors open.
100k
4.3 mA
BE-KVL:
0 = VBE + VE
→
IC
= 21.5 µA
β
VE = −0.7 V
CE-KVL:
4 = VCE + VE
→
VCE = 4.7 V
IE = 4.3 mA ≈ IC ,
Bias summary:
− 5V
IB =
IE ≈ IC = 4.3 mA,
IB = 21.5 µA,
4V
vi
4.3 mA
VCE = 4.7 V
− 5V
Small-Signal: First we calculate the small-signal parameters:
IC
4.3 × 10−3
gm =
=
= 165.4 mA/V
VT
26 × 10−3
VA
150
β
= 34.9 k
= 1.21 k
ro ≈
=
rπ =
gm
IC
4.3 × 10−3
vi
0.47 µF
vo
100k
− 5V
Amplifier Response: we zero bias sources (the current source becomes an open circuit. As
the input is at the base and output is at the emitter, this is a common-collector amplifier
(emitter follower). The difference with problem 3 is that here RE → ∞. Using formulas of
page 6-21 and noting RE k RL = RL ≫ re
Av =
4, 279
gm (ro k RE k RL )
=
≈1
1 + gm (ro k RE k RL )
4, 280
Ri ≈ RB k [rπ + β(ro k RE k RL )] = ∞ k (1.21 k + 5.17 M) = 5.17 M
rπ
1
rπ + RB k RSig
= 6.0 Ω (≈
=
)
1+β
β
gm
1
= 3.39 Hz
=
2πCc2 (RL + Ro )
R o = R E k ro k
fl = fp2
Comparing results from Problems 1 through 5 highlights the impact of each element on the
amplifier performance as in successive problems, RL and CC2 were added, and then RB , CC1
and RE were eliminated.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-32
Problem 6. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
15V
Bias: Set vi = 0 and capacitors open. Replace
RB1 /RB2 voltage divider with its Thevenin equivalent:
34k
100nF
100
vsig
BE-KVL:
1k
RB = 5.9 k k 34 k = 5.0 k,
5.9
× 15 = 2.22 V
VBB =
5.9 + 34
VBB = RB IB + VBE + 510IE
vi
vo
4.7 µF
100k
+
−
5.9k
47 µF
510
15V
3
2.22 = 5.0 × 10 IE / ∗ β + 1) + 0.7 + 510IE
CE-KVL:
34k
1k
5.9k
510
IC
= 14.2 µA
IE = 2.84 mA ≈ IC ,
IB =
β
15 = 1000IC + VCE + 510IE
VCE = 10.5 V
Bias summary:
> VD0
IC ≈ IE = 2.84 mA,
IB = 14.2 µA,
VCE = 10.5 V
15V
1k
Small-Signal: First we calculate the small-signal parameters:
VBB
2.84 × 10
IC
= 109 mA/V
=
VT
26 × 10−3
β
VA
150
rπ =
= 52.8 k
= 1.83 k
ro ≈
=
gm
IC
2.84 × 10−3
34k || 5.9k
−3
gm =
510
Proceeding with the small signal analysis, we zero bias sources (see circuit). As the input
is at the base and output is at the collector, this is a common-emitter amplifier with NO
emitter resistor as there is bypass capacitor.
vo
= −gm (ro k RC k RL ) = −106
vi
Ri = RB k rπ = 5.0 k 1.83 = 1.34 k
Av =
vo
Ri
vo
=
×
= −0.93 × 106 = −99
vsig
Ri + Rsig
vi
Ro = RC k ro = 0.98 k (≈ RC )
1
1
=
= 25.3 Hz
fp1 =
−6
2πCc1 (Ri + Rsig )
2π × 4.7 × 10 × (1, 340 + 0)
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-33
1
1
=
= 15.9 Hz
2πCc2 (RL + Ro )
2π100 × 10−9 (100 × 103 + 980)
1
=
2πCe [RE k (1/gm + (RB k Rsig )/β)]
fp2 =
fp3
fp3 =
1
2πCe [RE k 9.67]
= 356 Hz
fl = fp1 + fp2 + fpb = 25.3 + 15.9 + 356 = 397 Hz
Note that although Cb is the largest capacitor in the circuit (e.g., 10 times larger than Cc1 ,
fp3 is 10 times larger than the other poles.
Problem 8. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
15V
Bias: Set vi = 0 and capacitors open. The bias circuit
is exactly that of Problem 7 with RB = 5.0 k.
Bias summary:
IC ≈ IE = 2.84 mA,
34k
100nF
100
vsig
IB = 14.2 µA,
1k
VCE = 10.5 V
vi
100k
+
−
Small-Signal: The small-signal parameters are also the
same as those of Problem 7: gm = 109 mA/V, rπ =
1.83k, and ro = 52.8 k.
vo
4.7 µF
5.9k
510
Proceeding with the small signal analysis, we zero bias sources (see circuit). As the input is
at the base and output is at the collector, this is a degenerated common-emitter amplifier
(i.e, with a emitter resistor):
vo
gm (RC k RL )
≈−
= −1.91
vi
1 + g m RE
Ri = RB k [rπ + (1 + β)RE ] = 4.8 k (≈ RB )
Av =
Ri
vo
vo
=
×
= −0.98 × 1.91 = −1.87
vsig
Ri + Rsig
vi
"
R o = R C k ro
βRE
1+
rπ + RE + RB k Rsig
!#
≈ RC = 1 k
fp1 =
1
1
=
= 6.91 Hz
−6
2πCc1 (Ri + Rsig )
2π × 4.7 × 10 × (4, 800 + 100)
fp2 =
1
1
1
≈
≈
= 15.8 Hz
−9
2πCc2 (RL + Ro )
2πCc2 (RL + Rc )
2π100 × 10 (100 × 103 + 103 )
fl = fp1 + fp2 = 6.9 + 15.8 = 22.7 Hz
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-34
Problem 9. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
15V
34k
1k
100nF
100
vsig
vi
100k
+
−
270
5.9k
Bias:
240
Set vi = 0 and capacitors open. Because the 47 µF
capacitor across the 240 Ω resistor becomes an open
circuit, the total RE for bias is 270 + 240 = 510 Ω
and the bias circuit is exactly that of Problem 7 (or
Problem 9) with RB = 5.0 k.
Bias summary:
IC ≈ IE = 2.84 mA,
IB = 14.2 µA,
47 µF
15V
34k
VCE = 10.5 V
5.9k
Small-Signal: The small-signal parameters are also the
same as those of Problem 7: gm = 109 mA/V, rπ =
1.83k, and ro = 52.8 k.
Proceeding with the small signal analysis, we zero
bias sources (see circuit). As the input is at the base
and output is at the collector, this is a degenerated
common-emitter amplifier (i.e, with a emitter resistor). For midband amplifier parameters calculations, the 47 µF capacitor across the 240 Ω resistor
becomes a short circuit and the total RE for smallsignal is 270 Ω.
vo
4.7 µF
1k
270
240
1k
100nF
100
vsig
vi
vo
4.7 µF
100k
+
−
34k || 5.9k
270
240
47 µF
gm (RC k RL )
vo
≈−
= −3.55
vi
1 + g m RE
Ri = RB k [rπ + (1 + β)RE ] = 4.6 k (≈ RB )
Av =
vo
Ri
vo
=
×
= −0.98 × 1.91 = −3.47
vsig
Ri + Rsig
vi
"
R o = R C k ro
fp1 =
βRE
1+
rπ + RE + RB k Rsig
!#
≈ RC = 1 k
1
1
=
= 7.20 Hz
−6
2πCc1 (Ri + Rsig )
2π × 4.7 × 10 × (4, 600 + 100)
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-35
fp2 =
1
1
1
≈
≈
= 15.8 Hz
2πCc2 (RL + Ro )
2πCc2 (RL + Rc )
2π100 × 10−9 (100 × 103 + 103 )
We need to find the pole introduced by the 47 µF by-pass capacitor, fpb . Although this
configuration was not included in the formulas for BJT elementary configuration of page
6-21, we can extend those formulas to cover this case.
The pole introduced by the by-pass capacitor in the common emitter case is (see figure below
left)
fp3 =
1
2πCe [RE k (1/gm + (RB k Rsig )/β)]
1k
1k
100nF
100
vsig
vi
100nF
vo
4.7 µF
100
100k
+
−
Re
vsig
vi
100k
+
−
Re
34k || 5.9k
34k || 5.9k
RE
CE
vo
4.7 µF
R E2
R E1
CE
Per our discussion of Section 6.7 on how to find poles introduced by each capacitor, RE k
[1/gm + (RB k Rsig )/β)] is the total resistance seen across the terminal of Ce . As can be seen
from the circuit (above right), the resistance across Cc terminals consists of two resistors
in parallel, RE and Re . Re is the resistance seen between the emitter of the BJT and the
ground and is: Re ≡ 1/gm + (RB k Rsig )/β) from the above formula.
For the circuit here (defined RE1 = 240 Ω and RE2 = 270 Ω), the resistance across Ce is
made of two resistances in parallel: RE1 and the combination of RE2 and Re , the resistance
seen through the emitter of BJT in series. Thus:
fp3 =
fpb =
2πCb [RE1
1
k (RE2 + 1/gm + (RB k Rsig )/β)]
1
1
=
= 26.2 Hz
2π × Ce [240 k (270 + 9.17 + 0.49]
2π × 47 × 10−6 × 129
fl = fp1 + fp2 = 7.20 + 15.8 + 26.2 = 49.2 Hz
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-36
Problem 10. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
3V
Bias: Set vi = 0 and capacitors open.
BE-KVL:
100
3 = 2.3IE + VEB
vsig
IE = 1 mA ≈ IC ,
CE-KVL:
2.3k
IB = IE /(1 + β) = 5 µA
3
vi
100nF
+
−
2.3k
vo
100k
3
3 = 2.3 × 10 IE + VEC + 2.3 × 10 IC − 3
3
VEC = 6 − 4.6 × 10 × 1 × 10
−3
− 3V
= 1.4 V
3V
2.3k
Bias summary:
47 µF
IC ≈ IE = 1 mA,
IB = 5.0 µA,
VCE = 1.4 V
100
Small-Signal: First we calculate the small-signal parameters:
1 × 10−3
IC
=
= 38.5 mA/V
gm =
VT
26 × 10−3
β
VA
150
rπ =
= 150 k
= 5.26 k
ro ≈
=
gm
IC
1 × 10−3
47 µF
vi
vsig
2.3k
− 3V
Proceeding with the small signal analysis, we zero bias sources. As the input is at the base
and output is at the collector, this is a common-emitter amplifier. It does not have an emitter
resistor as 47 µF capacitor shorts out RE for signals.
Av = −gm (ro k RC k RL ) = −38.5 × 10−3 (150 k k 2.3 k k 100 k) = −85.3
Ri = RB k rπ = 10.4 k
Ro = RC k ro ≈ 2.3 k
fp1 = 0
1
1
=
= 15.8 Hz
−9
2πCc2 (RL + Ro )
2π100 × 10 (105 + 103 )
1
1
=
=
= 132 Hz
2πCe [RE k (1/gm + (RB k Rsig )/β)]
2πCe [2, 300 k 26]
fp2 =
fp3
fl = fp1 + fp2 + fpb = 0 + 15.8 + 132 = 148 Hz
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-37
Problem 11. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
3V
This is the same circuit as that of Problem 11 expect that the
transistor is biased with a current source
Bias: Set vi = 0 and capacitors open. From the circuit IE = 1 mA
vsig
IE = 1 mA ≈ IC ,
IC
= 5 µA
IB =
β
100nF
+
−
vo
100k
− 3V
VE = VEB = 0.7 V
CE-KVL:
VE = VCE + 2.3 × 103 IC − 3 = VCE − 0.7
3V
47 µF
1mA
VCE = 1.4 V
vi
100
IC ≈ IE = 1 mA,
vi
100
2.3k
BE-KVL:
Bias summary:
47 µF
1mA
IB = 50 µA,
vsig
VCE = 1.4 V.
Small-Signal: As the bias point is exactly the same as that of
problem 11, we have:
gm = 38.5 mA/V, rπ = 5.26k, and
ro = 150 k.
100nF
vo
2.3k
100k
− 3V
Amplifier response: The only difference with problem 11 is that RE → ∞ in this circuit. RE
only appears in fp3 but RE = ∞ does not change results:
Av = −37.9, Ri = 10.4 k, Ro = 0.99 k, and fl = 0 + 15.8 + 132 = 148 Hz.
Problem 12. Find the bias point and amplifier parameters of this circuit (Si BJT
with β = 200 and VA = 150 V. Ignore the Early effect in biasing calculations).
2.5V
Bias: Set vi = 0 and capacitors open.
1k
BE-KVL:
vo
RB = 12 k k 13 k = 6.24 k,
12
× 2.5 = 1.2 V
VBB =
12 + 13
VBB = RB IB + VBE + 510IE
vi
100nF
100nF
400
1.2 = 6.24 × 103 IE /(1 + β) + 0.7 + 400IE
CE-KVL:
13k
100nF
12k
2.5V
IC
= 5.8 µA
IE = 1.16 mA ≈ IC ,
IB =
β
2.5 = 1000IC + VCE + 400IE
1k
13k
400
12k
VCE = 2.5 − 1, 400 × 1.16 × 10−3 = 0.88 V
Bias summary:
IC ≈ IE = 1.16 mA,
IB = 5.8 µA,
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
VCE = 0.88 V
6-38
Small-Signal: First we calculate the small-signal parameters:
1.16 × 10−3
IC
=
= 44.6 mA/V
VT
26 × 10−3
β
VA
150
rπ =
= 129 k
= 4.48 k
ro ≈
=
gm
IC
1.16 × 10−3
gm =
Proceeding with the small signal analysis, we zero bias sources. As the input is at the emitter
and output is at the collector, this is a common-base amplifier (note RL = ∞).
vo
= gm (ro k RC k RL ) = 44.6 × 10−3 (129 k k 1 k k ∞) = 44.26
vi
1 + (RC k RL )/ro
R i = R E k rπ k
= 1 1k k 4.48 1k k 22.4 = 21.8 Ω (≈ 1/gm )
gm
Ro = RC k [ro (1 + gm (RE k rπ k Rsig ))] ≈ RC = 1 k
fp1 =
1
1
=
= 7.30 kHz
2πCc1 (Ri + Rsig )
2π1000 × 10−9 (21.8)
fp2 =
1
=0
2πCc2 (RL + Ro )
RCB ≡ RB k [rπ + (1 + β)(Rsig k RE )] = 6.24 k k 84.9 k ≈ 5.81 k
1
1
= 274 Hz
==
−9
2πCb RCB
2π × 100 × 10 × 5.81 × 103
fl = fp1 + fp2 + fpb = 7, 300 + 0 + 274 = 7.57 kHz
fp3 =
Note the small input resistance of this amplifier and corresponding large fp1 .
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-39
Problem 13. Find the bias point and amplifier parameters of this circuit (Vtn =
4 V, Vtp = −4 V, µp Cox (W/L) = µn Cox (W/L) = 0.4 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.)
18V
Bias: Since IG = 0:
1.3M
10k
0.47 µF
0.5 M
VG =
× 18 = 5 V
1.3 M + 0.5 M
RG = 1.3 M k 500 k = 361 k
100
vsig
vo
vi 0.47 µF
100k
+
−
500k
Assume PMOS is in the active state,
18V
ID =
2
0.5µp Cox (W/L)VOV
1.3M
10k
SG-KVL: 18 = 104 ID + VSG + VG = 104 ID + VOV + |Vtp | + VG
2
104 × 0.5 × 0.4 × 10−3 VOV
+ VOV − 18 + 4 + 5 = 0
2
+ VOV − 9 = 0
2VOV
500k
Negative root is unphysical, VOV = 1.89 V and VSG = VOV + |Vtp | = 5.89 V.
2
ID = 0.5 × 0.4 × 10−3 VOV
= 0.71 mA
SD-KVL:
18 = VSD + 104 ID
→
VSD = 18 − 104 × 0.71 × 10−3 = 10.9 V
Since VSD = 10.9 ≥ VOV = 1.89 V, our assumption of PMOS in active is justified.
Bias summary: ID = 0.71 mA, VOV = 1.89 V, VSG = 5.89 V, VSD = 10.9 V.
Small-Signal: First we calculate the small-signal parameters:
2 × 0.71 × 10−3
2ID
= 0.751 mA/V
=
VOV
1.89
1
1
ro =
=
= 141 k
λID
0.01 × 0.71 × 10−3
gm =
Proceeding with the small signal analysis, we zero bias sources. As the input is at the gate
and output is at the source, this is a common-drain amplifier (source follower).
gm (ro k RS k RL )
6.41
vo
=
=
= 0.866
vi
1 + gm (ro k RS k RL )
7.41
Ri = RG = 361 k
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-40
Av =
vo
Ri
vo
=
×
= 0.866
vsig
Ri + Rsig
vi
Ro =
1
k RS = 1.33 k k 10 k = 1.17 k
gm
fp1 = 1/[2πCc1 (Ri + Rsig )] = 0.94 Hz
fp2 = 1/[2πCc2 (RL + Ro )] = 3.39 Hz
fl = fp1 + fp2 = 4.33 Hz
Problem 14. Find the bias point and amplifier parameters of this circuit (Vtn =
4 V, Vtp = −4 V, µp Cox (W/L) = µn Cox (W/L) = 0.4 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.
13V
Answer:
10k
0.47 µF
ID = 0.71 mA, VOV = 1.89 V, VSG = 5.89 V, VSD = 10.9 V.
100
vo /vsig = 0.866, Ri = ∞, Ro = 1.17 k,
fp1 = 0, fp2 = 3.35 Hz, fl = 4.3 Hz.
vsig
vo
vi
100k
+
−
− 5V
Problem 15. Find the bias point and amplifier parameters of this circuit (Vtn =
4 V, Vtp = −4 V, µp Cox (W/L) = µn Cox (W/L) = 0.4 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.)
This circuit is also similar to that of problem 14 expect that it
is biased with a current source:
13V
0.71mA
0.47 µF
ID = 0.71 mA
100
2
ID = 0.5µp Cox (W/L)VOV
vsig
2
0.71 × 10−3 = 0.5 × 0.4 × 10−3 VOV
vo
vi
100k
+
−
− 5V
VOV = 1.88 V
13V
VSG = VOV + |Vtp | = 5.88 V
VSG = VS − VG = 5.88
→
0.71mA
VS = 5.88 V
VSD = VS − VD = 5.88 − (−5) = 10.9 V
(> VOV = 1.89)
100
vi
vsig
Bias summary:
ID = 0.71 mA, VOV = 1.88 V, VSG = 5.88 V, VSD = 10.9 V.
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
− 5V
6-41
2 × 0.71 × 10−3
2ID
= 0.751 mA/V
=
VOV
1.89
1
1
ro =
= 141 k
=
λID
0.01 × 0.71 × 10−3
0.47 µF
gm =
100
vsig
vi
+
−
vo
100k
This is a common-drain amplifier (source follower). Note RG = ∞, Rs = ∞.
43.9
gm (ro k RS k RL )
vo
=
= 0.98
=
vi
1 + gm (ro k RS k RL )
44.9
Ri = RG = ∞
vo
Ri
vo
Av =
=
×
= 0.98
vsig
Ri + Rsig
vi
Ro =
1
k RS = 1.33 k k ∞ = 1.33 k
gm
fp1 = 1/[2πCc1 (Ri + Rsig )] = 0
fp2 = 1/[2πCc2 (RL + Ro )] = 3.39 Hz
fl = fp1 + fp2 = 3.39 Hz
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-42
Problem 16. Find the bias point and amplifier parameters of this circuit (Vtn =
1 V, Vtp = −1 V, µp Cox (W/L) = µn Cox (W/L) = 0.8 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.
15V
Bias: Since IG = 0:
1.8M
10k
100nF
1.2 M
VG =
× 15 = 6 V
1.2 M + 1.8 M
RG = 1.2 M k 1.8 M = 720 k
100
vsig
vi
vo
100nF
100k
+
−
1.2M
1 µF
10k
Assume NMOS is in the active state,
15V
ID =
2
0.5µp Cox (W/L)VOV
1.8M
10k
1.2M
10k
VG = VGS + 104 ID = VOV + Vt + 104 ID
GS-KVL:
2
104 × 0.5 × 0.8 × 10−3 VOV
+ VOV − 6 + 1 = 0
2
4VOV
+ VOV − 5 = 0
1 µF
Negative root is unphysical, VOV = 1.0 V and VGS = VOV + Vt = 2.0 V.
2
ID = 0.5 × 0.8 × 10−3 VOV
= 0.40 mA
15 = 104 ID + VDS + 104 ID
DS-KVL:
→
VDS = 7 V (> VOV = 1.0)
Bias summary: ID = 0.40 mA, VOV = 1.0 V, VGS = 2.0 V, VDS = 7.0 V.
Small-Signal:
gm =
2ID
= 2 × 0.4 × 10−3 = 0.8 mA/V
VOV
ro =
1
1
= 250 k
=
λID
0.4 × 10−3
As the input is at the gate and output is at the collector, this is a common-source amplifier.
There is no RS because of the by-pass capacitor.
vo
= −gm (ro k RD k RL ) = −0.8 × 10−3 (250 k k 10 k k 100 k) = −7.02
vi
Ri = RG = 720 k
Ri
vo
vo
=
×
= −7.02
Av =
vsig
Ri + Rsig
vi
Ro = RD k ro = 10 k k 100 k = 9.09 k
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
6-43
fp1 = 1/[2πCc1 (Ri + Rsig )] = 2.21 Hz
fp2 = 1/[2πCc2 (RL + Ro )] = 14.6 Hz
fp3 =
1
1
1
=
=
= 143 Hz
2πCs [RS k (1/gm )]
2πCs [10 k k 1.25 k]
2π × 10−6 × 1.11 × 103
fl = fp1 + fp2 + fpb = 2.21 + 14.6 + 143 = 160 Hz
Problem 18. Find the bias point and amplifier parameters of this circuit (Vtn =
1 V, Vtp = −1 V, µp Cox (W/L) = µn Cox (W/L) = 0.8 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.
15V
Bias: Since IG = 0:
1.2M
1.8 M
× 15 = 9 V
1.2 M + 1.8 M
RG = 1.2 M k 1.8 M = 720 k
VG =
100
vsig
vi
10k
100nF
100nF
+
−
1.8M
vo
10k
100k
Assume PMOS is in the active state,
15V
ID =
SG-KVL:
2
0.5µp Cox (W/L)VOV
1.2M
10k
1.8M
10k
15 = 104 ID + VSG + VG = 104 ID + VOV + |Vtp | + VG
2
104 × 0.5 × 0.8 × 10−3 VOV
+ VOV − 15 + 9 + 1 = 0
2
4VOV
+ VOV − 5 = 0
Negative root is unphysical, VOV = 1.0 V and VSG = VOV + |Vtp | = 2.0 V.
2
ID = 0.5 × 0.8 × 10−3 VOV
= 0.40 mA
SD-KVL:
15 = 104 ID + VSD + 104 ID
→
VSD = 7 V (> VOV = 1.0)
Bias summary: ID = 0.40 mA, VOV = 1.0 V, VSG = 2.0 V, VSD = 7.0 V. Small-Signal:
gm =
2ID
= 2 × 0.4 × 10−3 = 0.8 mA/V
VOV
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
ro =
1
1
= 250 k
=
λID
0.4 × 10−3
6-44
As the input is at the gate and output is at the collector, this is a common-source amplifier
with RS .
vo
gm (RD k RL )
0.8 × 10−3 (10 k k 100 k)
=−
=−
vi
1 + gm RS + (RD k RL )/ro
1 + 0.8 × 10−3 × 104 + (10 k k 100 k)/(250 k)
7.27
vo
=−
= −0.805
vi
9.04
Ri = RG = 720 k
Ri
vo
vo
=
×
= −0.805
Av =
vsig
Ri + Rsig
vi
Ro = RD k [ro (1 + gm RS )] = 10 k (≈ RD )
fp1 = 1/[2πCc1 (Ri + Rsig )] = 2.21 Hz
fp2 = 1/[2πCc2 (RL + Ro )] = 14.5 Hz
fl = fp1 + fp2 = 16.7 Hz
Note one needs to choose RD to be several times RS for this amplifier to have a gain larger
than unity.
Problem 19. Find the bias point and amplifier parameters of this circuit (Vtn =
1 V, Vtp = −1 V, µp Cox (W/L) = µn Cox (W/L) = 0.8 mA/V2 , and λ = 0.01 V−1 . Ignore
the channel-width modulation effect in biasing calculations.
15V
Answer:
ID = 0.40 mA, VOV = 1.0 V, VGS = 2.0 V, VSD = 7.0 V.
vo /vsig = 0.866, Ri = ∞, Ro = 1.17 k,
fp1 = 0, fp2 = 3.35 Hz, fl = 4.3 Hz.
vo
vi
10k
1.8M
10k
1.2M
100nF
100nF
Amp Response (common-gate amp):
Av = 7.7, Ri = 1.1 k, Ro = 10 k, and fl = 1.45 × 103 + 22 = 1.47 kHz,
ECE65 Lecture Notes (F. Najmabadi), Winter 2013
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