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Power Up: A Power Integrity Design Approach
Introduction
Designing a clean and reliable power delivery network (PDN) for a PCB design is a challenging and sometimes daunting exercise. While Power Integrity analysis has been a very active
field, in recent years it has started to attract more attention and it now shares the stage with Signal Integrity as one of the top concerns for high-speed digital designers.
From the perspective of a high-speed digital designer, Power Integrity analysis involves looking at how the entire power delivery network responds when there is a change in current (di/
dt) and how that affects the power rail that is connected to chips on the PCB. Since the entire PDN is inductive, when you have a large change in current, the power rail will droop due to L *
di/dt. A droop (or bounce) in your power and ground rails can cause timing errors at your receiver inputs and add jitter to your sensitive SerDes interfaces. It is desirable to keep the power rail
noise within a specified range to limit the impact on your system margins. In this article we will present one method that can be used to analyze your power delivery network and help you
meet your design goals.
Setting an Impedance Target
We want to have a low impedance path from the power supply to the die. A target impedance for a power rail can be calculated by dividing the allowable voltage supply ripple by the
current draw from a device switching under load.
Ztarget = (3.3V) x (5%) / 2 Amps = 82.5 milli Ohms
It can be seen from this simple calculation that as device voltages go down and current demand goes up (as is the trend we see today) the target impedance will continue to get smaller.
Response of a Power Delivery Network
A diagram of a standard power delivery network is shown below.
The major components of the power delivery network are the die, package, the PCB planes, and the voltage regulator module. There are also several types of decoupling capacitors as
well. The role of the decoupling capacitors is to help the voltage regulator supply current when there is high demand. Each of the system components contributes to the overall inductance
of the PDN. Even the capacitors themselves have an inductance (ESL) that plays a role. The goal is to limit this inductance to maintain the target impedance. (Remember, since V=L*di/
dt, keeping the inductance small when there is a current change will help keep the voltage noise small as well.) When we view the frequency response of all of the components of a power
delivery network, we can see where the different components are effective in limiting the inductance and keeping the overall impedance low.
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From the frequency response it can be seen that the electrolytic bulk decoupling capacitor is only effective at very low frequencies (< 10 MHz). Then the high frequency ceramic
decoupling capacitors are effective up to a hundred megahertz and the package decoupling capacitors can be effective up to a few hundred megahertz. After that it’s the capacitance of the
power planes of the PCB and die that dominates into the GHz range. Of course these are just general plots of components and the overall frequency response of a PDN will depend heavily
on the actual inductance of the network and the real device characteristics of the various decoupling capacitors. By viewing the impedance in the frequency domain you can see where the
inductance of the overall PDN is suppressed by the capacitance of various components. It can also be seen that at certain frequencies the decoupling between the different components can
form a resonance with the inductance. This can often happen between the effective decoupling frequency of the package decoupling capacitors and the on-die capacitance.
The Inductive Path
The different components in the PDN add up the total inductance that the chip sees when it is switching current. The package is often one of the biggest contributors to the inductance
and careful attention needs to be paid to the package power planes to ensure low inductance paths. The PCB itself has spreading inductance through its power planes and the voltage
regulator module has an output inductance that can be significant. The use of vias also adds to the overall inductance. Even when placing decoupling capacitors on the PCB to limit the
inductance, the via pattern used to layout the decoupling capacitor has a loop inductance that needs to be accounted for.
Modeling the PDN
There are many methods available to model the entire PDN in order to validate if the target impedance has been met. We are going to look at modeling the power and ground planes in
the package and PCB as an S-parameter model that will include the full path from the VRM to the die.
In order to generate this type of model, it is best to use a commercial simulation tool such as Sigrity’s PowerSI or Ansoft’s SiWave to do the model extraction. From a high level, these tools
will use internal field solvers to calculate the S-parameters of the path from the die to the VRM, including the power and ground planes along with the vias. (Think of using a VNA to extract
the S-parameter models) One can assign ports for the decoupling capacitors to hook up external models or they can be included in the extraction. It should be noted that the VRM is not
modeled and is treated as an ideal voltage source. (The modeling and simulation of a VRM is a completely different analysis.) Once this model has been extracted, the impedance of the PDN
can easily be simulated and compared against the target impedance level.
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With the extracted S-parameter model of the PDN from the die to the VRM, both time domain and frequency domain simulations can be performed. The above diagram shows the setup
for a time domain simulation. The current of the device switching is connected to the die side of the extracted model and the ideal VRM is connected to the PCB side of the extracted model.
This way, the VRM starts by applying an ideal voltage source and by the time the voltage reaches the die through the PDN extracted model, it will have picked up the noise from the inductance in the PDN. The frequency response of the PDN model can easily be simulated in HSPICE by applying an ideal 1 V Sine Wave to the die side of the model and shorting the VRM side of
the model, performing an AC sweep, and plotting the magnitude of the response. It’s important to include the on-die capacitance and resistance with your simulation. Below is an example
frequency response of an extracted model, showing the magnitude of the impedance of the PDN.
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Power Integrity Analysis
With an extracted PDN model, the sensitivity of the PDN response due to the on-die resistance and capacitance can be analyzed and provide data that can be fed back to a design team on
the number of decap cells needed for an IO.
Back in the Time Domain
Even if you are meeting your impedance target in the frequency domain, you should always run a time domain simulation to validate the actual voltage rail noise. You will need to generate the proper current switching profile in order to measure the noise. This can be done in several ways; the easiest way (but most simulation intensive) is to hook up the SPICE IO model of
the device switching into the PDN model and measure the voltage at the die power rail.
An alternative approach is to capture just the device IO switching current into an ideal power delivery network and reuse that current profile as a PWL current source to drive the actual
PDN model. This way you use a simple current source that mimics the number of device IO’s that were switching. This can be achieved by setting up a current monitor on the power and
ground paths for an IO buffer and measuring that current when switching into a load. To measure the current for multiple outputs switching, you can put in a current multiplier by using a
dependent current source that multiplies that measured current by the number of outputs you specify.
Once you have the current profile, then you can run a time domain simulation to validate the power supply noise using the previous extracted PDN model setup.
Summary
An approach for Power Integrity was presented that showed a methodology using commercial tools to extract S-parameter models of the power delivery network and how to use that
model in time domain and frequency domain simulations to validate your PDN design. This is only one of many analytical methods available to analyze your PDN but should offer at least an
overview of how to tackle your next PDN design.
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