Rochester Institute of Technology
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Thesis/Dissertation Collections
1977
The Design of Fail-Safe Logic
Harvey Becker
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Becker, Harvey, "The Design of Fail-Safe Logic" (1977). Thesis. Rochester Institute of Technology. Accessed from
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THE DESIGN OF FAIL-SAFE LOGIC
by
HARVEY
W.
BECKER
,
A Thesis Submitted
in
Partial Fulfillment
cJf the
Requirements for the Degree of
MASTER OF
SCT~NCE
in
ELECTRI Cllli IDJG DffiERING
Approved by:
professor
Name Illegible
(Thesis Advisor)
professor
Professor
George A. Brown
---- - -- - - -.- - ----- -George Thompson
,,-------
Professor
--- -- - - -- - -----
Name Illegible
-- - ---- -- ----- (Department Head)
......
DEPARTI1ENT OF ELECTRICAL ENGINEERI"lG
COLLEGE OF ENGINEERING
RO CHESTER INSTI'fUTE OF TECfWOLOGY
ROCHEs '.r 3R, NEW YOR.T(
JUNE, 1977
ABSTRACT
This
families,
specifically
characteristics
digital
examines
paper
utilizing
classical
structure
of
and
a
The
techniques
to
are
examined.
With
The
digital
of
is
properties
examined
the
logic
the
digital
logic.
theory.
fail-safe
identifying
of
fail-safe
semiconductor
discussion
behavior
digital
of
design is
the
effects
integrated
pertinent
detect
these
of
all
types
results,
presented
11
and
failures
a
multiple
method
analyzed.
logic
of
and
to
internal
are
design is
of
and
Fail-safe
circuits
logic
logic
analyzed
presented.
failure
design
modes
for
TABLE OF
CONTENTS
LIST OF FIGURES
v
LIST OF
CURVES
vii
LIST
TABLES
viii
OF
1
INTRODUCTION
r
Chapter
I-
II
III
INTERNAL
CIRCUITS
DISCUSSION OF
.
TYPES OF LOGIC
.
IV.
.
X.
30
FAULTS
40
LIMITATIONS OF
AND
THE
CMOS
42
DISCUSSION OF FAIL-SAFE DESIGN TECHNIQUES
VII.
IX
21
THRESHOLD LEVELS
BASIC PROPERTIES
LOGIC GATE
VI.
.
6
PROPERTIES OF FAIL-SAFE LOGIC
V.
VIII
COMPONENT FAILURES OF INTEGRATED
...
51
ANALYSIS OF THE THREE TERMINAL GATE
66
THE FAIL-SAFE
80
LOGIC
GATE
104
RESULTS
107
CONCLUSIONS
109
REFERENCES
OF
FAILURE
111
APPENDIX A.
EVALUATING THE EFFECTS
MOLES
APPENDIX B.
ANALYSIS
APPENDIX
ANALYSIS OF A TTL NAND GATE
121
ANALYSIS OF A ECL GATE
1 25
C.
APPENDIX D.
OF A RTL
m
CIRCUIT
1 20
TABLE
OF
CONTENTS
(cont'd.)
Page
APPENDIX E.
ANALYSIS OF A RTL GATE USING
RAPHSON METHOD
APPENDIX F.
ANALYSIS OF A TTL
APPENDIX G
.
LOGIC
FAULT
APPENDIX H.
LOGIC
HAZARDS
APPENDIX
ANALYSIS
I.
OF
SCHMITT
NEWTON-
TRIGGER GATE.
128
132
137
DETECTION
THE
THE
147
CMOS
GATE
153
159
BIBLIOGRAPHY
IV
LIST OF FIGURES
Figure
1.
Page
NOR transistor circuit
component failures
truth
and
table
with
internal
9
2.
RTL logic
3
DTL NAND/NOR
gate
4.
Schematic
of
a
TTLrNAND
5.
Schematic
of
a
ECL
gate
19
6.
Schematic
of
a
RTL
gate
23
7.
The
AND
8.
The
NAND
9.
Logic
.
10.
gate
with
input
open-circuit
network
illustrating
fault
of
multi-valued
a
12.
internal
13.
Structure
NAND
14.
Typical
15.
Minimum
tics
Minimum
tics
Minimum
fault
lines
34
stuck-at-faults
34
masking
line
in
a
DTL
network
Illustration
tics
14
gate
output
11.
17.
H
illustrating
Example
10
circuit
equivalent
gate
logic
16.
with
gate
of
37
indistinguishable
structure
and
of
the
truth table
faults
CMOS
inverter
of
two-input
a
37
43
CMOS
43
gate
N-and-P-channel
and
for
and
for
voltages
a
voltage
four-input
maximum
the
and
of
maximum
the
MOS
transfer
NAND
voltage
two-input
two-input
5VDC
and
15VDC
47
characteris
48
gate
transfer
voltage
typical
characteris
gate
transfer
HAND
maximum
of
45
impedance
NAND
characteris
gate
for
supply
50
LIST
OF FIGURES
(cont'd.)
Page
18.
of a two-input CMOS
terminal logic gate
Comparison
three
19.
The
structure
truth table
and
NAND
gate
and
the
52
of
three
a
terminal
53
gate
20.
Minimum
tics
for
and
of
a
a
voltage
typical
three
input, V2>
secondary
21.
Secondary input
22.
input
and
transfer characteris
terminal gate with plots
maximum
output
signal
of
waveforms
the
of
of
5VDC
three
the
and
15VDC
terminal
three
..
gate
Graph
the
58
terminal
60
gate
23.
55
of
maximum
three
24.
The
25.
Voltage
fail-safe
logic
transfer
fail-safe gate
26.
Input/output
27.
The
minimum
and
terminal
structure
of
78
&1
gate
characteristics
of
a
typical
86
waveforms
and
threshold levels
gate
of
the
truth table
fail-safe
of
the
gate
..
87
element
^00
#3
VI
LIST OF
CURVES
Curve
1.
2.
3.
Page
of the RTL gate's
output voltage as a
function of the change in load resistance
Plot
of the RTL gate's output voltage as a
function of the change in input resistance
Input/output
transfer
characteristics
of
...
gate
13
a
24
gate
Input/output
RTL
5-
12
Plot
RTL
4.
....
transfer characteristics
failure in the base
a
with
Input/output
transfer
characteristics
RTL gate with failures
load resistors
Vll
in both the
of
a
resistor
of
base
.
25
a
and
26
LIST OF
TABLES
Table
1
.
2.
Page
Types
of
Sensitivity
gate
3.
Truth
of
4.
table
of
network
Truth
table
component
7
modes
for
variations
the
DTL
16
3
normal
and
in Figure
of
the
faulty
functions
output
36
9
three
terminal
gate
shown
in
61
Illustration
Internal
failure
19
terminal
6.
of
in Figure
Figure
5.
component
internal
of
gate
of
failure
Figure
modes
of
faults
of
the
three
64
19
the
three
terminal
67
gate
7.
Terminal
failure
modes
of
the
three
terminal
75
gate
8.
Identification
the
9.
Truth
table
of
the
of
fail-safe
gate
the
input/output
in Figure 24
fail-safe
terminals
of
83
84
gate
10.
Internal
failure
modes
of
the
fail-safe
gate
....
91
11.
Terminal
failure
modes
of
the
fail-safe
gate
....
98
12.
Examples
of
safe
13.
detectable
failure
modes
of
Internal
failure
the
fail
101
gate
modes
vm
of
the
element
#3
102
INTRODUCTION
intent
The
design is
with
of
to
identify
and
digital
circuits
as
ble
designed
for any
failure
to
they
other
establish
a
various
fail-safe
hdve
systems
application
use,
unable
to
method
resolve
hybrid
or
are
or
approach
modes
of
in
for
logic
electronic
and
not
adapta
potential
The
nature.
fail-safe
is
designs.
been found to
all
gates
applications
engineering
present-day
to
logic
associated
problems
single
failure
all
the
pertain
and
fail-safe
on
a
only
designmmodes,
resolves
in
for
paper
resolve
Existing fail-safe devices
be
a
writing
logic
be
and
need
that
useable
to
pertinent
many
systems.
HISTORICAL OVERVIEW
When,
device
or
demand
for
fail-safe
the
where
system
safety
which
injuries,
is
and
and
the
invented the
known.
into
come
Revolution,
in
damage.
Failure
occurrence
of
to
where
has
systems
the
With
numbers
keep
became
disasters
1
fail-safe
rapidly became
increasing
growth
major
or
being.
systems
resulted
first
known, that
is
It
devices
safer
creasing technological
as
who
not
devices have
Industrial
complex
or
pace
of
prevailed,
advent
of
more
accidents,
with
increasingly
increased
the
the
in
evident
over
the
Efforts
years.
Mine,
Industrial,
Railroad
basic
stall
The
ardent
fail-safe
the
of
supporters
devices
were
relays
replaced
proved
themselves.
that
systems
develop
ical
age
and
of
the
acceptance
for many
In
the
the
safe
laid
the
designed
but
by
around
devices
in
early
the
mid
unique
and
foundation for
and
However,
the
fact
that
very
much
in
are
to,
convert
or
is
concepts
rely
that
have
quickly
fail-safe
on
be
in the
today,
of
the
lack
electronic
we
have
a
of
device
level
of
applications-oriented.
but
that
extend
involves
in
required
integrated
to
electro-mechan
use
the
encompass
one
electronic
continued
evidence
Today
basically
application,
the
is
requirements.
design that
of
These
semi-conductor,
to
use
nature
use
design techniques may
adequate
the
circuit,
particular
in
mechanical
integrated
future,
to
legislation
such
into
devices
fail-safe
fail-safe
systems
of
came
grow.
fail-safe
the
today.
advent
systems
passed
railroads
measures.
safety
earlier
This
exist
the
With
fail-safe
the
opposed
mechanical
electro-mechanical
the
safety.
many involved fail-safe design.
of
1920's
Congress
forcing
initially
who
Traffic
and
century,
Act
legislation for
adopting
Marine,
safety devices;
railroads,
became
turn
Appliance
Safety
to
Railroad,
the
After
led
finally
beyond
general
order
to
fail
make
circuit.
SCOPE
The
scope
of
the
paper
will
be
fail-safe
logic.
The
intent
Logic
is
to
Family that
mode
of
failure
the
using
CMOS
the
modes
individual
fail-safe
to
logic
digital
of
is
of
intended
level
gate
integrated
these
resolve
techniques
it
self -checking.
function in
to
it
enable
for the
by identifying the internal
gate
the
implementing
at
will
operation,
(logical)
design techniques
establish
fault
CMOS
a
fail-safe
and
external
circuits
conditions
and
that
these
of
use
of
will
operation,
by
dynamic
complimentation
the
and
methods,
produce
a
gate.
r
first
The
failures
internal
fied
on
faults
and
the
relates
the
CMOS
will
fail-safe
these
ment
gate.
is
the
be
in
in
methods
are
in
and
and
as
analyzed
discussed
in
V,
the
the
in
CMOS
their
VII
Chapter
IX
to
of
VIII.
and
common
identi
are
in
focuses
Chapter
on
the
The
then
the
IV,
of
techniques
produce
will
results
on
limitations
and
logic
operation
Chapter
and
followed by the
Chapter
VI.
analyze
to
logic
properties
Chapter
II
then
paper
of
variation
operation
The
cir
digital
Chapter
fail-safe
of
by
logic
III.
basic
the
Chapter
A discussion
paper
Chapter
threshold
in
circuit
effects
of
operation
of
of
integrated
the
analyzes
discussed
normal
types
the
digital
the
on
requirements
gate
and
effects
is
implemented
gate
presented
of
affect
them to
logic
families
The
logic
that
general
discuss
failures
explained
and
that
of
chapters
identifies
I
circuits.
operation
logic
all
component
integrated
the
to
common
Chapter
cuits.
three
a
imple
CMOS
Nand
fail-safe
gate
results
conclusions
of
are
then brought
forth
indicate
which
the
degree
of
success
obtained.
THE
CONCEPT OF FAIL-SAFE
The
concept
ization
of
a
concept
is
inherently
and
of
definition.
risks
been any
major
to
of
a
device
agreement
or
system
to
the
risk
some
do
occur
an
absolute
mal
device
or
maximizes
and
1
>
the
in
this
A
so
of
far
It
of
design
is
that
be
safety
has
fail-safe
to
some
should
acceptance
malfunction
in
the
fail
an
entirely
definition
that
that
no
such
failures
relates
rates
design is
event
of
fail-safe
a
possibility
will
definition
and
not
characteristic
a
any
implies
the
not
should
failures
such
that
limit
as
exists.
fail-safe
it
circuit
that
There
failure
all
safety
Hence,
inherent
problems
appears
This
as
level
injury
fact
systems.
ensures
limit.
a
the
the
standard
any
sufficiently low probability
degrade
system.
preferably
interpret
in
fail-safe
fails,
system
not
intent
damage
of
specified
must
The
is
a
to
fail-safe
is. acceptable.
safety levels
exceed
There
which
due
or
what
definition that
affecting safety
that
on
precluded
with
devices
accomplish.
the
has
is
This
involved
such
using
specifically
given
fail-safe
of
the
in
safe
as
designed
a
design
mini
produce
to
malfunction
is
one
the
which
that
if the
device
least
unsafe
condition
condition.
implying
for
to
the
fail-safe
This
paper
or
will
following:
operation
and
has
property that once a fault (or faults) has
the system to malfunction, it must auto
"safe"
from which the
state
matically enter a
the
caused
system
2.
The
circuit
and
multiple
of
3.
should
The
never
leave.
be capable of acting on single
failures regardless of the sequence
must
occurrence.
circuit
device
must
failures
be
as
capable
well
as
of
internal
failures.
detecting
logical
CHAPTER
INTERNAL
COMPONENT
Internal
of
may
fail-safe
a
the
cause
is
signal
a
compounded
by
the
the
device,
then
internal
integrated
gate's
the
The
unsafe.
circuit
operation.
effects
circuit
of
1
in
ponents
used
failure
modes.
purpose
change
could
modes
determine
circuit
complexity
be
can
the
lists
digital
and
four
common
and
gates
shows
their
these
the
on
the
it
is
that
component
of
device.
the
is
of
selection
effect
Regardless
on
the
on
the
of
potential
to
can
range
misuse
the
operation
As
com
in
causes
of
of
the
an
example
of
NOR transistor
circuit
in
significance.
failures,
circuit
failures
of
component
effect
integrated
the
internal
identify
examined.
manufacturing techniques
circuit
the
analyze
component
and
digital
output
By considering different logic structures,
from processing
failures,
to
is
in
an
render
their
causes
these
to
the
at
and
The
application
If
noise,
chapter
failure
to
failures
this
failure
due
variations
and
design
erroneous
an
produce
elsewhere
of
in the
internal
an
undetectable
an
component
performance
Table
to
CIRCUITS
crucial
that
fanout,
failure
a
are
parameter
supply voltage,
produces
potential
device
of
failure
circuit
fact
The
circuit.
INTEGRATED
failures
component
ternal
of
OF
.^AILilRES
output
temperature,
I
1
TABLE
TYPES OF
COMPONENT
FAILURE MODES
COMPONENT
TYPES
Resistor
Out
of
tolerance
increase
Out
of
tolerance
decrease
OF
FAILURES
Open-circuit
Short-circuit
Capacitor
Open-circuit
Short-circuit
Diode
Open-circuit
Short-circuit
Excessive
Transistor
leakage
Short-circuit
Open-circuit
Excessive
Loss
of
leakage
beta
8
1
Figure
illustrates
by
caused
Z2
the
the
defective
output
failures
open-circuit
of
functions
Z.
R-
respect
and
R2
and
ively.
The
the
on
pact
significance
the
on
in
evaluated
device,
are
terms
internal
The
RTL
level
output
(ground
left
for
analysis
A
for
tivity
the
high;
is
the
to
(Q.
Resistor
be
of
im
digital
ccnponent
es
circuit,
sensitivity
Transistor
to
used
left
the
on
the
the
of
component
are
all
assumed
low
circuit
loading
for
illustrated
SRLB
RL
obtained
tolerances
to
for R^
and
2b.
component
to
reference
results
itt
of
RT
:he
tol
Appencix
output
are
the
as
sensi
follows:
%
=
1
-R^3R7
(PanUt
=
3)
(Fanout
=
3)
'
"B ^XLL
5EL
QVo
O
in Figure
sensitivity
with
has
of
circuit.
inputs
is
Vo
this
of
circuit
Q2)
The
effects
the
in Appendix B,
procedure.
(RTL),
of
equivalent
the
the
operation
The
determining
Logic,
illustrate
portion
i.e.,
and
given
and
the
of
effect
transistor
stability
changes
potential).
portion
erances
in
the
will
component
gate
basic
a
the
of
of
2
showing the
thei:
is
in Appendix A-
given
in Figure
characteristics
calculations
of
failures
component
output
output
Analysis
gate
and
Sample
circuit.
changes
input
of
=
1
_
RB+3R,
(2)
Tcc
R4
Rl
-WV^
i
inputs
Q1
AAAA-
R2
R3
OUTPUTS
INPUTS
NORMAL
A
B
0
0
o
r
DEFECTIVE
Zn
1*
1*
o
0
r
r
0
with
0
0
0
+
SIGNAL
Transistor Circuit & Truth
Internal
r
1*
DENOTES
NOR
r
0
0
r
Z2
Zl
Componet
FIGURE 1
Table
Failures.
10
VCC* +
qVCc--'3V
3V
R^UOju
r
va-ov
VCC"43V
"SAT.=
R^tlOJt-
8
Roi
AA#
RB? RB2"RB3
VRF
*-\r-
a
(b)
^w^
^
RB3
VBE
-^
+jVbE
VW^
(a) RTL Logic
(b) Equivalent
Gate
11
with
Circuit
FIGURE 2
of
0.7M
Loading.
(a).
)
11
It
be
can
2
2
from Eq.
seen
a
change
in the
responding
change
in Y
Figure
of
plot
of
nominal
these
plots
either
of
output
the
R
or
these
of
effects
of
the
by
of
this
is
defined
of
output
type
components
have
to
a
R
of
value
in
change
a
in
shown
significant
a
compojaent
to
ability
internal
the
as
for
detect
,
2.
Curve
the
effect
value
the
on
fan-out
a
failures
multiple
in
shown
degrade
Curves
1
of
three,
the
at
2,
and
information
the
being
gate.
the
discussion
DTL
of
DTL
ratio
in Figure
3,
=
VDD~VBES
the
gate
is
3
failures
the
is
the
on
gate.
In
I^/I^.
A^
RTL
an
in Figure
gate
of
on
failures
component
transistor
the
as
failures
internal
[l]
for
changes
However,
gate.
n-m.ls.(R^RK)
Ai
Also,
cor-
a
Simulating failures by determining
gate.
component
effect
1.
the
of
is
2,
that
seen
passive
the
the
in Figure
the
analysis
in
-D
be
will
result
Curve
function
a
Whereas
the
of
R_
will
in
plotted
as
can
logic
the
simple
processed
V0
0
RT
of
in
values
nominal
si
the
illustrates
as
the
for
value
values
it
h
sensitivity
output
in
change
the
using
From
the
that
given
An
on
showed
gate's
will
of
the
gain
the
the
outp :.t,
illustrate
current
important
current
terms
gate
gain
property
(Aj_)
whioh
circuit
as:
^Vcc-W^'^VV
1
^BB+VBES X VV/ < VDD"VBES > Rl
'
"
(3)
12
+100
RLat
a
Fa n O ut
ol
1
-
-t-80
+-60
+
40
a*
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No min
ol
>
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lL
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at
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an
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24
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z
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o
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1
J
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c
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Z
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0
2
4
6
RESISTANCE
P|ot
of
the
Change in
10
8
OF
12
RL
14
for
the
18
20
IN HUNDREDS
Output Voltage
RL
16
as a
RTL Gate
CURVE 1
OF OHMS
Function
of
26
of
the
Figure 2
13
+100
1
RE
.
-i.
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i
at
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fin
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0
Plot
of
2
3
|
1
4
5
6
RESISTANCE
OF
Rg
1
the
Change in
7
IN
Output Voltage
RR
for the
8
10
HUNDREDS
'js a
RTL Jate
CURV^
9
2
11
13
OF OHMS
Function
of
12
of
Figure 2
the
H
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l,| >Rl=2Kji.
RD
N
2K
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h
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D,
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DTL NAND/NOR Gate.
FIGURE 3
vcc
9
R2
Rl
Q3
A.
QI
N*
Q2
R4.
o-
f
Vin
K
.05
R3
2S"&
6
GND
TTL NAND Gate
FIGURE 4
vVout
m
15
The
obtained
for R
erances
of
results
R
R^,
,
gain
R
and
,
to
sensitivity
are
as
tol
component
follows:
2E*
sAi
RD
RD+RK
(4)
2H*
sAl
.
RK
RD+RK
(5)
(6)
A,
A,
RL
Various
in the
changes
have
been tabulated
vity
of
A^.
These
the
output
produced
may
cause
that
will
ivated.
at
may
the
not
always
failures
modes
and
failures
gate.
but
output
cannot
as
may
fan-out
be
the
shown
of
to
identified.
be
the
from
DTL
However,
distinguished
information
of
the
sensiti
of
failure
The
gate.
in
being
gate
3
Figure
effect
component
for the RTL gate,
degrade
the
malfunction
the
within
of
function
the
gates
particular
always
a
as
illustrate
output
failure
a
2
transistor
the
prevent
Thus,
in Table
the
tolerances
component
results
on
modes
(7)
RB
effects
a
manner
properly
can
be
detected
causing the
multiple
from
act
failure
internal
single
these
types
being
processed
of
failure
internal
by
the
16
nq
Ph
<l
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ro
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17
Analysis
gate
in Figure
of
internal
of
gate.
4
is
Appendix A
for the
sitivity to
=
to
illustrate
changes
on
the
the
given
in Appendix
C
The
variations
1
are
effects
this
of
type
with
to
reference
results
of
sen
follows:
as
=
TTL
sensitivity to
obtained
SE2
<8>
the
operation
determining
procedure.
component
bEl
used
for
analysis
changes
Transistor-Transistor Logic,
be
will
component
The
component
the
of
O)
-1
=
R2+E4-(|+1)
E4
*2
sAl.
R
(11)
R2+R4-(^+1)
2
A
Sp
From
can
the
be
=
1
that
a
effect
the
Q^
a
of
parameter
A
=
1
(13)
RT
significant
gain
S
(12)
derivedequations
seen
(10)
B.RL+R4(p+1)
when
change:
change
on
the
of
in the
gain
switched
in
Q^
,
sensitivity
to
(Eq..
value
of
Q2
the
12),
of
and
for the
R2
will
will
little
opposite
circuit
have
effect
it
a
on
state.
Also,
the
gate's
affect
18
in
performance
the
same
the
RTL
types
the
masks
identity
many
the
binary
states
Analysis
of
The
obtained
are
as
O
gate
the
of
complexity
from
exhibits
discussed
were
as
for
structure
determined
being
detectable
in only
one
of
gate.
.e
Coupled
Emitter
internal
Logic,
component
The
gate.
changes
ECL,
in
gate
changes
on
the
analysis
for determining
is
in Appendix D.
j
nent
i
sensitivity to
V0R
UK
given
component
variations
nVOR
O
2
=
-
^
the
=
the
the
value
circuit
of
R2,
norminal
TTL gate,
the
equations,
R,
,
1.
or
output
1
from
le
(Eq,.
5 it
in Figure
_ig
of
the
be
have
16),
of
sensitivity
that
a
structure
at
As
gate.
masks
the
in
change
significant
the ECL
determined
(17)
-1
seen
a
(15)
-1
=
14 to
can
will
-/els
of
=
^
(16)
+2
complexity
failures
O
O,
(14)
(14)
-
derived
for
most
cc.
be
to
:f
results
-T,
of
failures
TTL
follows.-
O^
the
~;
tyv
this
of
sensitivity to
on
the
.ost
the
of
the
From
However,
illustr.iie
will
operation
modes
failuras
allows
5
of
The
state.
output
y
gates.
and
Figure
fav.l
of
DTL
and
binary
r.
only
the
input
effect
with
the
identity
or
out-
19
o
1
l"v
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o
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FIGURE 5
o
to
a:
AY
u
E
ex
>
UJ
a:
Q
20
put
terminals
the
transistor's beta,
that
of
ECL
on
(as
gate
variations
the
ation
previous
of
the
at
the
input
output
or
that
(but
we
not
can
failures
gate,
failure
be
must
failures
degrade
gate
.
(2)
must
structure
modes;
or
must
all
be
all
be
be
change
The
detectable,
for,
and
(4)
accomplished
the
of
be
for
detection
fail-safe
failures
detection
a
information
manner
being
the
is
the
short-circuits,
the
at
a
of
that
the
suppo
necessary
operation,
internal
all
of
oper
by
output
within
Based
structures
logic
the
at
detection
(3)
on
(1)
that:
para
multiple
and
failures
.
normal
affected
Based
states
gates.
the
single
gate.
internal
of
complicated
their
the
in
binary
effects
that
more
detectable
multiple
the
can
failures
terminal)
output
shown
analysis
open-circuits,
provided
must
of
the
in
change
produce
of
one
families
of
from this
conclude
have
condition
sufficient)
component
logic
detection
will
typical logic
of
prevent
terminals
R.
with
possibility
occuring but may
unspecified
the
at
dealt
we
failures
an
in only
failures.
component
or
,
output
analysis
only increase
sition
R,
observed
digital logic
all
internal
not
R2,
discussion has
This
meter
Also,
gate.
usually detectable
are
the
the
of
of
the
gate's
types
all
leakage,
of
etc.,
internal
does
processed
by
not
a
logic
21
CHAPTER II
DISCUSSION OF THRESHOLD LEVELS
the
Whereas
problem
this
circuits,
the
internal
of
instability
of
is
that
of
types
this
types
logic
of
structure
is
level
must
causes
other
be
the
Appendix
E.
volts
creases,
at
V.^
BE
level
a
to
ability
failure
a
of
function
A
of
output
intent
of
various
the
on
of
its
maintain
faulty
a
produce
the
effect
mode
mode
independent
mode
is
level
operation.
proper
purpose
individually
it
their
is
The
the
gate's
internal
threshold
change
in this
if
it
independent
of
the
gate
failures.
of
example
V-o-n,,
0.6
to
gate
voltage,
for
considered
internal
An
determine
to
gate's
essential
threshold
failure;
of
failure
failure
this
type
such
this
will
general
integrated
of
levels.
Therefore,
the
threshold
the
and
level
gates
one
the
with
modes
analyzing
resolving
analyze
The
operation.
to
failures.
of
to
chapter
and
design techniques
themselves
other
on
threshold
internal
separately identifying
address
focus
will
of
fail-safe
failure
component
chapter
dealt
chapter
previous
as
The
room
a
the
change
function
obtained
temperature
of
results
temperature
decreases
in base-to-emitter
at
and
the
show
as
rate
that
the
of
is
junction
in
given
V^-p
is
about
temperature
2.5
in
millivolts
per
22
degree
it
as
The
centigrade.
the
affects
(Figure
is
6)
threshold
shown
the
analysis
of
is
in Appendix E.
given
RTL
the
temperature
this
of
the
input
be
3
Curve
a
input/output
same
with
the
in
value
change
nominal
of
R
is
significant
A V.
reduced
in
value
internal
gate
oVBB
by
multiple
ohms
the
threshold
components
are
by
of
plot
a
shown
has
R
the
exhibited
from
the
its
effect
level
of
constraints
is
increased
This
gate,
plot
failures
component
ECL
in
L
+100$.
voltage
as
R
given
(V-n-r,)
with
on
the
in Appendix
respect
follows:
V<W
R5
R5 ( R6+R? ) +R6 R?
R^ +R?
'
R5
because
threshold
and
-100%
of
of
effect
decrease
with
plot
effect
for
the
on
640
sensitivity
in
as
gate
illustrates
plot
of
analysis
that
-100$
value
Using the
to
a
similar
level.
the
of
failure
threshold
D,
characteristics
This
ohms.
a
the
Method,
change
The
4 is
Curve
constraint
consisting
is
illustrates
gate's
transfer
5
nominal
The
-1-
B
from its
5.
the
is
amount
gate
from the RTL
expected
V-nE
RTL
Newton-Raphson
level
additional
450
and
400k.
component
Curve
gate.
that
of
internal
an
the
value
4,
illustrates
3
r
the
an
of
to
the
by
varies
3,
in
change
from 200k
in threshold
change
Curves
Curve
can
varies
in
using the
gate,
threshold level that
level
voltage
plotted
this
of
significance
(18>
23
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-
Rl=450jj_
MJ
VA+
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o
5
Nt
v,
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Schematic
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FIGURE 6
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From
these
will
have
the
of
ECL
its
V
V
In
swing
required
allow
for
that
see
effect
added
threshold
similar
type
integrated
From
these
of
analysis
+1
(24)
Schmitt
results,
we
in
Thus,
the
1
logical
and
the
gate,
as
level
component
complexity
0
the
as
well
greater
of
voltage
levels
changes
will
before
gate.
been
trigger
can
threshold
RTL
failures
component
disadvantage
the
has
the
to
swing.
variations
some
the
on
between logical
greater
the
an
voltage
output
A
can
comparison
is
structure
affecting
we
significant
gate.
smaller
=
EE
BE
results
a
(22)
BB
SV.
(23)
-2
'
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B
BB
=
_
~
O
(21
{
]))
=2
V
r5/r7+i
calculated
circuit
determine
the
for
a
TTL
in Appendix F.
sensitivity
of
its
28
threshold
to
voltage
component
VT+
REQ
RE
RE+REQ
sv-
R
EQ.
O
REQ.
.
=f0.62
(25)
=-0.62
(26)
RE+REQ.
vT_
R2
SE^
-<W
S-T+
=
0
(27)
VBE
1
of
In
previous
reached
level
is
designs
the
resistor
A failure
input
the
signal
chapter,
from this
the
several
is
R
either
critical
will
being
applied
additional
It
parameter
provide
is
for
the
for
to
the
brought
threshold
detection
gate.
forth in the
conclusions
can
be
that
the
threshold
apparent
fail-safe
means
proper
improper
cause
conclusions
analysis.
critical
must
(29)
-1.19
in R_
level
to
addition
a
+
RE+R2
E
detection.
(28)
E
s R.
expected,
="-81
R.
V,T-
As
be
to
changes
to
logic
maintain
and
this
such
level
29
or
the
ability to
at
the
output
ficulty
the
the
the
of
on
logic
property
the
gate.
of
an
gate.
in maintaining
dependency
of
detect
the
of
The
analysis
threshold
components
and
Therefore,
providing
tolerance
out
all
has
level
parameter
fail-safe
threshold
condition
shown
because
in the
logic
detection for
the
of
dif
its
structure
must
have
gates.
30
III
CHAPTER
OF LOGIC FAULTS
TYPES
The
internal
to
the
other
types
gated
herein;
of
failure
potential
all
dealt
integrated
of
structure
i.e.,
have
chapters
preceeding
modes
potentail
the
with
failures
All
circuits.
be
shall
failures
investi
that
occur
r
to
external
sidered
to
structure
logic
faults.
identify
the
A
as
the
and
remaining types
discussion
is
given
faults
not
faults
A-
logic
or
G-.
faults
purpose
logic
various
gate
this
of
faults
fail-safe
logic
for logic
along
with
a
con
is
chapter
must
resolve.
fault
discussion
define
to
as
so
used
.
be
shall
methods
or
time
further
of
detection
hazard
2.
3.
output
to
shorted
An
be
occurs
it
intermittent
categories
general
to
regards
of
a
faults
follows:
LOGIC FAILURES
An
A logic
inputs
fault
in
considered
to
assumed
Also,
nature.
These
as
are
permanent
a
its
are
interval.
PERMANENT
1.
faults
identified
considered
once
change
or
transient
be
to
i.e.,
solid,
disappear
predefined
be
common
logic
in Appendix H.
permanent
will
of
The
faults
of
in Appendix
The
can
analyze
the
of
is
or
gate
stuck
is
a
logic
open-circuited
does
(possibly
output
at
slow
not
due
to
0 (possibly
transistors).
1
or
to
failed
respond
to
a
change
after
one
or
more
diode).
the
input
due
12]
31
(possibly
time)
due
changes
fall
4.
An
output
and
Multiple
6.
Failure
power
chip)
The
B.
0
at
deteriorating
rise
or
out
is
some
inputs
logic
1
at
others.
failures.
of
a
complete
connection
or
due to a
damage to the
(possibly
chip
break
physical
.
of
shorting
(possibly
chip
fans
which
logic
5.
7.
to
.
two or more circuits on a single
due to failure of a crossover).
INTERMITTENT LOGIC FAILURES
1.
Electromagnetic
gate
coupling
of
noise
particles
in
the
2.
Loose
3.
Unusual
4.
Temporary overheating
5.
Random
a
into
logic
a
.
wires
or
conditions
drift
circuit
the
on
of
integrated
primary
input.
power
the
of
part
circuit.
circuit.
in the delay characteristics of
is used in logic with critical
which
timing.
Fail-safe
bridging
in
faults.
logic
a
logic
bridging
A
network
be
should
capable
fault
connected
are
of
occurs
detecting
two
when
accidentally
and
leads
wired
13]
logic
can
is
occur
1.
performed
at
in the
following
inside
the
crossover
masking,
connection.
connection
etching
This
type
of
fault
configurations:
integrated
insulators,
2.
the
of
circuit
is
a
package
result
conductors,
where
a
of defective
breakdown of
etc.
packaging provides bridging
the soldering between the tiny
solder pads
on the
chip and the pins of the
Two adjacent wires may come into con
package.
tact when one shakes loose from stress or excessive
Integrated
circuit
faults
to
due
32
solder
may establish
between pads.
a
bridge"
"solder
so-called
the circuit board level shorts may be caused
defective printed circuit traces, feedthroughs,
loose or excess bare wires, or solder bridges.
At
3#
by
The
majority
level
gate
gates
bridging
happen
connections
only the
where
input
and
the
at
leads
output
logic
logic
of
involved.
are
failures
Most
of
of
in digital
MB]
faults.
They
"Stuck-At"
faults
are
to
belong
networks
which
the
cause
class
logic
a
t
input
gate's
value
1
lines
do
but
(s-@-1)
the
input
not
are
of
AND
inputs
be
For
either
the
output.
for
a
and
If
we
or
both
sitive
input
puts.
For
pattern
"Stuck-At"
there
AND
11.
and
to
are
applied
will
be
affected
possible
input
being
the
most
gate
for OR
S-@-1
is,
and
gates
possible
Some
input
i.e.,
to
the
inputs
both
when
only
11
they
failures
to
an
will
AND gate,
will
cause
a
sensitive
input
pattern
111....1.
NOR
all
four
stuck
pattern
gate's
In
value.
change,
is
values
logic
particular
00
the
one's
Exclusive-OR
the
10,
other
all
apply
input
signal
output
if
output
Therefore,
multiple
the
example,
S-@-1
are
cause
the
gate,
masked.
then
not
corresponding
that
01,
logic
at
faulty
AND gate,
00,
stuck
The
though
as
become
(S-@-0).
the
assumes
patterns;
will
masked.
an
behaves
to
0
value
assume
two-input
a
input
failures
logic
line
line
output
actually
output
considering
or
or
circuit
or
binary
line
gates
the
The
are
possible
all
change
most
sen
zero
input
in
in
patterns
33
have
sensitivity to
equal
Although
a
fixed logical
the
it
gate,
actually
logic
assumes
if
wire
to
to
it
lead
X becomes
Y
the
of
As
be
nected
8B.
to
the
that
the
the
of
is
1
However,
still
but
directly
if
the
but
B
value
the
AND
by
change
of
faults
two
of
the
of
faults
fault
single
a
their
gate
logical
certain
realized
cannot
be
and
observing
9
and
let
the
by
both
the
wire
can
output
output
that
cannot
network
logic
by
be
as
In
do
become
in Figure
independent
some
not
con
are
shown
two
circuits
alter
network.
any
implies
This
applying inputs
Consider
S-<a-1
The
of
is
(DTL)
gates
cause
faults
outputs.
"a"
input
the
outputs
outputs
detected
the
NAND
function.
physical
connected
the
the
consider
independent
NAND
7,
BC
bridging fault,
a
or
corres-
value
is
the
input
open-circuited
logical
S-@-1,
or
signal
not
in Figure
example,
which
.
do
gate
"b"
input
output
network
Figure
wire
becomes
gate
output
functions
such
the
at
logical
S-@-0
by
For
to
applied
Assuming that diode-transistor logic
presence
the
the
of
particular
value.
stuck
gate
example
Consequently,
gates
of
an
the
if
as
1,
AND
second
together
to
equal
values
assume
may
inputs
signal
fixed
AND
the
of
gate
corresponding
become
the
some
wires
independent
8.
if
used,
the
to
of
faulty
noted
becomes
also
represented
Figure
of
"a"
logical
will
"a"
that
output
that
behaves
output
ponding
be
the
assume
or
independent
value
should
network
the
input
an
faults.
stuck-at
the
to
network
truth table
34
A
o-
B
o-
O
b
O
Gates
AND
Open-Circuit
ILLustrating
Input
Lines.
7
FIGURE
STUCK
-oY
AT
FAULT
Ao-
Ao-
B
~
B~
o
oX
^Y
Pi:
Co-
o
Do-
"(b)
()
(a)
NAND
Faults.
(b)
Gates
ILLustrating
Equivalent
Output
Stuck-at-
Network.
Logic
FIGURE 8
Dn
B
o-
O
"
C
O^
Network
Fault
ILLustrating
FIGURE
9
Masking.
-o
X
35
the
of
are
in Table
shown
when
the
will
an
input
The
the
"a",
points
line
may
be
it
and
"c"
logic
assumption
a
failure
affect
circuit
1
is
of
a
such
the
gate
fault
2
it
and
at
terminals
and
emitter
both lines
situation
for
identical.
If
the
input
diode
value
of
floating.
1
will
to
the
faulty
in Figure
10,
a
short
the
transistor
(DTL
"a"
and
"b"
to
S-@-0.
depend
Two
failures,
all
possible
on
the
i,j,
input
lines
of
the
gates.
structure
observe
that
valid.
For
at
does
because
the
output
.not
possible
result
in
all
logic
gates)
to
are
said
and
control
gate's
be
that
other
stuck.
between the
Therefore,
internal
gate
inputs
is
circuit
open-
of
It
being
example,
the
corresponding
.
the
(assuming
3
gate
gates)
logic
although
value
terminal
of
may
or
if
the
3 to be logical
be
not
terminals
force
terminal
we
the
when
same
take
the
of
However,
always
input
2
gate
other
states
different
of
we
is
lines
exist
logic
consideration,
of
connected
example,
the
valued
logic
.
the
not
inputs
input
will
lines
is
an
gate
one
For
if
is
point
|j)10o)
,
the
to
only
output.
line
a
network
that
3
following
that
into
at
logic
S-@-1
are
as
the
at
assumed
singled
open-circuit
an
the
at
[0010]
,
along
is
gates
of
are
faulty
and
in Table
observe
connected
10,
normal
multi-valued
of
all
the
of
[OOOO]
-
at
"b",
We
produced
problem
Figure
In
3.
the
of
variables
be
error
ABCD
value
functions
output
will
the
base
cause
actual
structure.
indistinguishable
input
combinations,
36
TABLE
TRUTH TABLE OF NORMAL
OUTPUT
FUNCTIONS
3
(Z)
AND FAULTY
(Z3)
OF NETWORK
IN FIGURE
z
9
za
A
B
c
D
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
r
37
0>
S>
E>
Example
in
a
DTL
of a
Mult-valued
Logic
Fault
Line
Network.
FIGURE
10
E>
O
O
ILLustration
of
Indistinguishable
FIGURE
11
Faults.
38
the
output
output
the
of
the
of
gate
distinguishable
example,
given
terminals
that
line
"a"
either
always
equal
the
Similarly,
types
of
gates
line
has
a
is
S-@-1
the OR
S-@-1
is
also
for
S-@-1
the
failures
same
for
the
Any input
S-@-1
and
output
S-@-0.
"c"
line
"e"
Any input
in Figure
be
to
be
S-@-1
and
lines
to
many
S-@-0
cascaded
through
11,
be
and
gates
"a"
"c"
"e"
line
"f","G",
levels
S-@-0
"a",
S-@-1
are
of
gates.
S-@-0
being
S--1
lines
indistinguishable
the
"b"
or
line
Therefore,
"e",
other
S-@-1.
output
and
several
lines
S-@-0,
S-@-1,
.
reason.
follows:
as
propagate
is
indistinguish
NOR GATE;
with
because
gate
S-@-0.
GATE;
conditions
one)
of
input
indistin
are
to
equal
For
as
the
output
indistinguishable
are
"b"
and
terminal,
"c"
"b"
"c"
identified.
"a"
fan-out
the
line
or
be
output
and
line
in
output
example,
S-@-0
"a"
and
of
and
networks
to
,
Certain types
lines
with
failures
the
S-@-0
faults may
"G"
"a"
j.
easily
the
as
the
is
Any input
NAND
line
as
same
i
GATE;
AND
cause
1
to
can
gate
S-@-1
the
of
from line
able
For
is
(if line
guishable
for
OR
line"c"
and
failure
with
failures
an
failure
with
gate
will
will
all
will
cause
cause
"c",
"b",
For
and
line
"d"
indistinguish-
ables.
Therefore,
not
at
always
faults
easy
on
a
to
we
observe
detect.
network
level
that
The
can
common
logic
difficulty
be
in
correlated
faults
are
detecting
to
the
stuck-
39
severity
i.e., the
of
determining
more
the
task
The
procedure
based
on
network,
of
determining
the
will
detection
thus
encountered
the
complex
we
in
internal
network,
the
presence
utilize
of
in
faults
eliminating m?ny
identifying
failures
and
the
of
of
more
the
fail-safe
at
all
gates,
difficult
logic
logic
levels
difficulties
detecting
logic
of
fault.
will
the
presently
logic
is
faults.
be
logi;
40
CHAPTER IV.
PROPERTIES OF FAIL-SAFE LOGIC
The
discussions
previous
limitations
multiple
of
internal
by
establishing:
of
logic
and
(1)
logic
faults
The
and
analysis
families.
that
we
general
have
is
It
these
resolve
fail-safe
of
properties
modes
to
attempt
will
the
shown
r
(2)
logic,
(3)
the
fail-safe
pertinent
for
analysis
this
to
vious
analysis,
logic
are:
either
able
of
ponent
all
to
the
The
for
of
all
the
gates
to
remain
modes
faults,
all
and
single
ring between the
the
ability
of
failure
detect
necessary
or
or
Based
conditions
for
all
or
multiple
terminals
of
detect
of
fault
any
and
chara
the
upon
pre
the
the
ability
internal
and
logic
to
network
combinations
all
com
respond
logic
to
detect
be
or
(2)
to
insensitive
ability
and
of
fail-safe
conditions
network,
to
intent
threshold levels
gate
fault
able
the
(3)
circuits.
gate
be
the
conditions
necessary
logic
output
logic
such
the
stable
remain
at
all
(1)
the
the
(4)
and
is
It
gate.
logic,
CMOS
of
techniques
logic
identify
fail-safe
of
limitations
and
design
fail-safe
a
chapter
cteristics
advantages
occur
gates
in
network.
In
fail-safe
providing
logic
have
these
the
conditions
following
it
is
suggested
properties:
(1)
that
The
41
ability to inhibit
as
soon
as
possible
ability to
detect
operation,
(3)
be
the
changed
masking
or
logic
of
from propagating
to
after
degraded,
(4)
through the
of
or
network
ability to
tolerance"
all
can
prevent
faults
prevent
the
(6)
and
of
that
so
ability to
network
"out
level
gate
failures
gate
the
the
(5)
detection for
provide
the
by
the
at
the
(2)
detected,
detect
processed
function
circuit's
is
faults
to
ability
faults,
the
of
fault
a
logic
all
information being
not
operation
ability
circuit
in-
or
r
ternal
component
changes.
Unrestricted
failures
erroneous
for
all
possible
tection
cated
in
in
both
and
circuits
with
which
does
to
grounds,
both
power
but
different
the
dynamic
using
CMOS
fail-safe
lines,
faults,
outputs.
logic,
logic.
but
The
is
ability
to
check
some
type
is
circuit
a
inputs,
circuits
problem
can
in the
lies
in
then
any
masking
system's
Modification
considered
a
of
dupli
and
by
dyna
error
will
or
be
faults
common
multiple
ability
this
of
multiple
through
occur:
de
of
independently
both
simultaneous
also
possible
simultaneously in both
that
or
if
isolated
of
of
require
operating
appear
circuits
the
and
number
any
known that
outputs
immediately detected.
common
will
are
similar
not
cause
circuit
is
it
comparing the
mically
a
conditions
circuitry.
parallel
fault
faults may
basic
to
evaluate
concept,
characteristic
of
42
CHAPTER V.
BASIC PROPERTIES AND LIMITATIONS
OF
The
is
I.,
the
in Figure
is
to
make
its
of
limitations
the
(4)
The
utilized
The
family
CMOS
of
input
its
effect
the
CMOS
(1)
simplicity
CMOS
as
device
the
NAND
gate,
basic
building
transistors
1
of
the
Q2
and
Q3
basic
form
with
logic
chapter
gate
out
which
several
upon
Its
the
nature
of
voltage
function
as
chapter),
structure.
of
Q4
&nd
2.
to
later
a
Inverter.
input
based
in Figure
block
Q1
other
usefulness.
ability
shown
as
shown
complementary
internal
its
of
transistors
The
as
CMOS
point
is
gate
its
(3)
gates
form input
its
(discussed in
of
to
and
fail
this
of
the
of
associated
symmetry
the
intent
The
that
will
to
CMOS,
in Appendix
analyzed
structure,
compared
logic
of
is
internal
when
for
suitable
Inverter
fail-safe
the
Semiconductor,
characteristics
characteristics,
three-terminal
and
logic
characteristics:
(2)
GATE
Oxide
discussed.
selection
circuit,
transfer
to
in
LOGIC
Metal
apparent
those
useable
following
its
is
previously
The
a
simplicity
identify
it
as
basic
The
12,
families
a
herein
design.
and
CMOS
Complementary
presented
safe
THE
13,
fail-safe
are
The
tied
input
Transistor
Q3
will
be
logic.
together
gates
of
acts
as
43
QVDD
1A
Ql
P'CHANNE L
DS
V, N
' 'DP
o
I'dn
vrDD
Q2
V,ss
Ki
s.
V0
V DD
N-CHANNEL
Y,DS
V ss
J-tHh^
o^ss
Internal
Structure
of
CMOS
the
FIGURE
Inverter.
12
oVDD
TABLE
TRUTH
A
A
O-
Ql
1
f-i
B
VG
i
Q2
V
i
i
o
Q3
B
O-
0=GND.
l
=
+
10v.
Structure & Truth Table
H|
Q4
a
Two Input CMOS
Gate.
<}V,ss
FIGURE
13
of
NAND
44
a
series
its
upon
input
inverter
other
at
ground
Q3
and
1
2
and
from both
as
well
that
and
the
V^
a
This
occurs
the
positive
gate's
gate
with
inputs
both
isolated
negative
The
requirement
only
is
than VQQ.
gate
transistors
MOS
the
resistors,
conjunction
the
is
*
supplies.
transfer
combination
parallel/series
the
in the
bb
controlled
and
Q4.
circuit
equally
bb
more
Since
in
when
operate
can
gate
and
transistors,
is
output
Q1
the
of
both
JJJJ
the
output
when
the
by
depending
resistance
series
The
only
Since
positive
be
as
saturation.
V-^.
at
V^^
DD
as
V^-p.
potential
in
are
are
acts
low
or
formed
inverter
configuration.
(VQa)
Q4,
Q4
extremely high
the
in
signal
transistors
Likewise
is
which
resistance
the
with
circuit
input
region
can
by
impedances
number
transfer
The
voltage
determined
is
the
voltages,
defined
be
mainly
transistor
the
of
configuration.
(Appendix I)
are
of
inputs,
region
of
as:
AV0UT
(30)
v
'
=AV
AVMAXIMUM
AY^
in Figure
As
shown
ON
resistance
on
the
value
region
may vary
physical
of
is
the
14,
by
values
10
from
dimensions
applied
given
the
the MOS
of
ratio
of
standard
to
megohms
voltages.
the
the
of
30
ohms
transistor
For
the
the
impedance
NAND
gate
of
transistor
depending
and
the
the
the
transfer
N-channel
45
W*
Z(iil
1 -
i
3*4
106
5
\
.o5
J-C HA
NN
H
\
5
j
\
A
1(1
PD
P-CHANNEL
1
5
VDD=l0v
P-tHAiNrNtL tj
\
1
N-CHANNEL
^
,o3
5
,
102
Gs
volts)
--+Vr<;
c)
.v.,
12345
67891 V
VDD
Nip)"
,
D
.
-10
-9
-8
-7
-6
-5
Typical
-3
-4
N
-2
and
-1
P
3
Channel
FIGURE
14
Impedance. \6j
46
transistors
in
connected
in
sistors
connected
for
the
CMOS NAND gate,
can
be
defined
listed
series
bounds
(approximately) by
the
of
the
V
=
VDD
BOUND
-
[^J^,
V
DD
=
UPPER BOUND
.
Total
~E
NT
of
plot
input
of
31
eq.
NAND
this
and
in Figure
is
to
place
a
of
gate
plot
number
because
of
the
large
the
utilize
size
provide
of
any
better
illustrated
the
both
transfer
given
inputs.
in Figure
voltage
This
fail-safe
transfer
voltage
16.
can
From
vary
of
15.
transfer
two
logic
used
inputs
The
a
signifi
the
on
of
NAND
allowed
that
voltage
input NAND gate,
we
restriction
impact
network
control
these
inputs
of
gate.
restriction
in
variation
gate
number
gate.
interconnections
considering the
When
(32)
combinations
shown
the
will
per
input
all
(31)
-0.1]
Number
is
to
occur.
for
32,
=
gate,
as
can
equations
5+N-^/N^
per
gate
voltage
1
0.9-
Where ;
cance
transfer
empirical
1
four
conditions
below:
VLOWER
A
tran
p-channel
Using these
parallel.
the
the
and
of
the
but
will
will
gate
as
plots
we
observe
significantly
as
a
that
function
47
\/Tp
3.0
\/TN= +
2.0v
v
10
-^
o
^N ^
\
-
^
^
^
^DD=+10v
Y
y
1.0
Kp=
""
7
r.
i
\\
ft
0
V,
..
j
b
4-
-
-b;
:2 INPUTS
J
INPUT
o
>
USED
USED
a
_j
*
n
i
a; AI INPUTS
USED
"
=>4
o
>
o
o.
\\
1
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1
0
i
1
()
1
2
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<
^
\
s
s^
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T
i
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A
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5
5
V
IhV
Max imun
For
t he
Min
munn
1
i
7
vo
Vc Itag
:our InpLit N ANC)
Fl GUF*E
"^ ^^1:^
1
1
8
(
?
'
10
11
1 2
ts
eTr ansf(3r
G<3te.
15
Chare cteri sties
43
1
\
1
^TP
i
10
9
*TN=*2.0v
^> \
1]
y
7
-3.0v
\
^? N.
8
=
VDD=+10v
\
kn/
Kp=
1.0
b
f>
-
-
o
b;
USED
INPUT
5
>
(3
_
f
t: a
3 "4
n
4
-
9 IKJPI IT^
I KFD
O
-
?.
.
n
U
\
v\v
1
i
I
'
1
^^
\
^
1
V
1
1
1
i
^
-
T
10
V|N3
Maximum
r
i
11
12
VI,S
& Minimum Voltage Transfer Characteristics
for the Two Input NAND
FIGURE
Gate.
16
49
of
various
gate
be
spread
must
in the
gates'
and
maximum
input
parameters.
considered
threshold
voltage
NAND gate,
is
shown
In
conjunction
as
in Figure
with
in
This
transfer
plot
of
the
characteristics
a
function
17.
This
the
A
of
plot
operation
the
V-^
will
of
a
transfer
detecting
or
checking
levels.
voltage
wide
be
variations
minimum
for
the
two-
supply voltage,
utilized
fail-safe
later
gate.
on
50
SUPPLY VOLTAGE
(VDDJ
=
1, 5
v
"^
VT
\.
1A
N
14
\
VT
\
\
]
12
~
p=
\
3.0v
N=+2.0v
m/kp=1-0v
i
-
3
1
10
-
i-*
i
MAXIMUM
T
1
i-
i
i
1
C
1
i\
'
1
\
YPICAL
MNIMUAvA
1
SIJPPl
\ton
-Y
1
C>
'vdd)
=5v
.
v
^
i
\
V
o
\
VO
n
C)
e
V
*.
>
*^
i
l0
3
t
INPL T
\;olt
1 2
c3ge *
T,
(
^pi<:al
Tw O Ifnpu t
Df
16
Y V.lM
1v\a:<im um & Miliim um VoJ tag e 1 rarisfe r
<3f c1
14
(Iha rac teristics
lAhJD Ga te for Su pphi
r>
i5vd c & 15 vdc
C:u RVIE
17
Volt-
51
CHAPTER VI
DISCUSSION OF FAIL-SAFE DESIGN TECHNIQUES
The
how
cuss
the
purpose
comings
logic
faults.
ally,
it
be
can
integrated
of
the
Although
is
chapter
techniques
various
short
this
of
to
identify
to
implemented
failure
circuit
methods
are
and
dis
overcome
modes
and
individu-
presented
r
a
later
is
intended
to
chapter)
that
be
they
be
effective
(discussed in
combined
in the
use
fail-safe
of
logic.
THREE
TERMINAL LOGIC GATE
We
which
18b
shall
can
shows
function
as
the
gate
CMOS
redefined.
The
must
be
always
terminal
terminal
ically
the
all
a
three
of
difference
at
terminal
18a
Figure
being
potential
a
logic
CMOS
that
within
modified
internal
input, Vp,
to
the
to
and
constant
three
define
terminal
the
semiconductors.
take
the
but
on
normal
terminals
terminal
reference
that
input
secondary
the
secondary
change
will
gate
Figure
gate.
its
with
device
a
as
logic
operating tolerances.
given
of
held
be
not
will
gate
than the
less
(not necessarily ground)
structure
table
the
redefine
19
Figure
its
and
operating
period
shows
truth
states
of
By allowing the secondary
particular
values,
we
have
a
means
VDD (Supply
Volt.)
o
o
0-
/.
Vout
1 1 1
I-
rVss(Gnd.)
()
V2 (Secondary
Input)
<
"\
Primary
'out
Inputs
TERM.
REF.
a
o
V.ss
i
(b)
Comparison
Gate, (b)
a
of
(a)
Three
Two Input CMOS
Terminal
FIGURE
18
logic
NAND
Gate.
53
O
V2;
SECONDARY
INPUT
O-
A
h
K
ai
PR IMARY
(VDD)
1
-O
o
INPUTS
H
Q3
ho-
H
Q4
H
Q
PRIMARY
The
INPUTS
OUTPUT
v
ss
INTERNAL
STATES
A
B
vQ
Ql
Q2
Q3
Q4
1
1
o
OFF
OFF
ON
ON
o
1
1
ON
OFF
ON
OFF
o
o
1
ON
ON
OFF
OFF
1
o
1
OFF
ON
OFF
ON
Structure & Truth Table
FIGURE
of
19
a
Three Terminal Gate.
54
transforming
of
the
device.
its
from the
NAND
gate
20 along
with
a
The
all
primary
to
the
input
changes
to
propagate
functions
diagnose
list
in
of
of
of
faults
any
be
can
(2)
to
detect
and
that
such
de
gate
to
(4)
(3)
gate,
normal
and
to;
out-of-
the
of
is
in the
utilized
faults
the
at
gate
variables
operating mode,
occurring
in Figure
terminal
threshold level
output
terminal
redefined
presented
input
faults,
the
in
is
three
primary
gate
dynamic
a
three
a
definitions.
the
combinations
the
into
gate
17.,
symbol
using
set
internal
of
tolerance
in Figure
purpose
Sensitize
CMOS
transfer characteristics,
voltage
(1)
tection
basic
self-
terminals.
gate's
TERNARY LOGIC
The
(n)
value
that
a
that
such
a
0
>1
or
should
be
failure
the
1
>0
based
on
the
N-Fail-Safe
ing
function
gate
change
and
and
or
modes
should
at
Mine
(NFS)
be
this
able
ternary
could
state
output,
with
Takaoka
system
from 0
gate
all
Conversely,
fault
a
faulty input,
inputs
N)
,
of
different
fail-safe
The
1
nature
,
internal
to
a
produce
not
value
ternary
0-*N
produce
third
a
the
condition
has
occurred.
ternary (i.e.
of
produce
as
viewed
representing
property
the
[J7j
1
be
can
a
or
0,
outputs
1
output.
?-N
failure
such
that
output.
first
inputs
proposed
outputs
and
system.
They
showed
realized
by
NFS
a
a
fail-safe
which
that
system,
they
any
such
called
switch
that
55
YIN=0v
15-
14
-
VIN=5v
V2
V2
12
M AXI/V\U^\
-
14
=5v
-12
=15v
CN
>
VourOv
%
10
15
IU
.in
Vout=5v
r
3
>
LU
Vout=15v
8
i-*
O
-M
o
A
o
>
6t_
^^m^
>
1
6
r
LU
<f
H
NIM UM
"~
z
\
J.
4q
KA L
(VlHAIIV
IUM
.
Q_
z
o
r
3
u
O 2
L
V\
I
\
n
m i
^
NIM UM
'
C)
^
1
8
j
PRI MAFIY
INPUT
14
12
10
VOLTAGE
16
V||s|
Ma xirrturn & Mi nim um Voltage Transfer Characteristics
of c
pic al
Sec on dar y
Thr ee Terminal
np
V2,
of
Gate
with
Plots
5vdc & 15vdc.
FIGURE 20
for
a
56
failures
output
for any
JJ3_|
input
realization
logic
and
failures
the
extended
that
of
by
caused
Also,
Appendix
the
gates
these
for
internal
considered
binary delay
failure
the
realized.
modes
hardware
discussed
as
their
is
have
in
not
but
G),
intended
imple
can
concept,
Appendix
to
the
of
modes
it
gate
be
failure,
faults
logic
which
by extending
logic
1**(0,1),
>(1,0),
cannot
and
the
Where
elements
(discussed in
logic
short
1^-0,
)
Ibaraki
and
However
outputs.
M
double-line
on
0-*
coding:
0
nor
machines.
based
is
WO
Takaoka
sequential
and
were
terminal
basic
Hi.
failures,
However,
two-rail
to
dual
of
undetectable
H.
three
or
inputs
utilized
additional
0-^N
(neither
>N
machine
consideration
mentation
with
a
use
for
logic
binary
such
asymmetric
no
1
concept
makes
N^-(1,1)
or
0-*-N
are
only
with
overcome
comings.
SELF -CHECKING
In
order
to
necessary
to
the
to
that
will
dent
of
within
gate.
be
the
the
periodic
to
the
It
location,
network.
is
this
to
type
The
is
It
detectable,
at
the
interruption in
some
of
the
it
observable
fault,
or
is
for
normal
output,
composed
V2>
not
output
quantity
secondary,
is
occurrance
only necessary
self-check
to
fault's
the
behavior
normal
applied
be
propagate
propagated
signal
to
output.
interrupt
failed
fault
a
able
observable
some
fault
be
for
input
of
operation
indepen
faults
of
of
the
a
of
the
57
three
terminal
to
having
the
level,
gate
failure
on
testing
perform
accomplish
output
for
oughly
test
to
for
for
capability
continuous
the
fault
a
the
provide
internal
all
for
faults,
of
checking
the
and
dependence
the
to
(5)
all
to
normal
circuit's
to
capability
and
to
able
faults
all
prevent
be
will
outputs
propagate
(4)
detection,
we
Isolate
(3)
operation,
hardware
external
(1)
gate
separate
provide
of
the
on
following:
(2)
modes
By keeping the primary input from
gate.
thor
the
provide
gates.
t
In
logical
be
can
a
value
varies
generated
and
three
terminal
gate.
has
waveform
as
a
previously
OFF
duty
cycle
in
errors
an
This
be
applied
into
to
three-terminal
for
a
input
variables,
F,
if
normal
operation
the
the
the
21
failure,
designed
observing
Carter
The
of
variables,
variables,
in F
N,
of
\\j
Schneider
and
gate.
A,
a
and
causes
the
concept
We
can
self-checking logic
set
forcing
of
interrupting
of
test.
a
fault
detect
and
as
each
to
circuit
the
the
alter
method
three -terminal
of
in T
the
gate
set
will
the
to
addition
variations
capability
by
in
.
of
signal
used
have
perform
input
(periodic)
input
modes,
the
introduced
the
primary
signals
to
secondary
Circuits
.
behavior
predictable
the
additional
requires
some
in Figure
failure
some
signal
"Self-Checking"
will
to
shown
periodic
operation
normal
applied
(T0W/TpERI0I))
erroneous
output.
to
with
whose
signals
circuit,
in time
During
discussed
due
T^.^,
and
functioning
normally
a
define
gate
secondary
a
fault
set
non-cyclic
of
output
58
PERIOD
-
V.
OFF
ON
-y,
FIGURE 21
Secondary
the
Input
Signal
Three Terminal
of
Gate.
59
for
to
input
some
insure
faults
take
one
that
be
an
is
during
then
applied,
during
error
fault
no
normal
we
least
at
in F
should
and
gate.
the
of
illustrated
is
operation
for
operation
logic
waveforms
if
Hence,
applied
self -checking
output
and
normal
inputs
multiple
and
single
detectable.
primary
totally
a
input
The
gate
of
is
be
will
undetectable
device
for
conditions
set
a
Self-checking is necessary
N.
and
occur
that N
period
the
all
that may
A to
cause
in A
three -terminal
in Figure
22,
r
4
Table
and
states
for
states
of
denote
the
is
a
inputs
all
all
truth table
modified
and
internal
applied
outputs
conditions
waveforms
illustrate
V0UT'
V0UT'
tlie
ternary
table
shows
T2
.
with
set
The
truth
the
application
to
V T->T
and
states
change
ternary
inputs
self -checking
DYNAMIC
an
in
and
at
V?
ternary
inPu"t
the
For
-
all
gate
and
four
manner.
used
in Figure
19.
states;
Vnnrp>
V^,
state
example,
state,
outputs
states;
normal
symbols
output
internal
complementary
the
ability
indication
failure
of
changes
a
The
illustrated
as
the
the
as
logic
the
v^,
and
variations
when
A
and
B
are
semiconductors
Therefore,
complementary
cycling
the
provide
level.
OUTPUT
The
is
Vo
well
semiconductors.
These
and
as
both
showing
the
gate
of
that
a
it
should
gate
is
not
to
remain
in
functioning
enter
into
a
dynamic
properly.
a
state
or
state
Upon
sequence
60
^Ti-^ *-T2-*
V2
V2
"
SECONDARY
INPUT, V2
vIKi
IIN
Z>
V|M
IrN
l
*:1
LU
i
PRIMAR Y
o
1
INPUT, VIN
<
1
1
o
V.N"
>
vo
V|N~
'2
<*
i
PRIMARY
V.N
INPUT,
Z
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consider
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denotes
fails
the
situation
the
be
one
fault
gate,
we
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failure
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the
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logic
to
to
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be
discussed
to
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if
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fj
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red
when
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system
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the
actual
the
may
undesir
be
must
either
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traffic
accident
failures
to
regardless
while
an
,
lights.
the
light
then
example,
and
light
no
fail-safe
the
assumed
S-@-0
a
or
three -terminal
for both S-@-1
to
faults
produce
a
at
a
(1,
1),
for
some
to
gate,
method
the
of
gate.
dynamic
categories
and
so
of
the
The
a
of
perma
pattern
input
detect
or
lack
internal
ability
is
fault
pat
the
by complementing
change
detecting
both
to
as
sensitive
input
non-sensitive
vary
output
most
stuck-at
any
Therefore,
gate.
the
a
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applying
combination
output
the
of
pattern
is
the
(0, 0)
cause
faults
gate
by
then apply
we
gate
that
output
gate's
If
output
red
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green
go
the
fail
all
or
stop,
component
they
and
logic
modes.
the
will
systems
both.
not
red
dangerous,
that
attempt
have
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input
is
road
i.e.,
way,
light
green
characteristic
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to
a
or
show
the
on
failure.
upon
state
state
fail-safe
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with
safe
should
situation
shows
on
a
dangerous
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occur.
to
denotes
a
actual
output
controller
controller
controller
able
safe-side
light
green
the
a
detectable.
not
traffic
a
light
of
are
of
measure
of
change
failures
fail-safe
of
its
63
failure
the
When
is
an
to
all
and
1
0
or
be
not
of
through
have
discussed the
terminal
is
a
to
the
of
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produce
of
one
We
gate
to
three-
multiple
dynamic
method
failed
circuit.
(fail-safe
arrangement
a
state
detected
be
can
three-terminal
a
in
remain
static
a
logic.
such
By applying this
faults
output
of
will
to
change
complementary
possible
it
propagation
of
ability
output.
in
gates
it
gate),
fault
ternary
a
the
the
to
another
this
multiple
by
masked
gate
produce
and
dynamic,
failure.
safe
a
characteristic
be
and
state
single
gates,
to
ceases
indication
will
important
an
output
the
either
and
mode
for
output
detection.
COMPLEMENTATION
The
the
in
nature
analysis
of
the
now
is
to
The
purpose
the
three-terminal
its
resolve
inherent
of
lustrated
in Table
5.
Vo
,
the
normal
for
output
output
shows
the
fault
is
the
state
state
output
is
gate
(later
illustrate
that
the
will
such
require
in detail
chapter).
limitations
method
to
failures
is
a
of
difficulties.
analysis
S-@-1
discussed
fail-safe
gate
An
being
is
complementation
of
particular
1
Item
input
will
(Table
of
the
table
conditions:
be
V^Ti-m-
4),
identical.
undetectable.
internal
Also,
for
VTTJ
shows
(A
Comparison
the
This
same
and
to
input
indicates
examining Figure
il
for Q1
B),
and
the
states,
that
the
19 for
all
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internal
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being
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defined
as
causes
(V
a
short
terminal).
is
unable
type
of
undetectable, failure
5.
Table
Analysis
the
For
of
normal
that
the
within
the
detect
these
Figure
(non-failure)
secondary input
the
gate's
using
in
a
a
later
this
gate's
fail-safe
chapter)
type
is
Table
state,
is
structure.
three -terminal
by
and
.
gate
above,
from the
conditions,
19
1
item
the
shown
Is
Q3
4
in
assumed
shows
but
low, V?,
These
usefulness
items
the
during
an
two
Another
2
to
be
(to be
be
in
interval
limitations
can
of
S-@-0.
to
output
.the
3
and
open-circuit
which
configuration
"terminal
>
three-terminal
failure.
of
that
shows
(V-mO
V2>
Consequently,
gate
to
for
be
exists
restrict
overcome
presented
66
CHAPTER VII
ANALYSIS OF THE THREE TERMINAL GA.TE
The
purpose
terminal gate,
4,
for
as
internal
from
discussed
in the
of
gate's
fault
chapter
detection
it
and
is
analyze
the
and
defined
in Table
faults.,
failures
and
level.
The
intended
to
show
them
methods
into
implemented
are
by combining
obtained
three-
to
threshold
its
previous
operation
19
logic
modes,
in
changes
is
chapter
in Figure
shown
failure
resulting
the
this
of
degree
the
in the
manner
described herein.
INTERNAL
FAILURES
For
gate,
this
(A, B)
00
variables:
The
(ON),
S-@-1
or
internal
ent
circuit
or
a
or
(OFF).
failure
short-circuit
This
all
the
selected
to
occur
defined
are
definition
be
of
the
transistors
combinations
failures
(Figure
of
19)
of
input
sequence
as
Q1
these
is
random
sequence
S-@-0,
all
by
a
perman
short-
through Q4
transistors.
open-circuits
are
the
before
represented
14,
of
assumes
can
Figure
three-terminal
sets
modes
resistance,
possible
of
The
assumed
failures
of
open-circuit
variable
All
,
11,
are
modes
types
begins,
10
inputs
through
sequeaced
01
failure
the
but
are
,
the
analysis
tabulated
and/or
in Table
6.
TABLE
67
6
INTERNAL FAILURE MODES OF THE THREE-TERMINAL GATE
SECONDARY
INPUT
v2
FAULT
CONDITIONS
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OO
01
(0
ON
ON
OFF
OFF
V0
Vo
OF
ON
V6
VX
OFF
ON
V0
Vo
Vo *y0
Vo Vo
v2
ON
ON
yo
Vo
V0
V0
Vo
Vo
yQ
v0
y2
OFF
vA
OFF
Vo
Vo
Vo
yQ
v0
v2
y2
V2
=,2
Y.o
o
*v,
Vo
^O
V,o
Vo
*
y2
v2
y2
ON
ON
y_o
V0
OFF
OFF
1
Vo
Vo
o
V
%
o
o
Vo
V0
Vo
o
1
Vo
V0
Vo
'o
Vo
Vo
^o
V,
V,o
Vo
^o
Vo
v0
#V0
Vo
Vo
v2
ON
ON
V,o
Vo
vo
V,o
y2
v2
OFF
OFF
V6
V6
Vo
7,o
Vo
yo
v2
p
y2
ON
v
ON
2
y0
Vo
*
y2
v2
=^2
OFF
OFF
"*V
*
*v,
-ip
Vo
74
table
The
nomal
identifies
in
symbol
the
6,
we
of
internal
a
can
double
of
the
Table
output
can
asterisk,
to
stuck-at-fault
for
given
modes
circuit
by
the
into
its
LOGIC
ary
be
We
and
(3)
always
observe
be
detected
the
output.
detected
by
the
fail-safe
the
short-
or
at
of
the
that
open-circuit
are
parti
a
seen
as
implementation
of
6
not
contribute
not
However,
gate
three -terminal
gate
FAULTS
that
terminal
modes
can
may
sequence,
structure.
Table
faults
Table
does
Vo,
by
terminal
output
specified
variables.
operation,
modes
choice
of
the
at
failures,
of
combinations
identified
those
the
combination
items
of
failure
these
for
types
input
of
asterisk
gate
these
cular
double
detected
secondary input,
periodic
set
be
Table
By examining
possible
except
the
before
asterisk
all
from its
changes
column.
(1)
stuck-at-faults,
significantly
a
sequence
that:
conclude
output
the
4) by
three-terminal
the
(2)
(of
value
the
when
7 is
will
gate.
may be
input,
detection.
a
tabulation
appear
table
This
detected
V2
does
at
at
not
the
of
all
terminals
indicates
the
combinations
gate's
contribute
of
these
output
but
logic
three-
the
that
of
failure
the
significantly
to
second
their
75
7
TABLE
TERMINAL FAILURE MODES OF
THE
THREE-TERMINAL GATE
SECONDARY
INPUT
FAULT
CONDITIONS
INPUT
ON
LINES
OUTPUT
INPUT
SEQUENCE FOR
SEQUENCE OF
'
A
Vo
B
OO
01
10
11
V,
S-@-0
NORMAL
vo
To
V,
V,
S-@-0
NORMAL
V,0
V,
V,
Yr
Vr
S-@-1
NORMAL
V,
To
Y-0
Yr
S-@-1
NORMAL
V,
V,
V
V
NORMAL
S-@-0
K
To
70
Vo
NORMAL
S-@-0
V
V,
V,
12
NORMAL
S-@-1
*0
K
*Y-0
*0
Vo
NORMAL
S-@-1
^0
\
f0
f0
12
S-@-0
S-@-0
vo
*0
V
*vo
Vo
S-@-0
S-@-0
^0
f0
^0
fo
I2
s-@-o
S-@-1
Yo
'0
Vo
s-@-o
S-@-1
^0
fo
0
0
0
*v,
0
0
0
0
0
0
0
*v,
0
0
*v
0
V
0
*0'
*vo
f0
^0
76
TABLE
SECONDARY
INPUT
v2
FAULT
7
(cont'd)
CONDITIONS
INPUT
ON
LINES
A
OUTPUT
INPUT
B
OO
SEQUENCE FOR
SEQUENCE OF
01
10
11
T0
To
*vo
vo'
Y-2
S-@-1
S-@-0
v2
S-@-1
S-@-0
?0
'o
?0
^0
12
S-@-1
S-@-1
*I0
*I0
*\
*0
v2
S-5-1
S-@-1
*I0
*Io
%
**0
SECONDARY
FAULT
INPUT
v2
CONDITIONS ON
OUTPUT
Yo
Y-2
S-0--0
V2
s-@-o
v2
LINE
OUTPUT
INPUT
00
*V
-0
*Y
SEQUENCE FORE
SEQUENCE OF
01
*V
-0
*Y
10
*V
-0
*Y
11
**Y
-0
-0
-0
-0
*^o
S-@-1
V
V
Y0
*v
S-S-1
^0
fo
fo
fo
77
THRESHOLD FAILURE MODES
The
purpose
for
complementation
is
a
graphical
maximum
gate
and
to
threshold
output
may
along
the
to
the
the
Vn
input
secondary
point
the
detect
and
Y
marginal
failures
posite
direction,
result
in
periodic
value,
a
an
marginal
outputs.
the
gate's
or
beyond
the
C),
to
output
that
gate
to
from
from
could
V2,
minimum
value,
and
result
Therefore,
the
values
transfer
curve
will
the
cause
the
determine
in
X),
its
would
types
selected
VQ
Faults
which
similar
with
beyond
curve
shift
of
for V2,
the
occurs
from y~
to
point
Vq
either
(V2),
in
to
may
VQ
increase
this
increase
transfer
VQ
to
,
Likewise,
(point A decreasing to
change
failures
change
failures
that
observed
When
will
shift
the
shift
is
effect
faulty
a
marginal
X.
gate's
open-circuit
(point B)
fault.
(point
level,
signal,
fault
point
marginal
any
any
level,
marginal
Vo
output
check
(V2)
line
the
cause
an
it
the
which
failures may
23,
23
three-terminal
producing
low, y_2,
three-terminal
at
cause
and
is
the
of
than
Figure
threshold
this
threshold
normal
input
by
in
failures
other
gate
20
Figure
transistor
Figure
modes.
marginal
Referring to
normal
of
of
mode
the
of
threshold
output
a
then these
secondary
cause
in
level
signal.
the
when
failure
internal
if
internal
provide
threshold levels
fail
short-circuit,
the
to
representation
illustrated.
are
is
V2
threshold
minimum
transistors
or
of
Also,
.
the
op
will
in the
maximum
appear
as
detectable
V2,
and
threshold
73
NPUT
Graph
of
of
Maximum
the Three
VOLTAGE
,
volts
& Minimum Threshold Levels
Terminal
Gate.
FIGURE
23
79
tolerance, i.e.,
fault
point
able
as
a
A to
logic
self-checking
the
that
degree
detectable.
is
from
by
the
of
B,
If
the
fault
the
the
periodic
specified
gate
which
marginal
output
by
three-terminal
exceeds
a
in
as
may
fault
shift
following
causes
gate.
tolerances.
as
a
to
enough
secondary input
well
(threshold)
marginal
a
shift
be
detect
Therefore,
is
threshold
accomplished
detection
80
CHAPTER VIII
THE FAIL-SAFE LOGIC
The
the
purpose
fail-safe
F.S.G.
Chapter
in
the
as
logic
consist
formation
be
The
fail-safe
the
exist
within
will
(state)
gates;
CMOS
be
and
observed
the
of
as
the
the
indicate
The
fail-safe
two
consisting
INVERTER gate,
a
circuit
24.
gate
of
the
be
is
of
of
composed
input
interconnected
a
multiple
in
that
a
correct
failure
gate
for
sensitized
if
in
change
a
if
any
the
then
faults
its
no
are
incorrect,
correct
or
value
faults.
three-terminal
CMOS NAND
as
de
to
fault
of
be
applied
states
output
presence
two
to
correct,
complement
is
the
faults
circuit
Therefore,
variables
is
of
of
constructed
The
such
variables
fault.
output
If
said
input
input
gate.
observed
is
gate
primary
primary
modes
transformation
result
and
dual-output
can
gate
for processing
the
gate,
fail-safe
failure
the
of
detectability
lines
gate's
analyze
techniques
primary
is
of
limited
the
of
in Figure
the
and
operation
shown
of
combination
define
as
set
V-,-,
The
The
gate.
particular
output
it
of
to
utilization
the
resolve
detectable
any
F.S.G.
the
gates,
to
as
function.
a
and
is
chapter
multiple -input,
any
CMOS
inputs
will
VI
three-terminal
fined
with
logic gate,
illustrate
will
in
this
of
GATE
shown
gates
and
in Figure
one
24.
81
2>v,
+
vIN
B
GROUND
o-
-o*vo
lLTg>
o_
Ao-
IN
b
T>
"
-o
(a)
-vrt
FUNTIONAL
DIAGRAM
9V2
A
o-
t
N
nd Ql
I
n
Q2
1
Q3
si
3
I
AMA-
n
Q4
A
~
Q9
H
?-
V,
IN
u
Q5
n
oVF
Q10
a6
4
Q7
(b)
3
STRUCTURE
Q8
FIGURE 24
THE
FAIL SAFE
GATE
82
The
relationship
and
the
CMOS
the
use
of
in
gate
The
characteristics
input,
ary
a
low
+V2,
25.
Figure
are
positive
9.
Table
the
of
binary
of
+5
state
and
volts
#1
Element
#2
operates
with
defined
as
being
ground
both
requires
tinuous
and
identical
except
fail-safe
The
In
this
normal
into
dynamic
circuit
a
voltage
detection
The
the
so
fault
ground
level
is
illustrated
in the
waveforms
or
+VQ
states
or
fauj_t
V^
for
input
will
free
proper
be
operation.
positive
never
be
gate.
terminal, V.,-,,
il
level.
gate
independent
operate
as
ground
output
and
the
of
a
and
terminals,
must
be
gate
operation.
in Figure
always
con
#3 is incorporated
can
terminal, V_,
a
-Vq,
it
R between the
less
between known
element
that
or
than
always
a
the
at
state
provide
the
at
high
#3
of
output
modes
a
will
+V,
occur
fault
is
use
i.e.,
Element
By connecting its input to
resistor
at
a
failure
of
structure
detector.
levels,
to
in
level.
i.e.,
level.
second
logic;
reference
the
a
shown
positive
With
requires
identified
as
for
is
logic
24,
transfer
plots
logic;
modes
has
operation.
gate's
providing
the
fault
manner
the
failure
detection
enables
with
negative
F.S.G.
signals
volts
reference
voltage
gate
with
+15
negative
The
voltage
ground
signal.
the
when
and
as
and
output
logic
negative
which
positive
dynamic
gate
operates
defined
at
minimum
typical
a
logic
in Figure
F.S.G.
8.
Table
negative
maximum
Element
in
given
and
of
for the
symbols
26.
at:
When
+v/,
V-^
greater
than
This
By switching
-V/,
produces
a
83
TABLE
8
IDENTIFICATION OF THE
INPUT AND OUTFTT
TERMINALS FOR THE FAIL-SAFE LOGIC
GATE
CMOS
SHOWN
IN FIGURE
GATE
TERMINALS
24
FAIL-SAFE GATE
ELEMENT #1
TERMINALS
ELEMENT #2
ELEMENT
#3
r
VDL
+v2
GROUND
+Y0
VSS
GROUND
-v2
~Y0
VIN
+VIN
"VIN
VOUT
+Y0
"VOUT
GROUND
VF
84
TABLE
TRUTH TABLE OF
SECONDARY
INPUT
9
THE FAIL-SAFE
PRIMARY
FAIL-SAFE
INPUTS
OUTPUTS
A
B
+v2
+fIN
+^IN
+^0
+v2
+^IN
+fIN
+Y0
v2
GATE
DETECTOR
OUTPUT
vo
7F
-^--Yo
-v2
"?IN
"fIN
~Y-0
-v2
"fIN
"fIN
~Y0
+v2
+^IN
+^IN
+vo
+VQ
+^IN
+^IN
+Yo
<
0
-V
-V
-IN
IN
~Y-0
"-IN
"VIN
~Yo
+v2
+v
+
+v
-IN
+Yo
+v2
+fIN
+^IN
+Yo
-I2
-Vo
1_
"IN
0
'-12
-v2
-V
-V
~Yo
"?IN
-IlU
~Yo
VIN
v+Vq
7-+Vq
85
TABLE
SECONDARY
INPUT
v2
9
(cont'd)
PRIMARY
FAIL-SAFE
DETECTOR
INPUTS
OUTPUTS
OUTPUT
A
B
Yo
+v2
+^IN
+^IN
+Y6
+v2
+^IN
+^IN
+Y0
VF
*
~Y2
"-IN
"-IN
~Y-0
t
-v2
-^IN
-IlN
~Y0
+Y0
86
15-15-
>
>
LU
O
<
<
i
I
6
o
>
>
-5H
=3
3
Q_
Q_
1
1
=)
=5
o
o
LU
>
1
LU
>
<
1
o
CO
LU
z
o
POSITIVE
0
PRIMARY
PRIMARY
NEGATIVE
-'5
SYMBOL
+yIN
4V,N
=
=+5v
=
-V|N
-^IN
0v
=
5v
0v
+v2
^v"2
=
=
-y^
-v2
=
VOLTAGE, -v|N
-1'5
TABLE
0v
+5v
+y0
+15v
+v0'=--
+-5v
-v0=
-15v
+
-H5v
~Vo
Vo
==
==
-yQ=
=
-15v
-5V
Ov
-5v
Voltage Transfer Characteristics
Gate.
FIGURE 25
of a
Typical
Fail Safe
87
MAX
I
-
+V^
!
|
1
!-
1
:
;
MIN.
i
j
,
A
"l
1
D
u
i
i
!
I
!
!
:
!
i
1
i
J
1
'
;
i
i
;
'
:
i
i
*
'
-
-J
i
'"
A
I
""T
L
1
i
-V,
IN
'
!
i
!
B
1
1
1
fv'o
i
+Vq
VQ
;
i
'
'
'
!
i
i
i
!
+VQ
.:,:'.
^r
+v, N
A
1
|
J
-J
,
I
!
i
i
'
i
1
i
!
i
'^_i
1
JlO
'
1
':
Ml N
~n
MAX."
i
!
i
Vr
-V
vo
u__l
.J
I
I
-V
Yo
r
\
i
1
I
1
i
-
-Vo
!
!
i
1
!
I
,
i
1
i
4-\/'
1
+v0
0
1
-
n
1
!
!
;
vo
1
i
TIME
(a)
Normal
Gate-
Operation.
Input & Output Waveforms
of
FIGURE 26
the
Fail-Safe
Gate
88
MAX
!
1
1
.
I
fV
*-
MIN
1
TAUL
T
?
A
+V,
1
IN
1
B
1
i
I
'
"f
i
A
-
1
'in
;
i
/
1
1
1
B
i
i1
+Vn
vO
/
'O
!
1
1
!
!
i
i
,
1
-
+v'
vo
*-F-ALJLT
-
^
+y0
L__J
MIN.-
s
2
'
MAX.
-V
vo
VQ
-
V0
Xo
-
i
i
i
i
1
+\/'
TV0
0
^FAULT
-
MS
i
-
P
*\
|JU
i^
1^
-
"Vo
TIME
(b)
Gate
Operation
with
Indicated
FIGURE 26
Failures.
(continued)
89
value
gate
of
or
-Vq
or
its
at
internal
occur
then
-VQ
fault has
a
input/output
terminals.
to
but
the
gate,
are
elements,
(gate interconnections),
the
terminal V^.
fault
occurred
that
Failures
three
the
to
external
detectable
also
are
the
within
at
F
26b
Figure
failure
of
failure.
the
by
This
a
#1
the
of
portion
selection
terminal.
to
of
meet
shown
transfer
voltage
of
fail-safe
#3
gate
and
in Figure
26b
feedback
To
were
at
the
Vthen the
permanent,
different
be
would
operate,
component
require
will
is
and
-Y/
element.
detection levels
modes
terminal.
fault
zero
indicated
are
characteristics,
the
failure
internal
an
for
fault.
reference
to
ternary
show
waveforms
between
varies
to
the
at
terminal
input
A
faults
these
level
voltage
specific
these
simulated
In
the
the
at
terminal due
detect
gate's
input
If
V-- waveform,
F
each
in
normally
and
resistor,
to
(non-permanent)
intermittent
occurred
+Vn
ability
variation
function
have
the
and
The
output
this
that
modes
element
illustrates
the
waveforms
levels
of
of
-yC ,
U
Figure
26,
the
and
V~
for
-V~ ,
-vn
the
u
0
_
binary inputs;
idealized
for
operation
only
function
the
with
waveforms
occur
only
-VTTT
the
and
-V,
of
input
gate
ternary inputs,
show
when
the
that
the
the
for
(+VIlf,
input
secondary
a
logic
input, V2,
been
In normal
network
-Vj^,
state;
has
example
illustration.
purpose
the
because
and
+V-j-jx
is
at
would
-Y^)
or
-V^
+V2
or
Also,
can
-y_2,
90
respectively.
this
sequence
will
create
of
element
#1
VII.
similar
10
and
is
shown
has
11.
been
detect
all
faults
internal
prevent
vice
is
to
identified
#3
to
output
will
unless
a
are
an
masking
#2
is
fail-safe
multiple
gate
with
two
its
Figure
at
the
secondary input
signals
fail-safe
type
of
at
or
this
the
13,
set
change
the
of
short-circuit
this
all
of
a
function
unique
input
primary
9).
in Table
The
levels
voltage
Table
gate.
for
12
specific
element
modes
of
fault
conditions
element.
failure
,
terminals,
produced
failure
indicating
output
of
-Vn
By continuously
shown
fail-safe
the
of
inputs,
produces
sets
(as
gate
output
Analysis
in Table
open-circuit
to
occurs
gate
normal
maintain
always
detectable
the
for
V-^,
the
the
fail-safe
the
of
de
The
input, VTW,
primary
26.
should
faults.
secondary
#3
including
element
and
Table
element
gate
gate
The
independently
The
structure.
are
in Table
shown
to
24,
Chapter
of
for
truth table
the
of
they
chapters.
7
and
8
modes.
shown
6
Table
in
failure
identifies
#3 is
own
because
previous
Its
output,
variables
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27
of
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101
TABLE
12
EXAMPLES OF DETECTABLE FA.ILITRE
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103
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6
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CMOS
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self-checking
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the
in Table
ternary
of
signals,
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failure
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structure
single
cycle
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detecting
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gate.
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internal
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undetectable
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to
identified
conclude
fault
that
the
were
logic
states,
identical
Consequently the fail-safe
We
modes
is
the
1 34
CHAPTER IX
RESULTS
The
failures
of
digital
have
logic.
the
logic
and
composite
we
is
types
specific
set
to
effect
that
problems
has
shown
logic
have
either
failure
of
internal
the
normal
behavior
objectives
modes
or
identify
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the
all
toward
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failures
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for
unacceptable
this
that
believed
is
of
review
identify
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techniques
most
made
to
restriction
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fail-safe
of
thorough
a
failure
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a
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can
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significant
of
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to
because
menting
the
logic
identify
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aspect
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CMOS
of
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for
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logic
fail
forth
paper.
techniques,
for
internal
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logic.
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Chapter
have
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characteristics
gate,
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families,
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simplicity
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the
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acceptable
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nificant
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fail-safe
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gates
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relevant
safe
of
group
literature
logic
identified
circuits.
This
failure
has
paper
shown
successful
VI
are
that
by
method
a
sig
imple
of
pro-
105
fail-safe
viding
purpose
of
logic
technique
each
implementation into
short
(1)
shown:
degree
tion
marginal
fault
internal
the
at
dynamic
and
(5)
The
into
implement
track
of
all
a
modes
of
the
gate
the
gate
masking
detection
terminals
output
zero
or
that
the
and
,
multiple
process
have
The
V
to
by
be
the
logic
to
and
of
the
faults
for
necessity
implemented
into
for
means
be
compli
to
i.e.,
its
keep
would
provides
use
allows
all
independently
operate
technique
logic
isolating
logic levels
fault
resolves
in
would
However,
terminal
toward
the
provides
logic
network
state.
level,
a
implementa
input
second
logic network,
problems.
identify
within
signals
at
to
means
ground
design
restricts
instrumental
it
gate's
achievement
negative
and
positive
existing
positive
of
the
large
a
is
the
(2)
the
(3)
of
ternary
of
use
use
major
a
level,
operation.
compound
is
gate
it
gate
technology
present
has
gate
the
of
some
combinations
detection,
function
a
(4)
to
normal
and
input
primary
fault
all
detection,
cated
a
of
identified
three-terminal
threshold detection,
three -terminal
faults
sets
for
gate
the
of
has
gate
self-checking through the
of
the
analysis
certain
the
been presented, their
fail-safe
characteristics
to
use
the
has
the
Although
achieved.
threshold detection is
of
transfer
of
Only
sensitize
will
its
The
comings.
be
can
detecting
existing
but
problems
complicates
multiple
an
failure
fault
observable
.
The
fail-safe
gate
is
shown
to
be
an
effective
gate
106
for
fail-safe
fault
complete
complex
if
the
probability
is
gate
presented
of
techniques,
are
implemented to
is
somewhat
possible
occurrance
to
of
as
then
possible
networks.
a
means
certain
and
may
structure
types
of
if
the
implementing
the
fail-safe
prove
its
oy
its
However,
of
different
produce
limited
reduce
insignificant.
considered
logic
it
is
It
considered
is
figurations
complex
Although
detection,
structure.
failures
safe
logic.
more
gate
fail
con
effective
in
107
CHAPTER X
CONCLUSIONS
the
Although
of
logic
a
and/or
gate
the
component
deterioration
to
detect
so
that
safe
mode
is
determined
internal
states,
a
of
the
The
CMOS
techniques
tolerance
the
or
gates
gate
gate
and
inability
to
the
as
its
basic
some
exhibited
of
the
predict
It
is
important
gate
or
a
gates
by
a
into
network
circuit
the
detection
of
combination
a
logic
ternary
are
self-checking
fail-safe
logic
which
element.
success
of
The
applied.
its
gate's
occur,
fault location is
degree
are
they
as
complementation,
designing
been
gradual
soon
Thus,
of
how
matter
to
fail-safe
described herein
limitations
the
continuous
achieves
variations
as
components
due
By designing
similar
and
no
capability
redundancy has
Thus,
rendering
detection,
method
CMOS
forever
self-check.
gate
two-rail logic
utilizes
the
of
much
damage.
Implemented
component
a
last
can
reliable
circuit,
how
initiated.
block
by
into
and
be
easily
combined
tics,
by using
or
components
action
can
are
physical
faulty
proper
process
the
or
building
a
improved
components
no
provided,
as
be
can
fault-tolerance
and
providing redundancy in the
reliable
a
reliability
transfer
maximum
known logic
when
wide
characteris
operating
state
for
levels,
some
108
failure
common
modes
Any digital design
element
networks
and
as
usefulness.
terminal
prove
to
realization
ing
have
all
only
The
logic
be
Uceful
of
restricted
type
and
of
independent
for
techniques
failure
gate
Dynamic
of:
modes
storage
would
fault
Its
three-
detection,
logic.
importance
major
logic
restrict
self-checking,
the
the
a
combinational
fail-safe
and
are
capabilities.
without
in
gate
logic
techniques
these
achieved.
be
fail-safe
concepts
gates,
internal
been
the
using
the
would
fail-s.fe
its
limit
goals
The
of
detect
that
109
LIST OF REFERENCES
1.
December,
1964.
Friedman,
A.
Digital
5.
Su,
:
Prentice-Hall,
Fault
Detection
in
Inc.,
Englewood
Cliffs,
Bridging and Stuck-at-Faults,
Computers, July, 1974.
Stephen,
Y.
:
,
Combinational
Trans
A New Approach to the Fault Location
Circuits, IEEE Transactions on Computers,
Applications
Staff,:
Motorola,
Motorola,
Inc., 1974.
Mine,
C,
H.
Inc.,
Motorola
Tadao,
Takaoka,
Tadao, C., Ibaraki, Toskikide,
Machines, IEEE Transactions
Transactions
IEEE
,
:
on
Safe
N-Fail
Takaoka,
Systems,
Computers,
Checked
ume
2,
1971.
N-Fail
on
Safe
Computers,
1972.
November,
Carter,
McMOS
Logical
May,
:
Sequential
9.
IEEE
1972.
Handbook,
8.
,
C.,:
on
January,
7.
M.
Fault Masking in Combinational Logic
Dias, Francisco,:
Transactions
on Computers,
IEEE
Circuits,
May, 1975.
of
6.
R.
Computers,
*
actions
4.
Menon,
,
circuits,
K.
Mei,
D.
Circuits
on
1971.
N.J.,
3.
integrated
Suran, J. j.,:
Transactions
IEEE
Systems,
A.,
Integrated
and
2.
R.
Marolf,
Design of Dynamically
C, Schneider, P. R. , :
Computers, proceedings of IFIP Conference, Vol
NOEI-HOLLAND, 1968.
Amsterdam, The Netherlands:
W.
10.
Fault-Tolerant Computers
Freeman, H. A., Metze, G.,:
Using Dotted Logic Redundancy Techniques, IEEE Transac
tions on Computers, August, 1972.
11.
Mine,
Method
,
Koga
for
a
,
Y.
,
Basic
:
Fail-Safe
properties
Logical
Computers,
June,
1967.
Blood, W. R.,
inc., 1971.
Jr.,:
MECL
on
12.
H.
a
Construction
IEEE
Transactions
and
Systems,
System Design
Handbook,
Motorola,
113
LIST
13.
A.,:
John
DeFalco,
Versatile
Bulletin
Design
OF REFERENCES
The
(cont'd)
Integrated
Component,
Texas
Schmitt
Trigger;
Instrument
A
Design
Report,
CA-152.
14.
Error DeSellers, F- F-, Hsiag, M. , Bearnson, L. .,:
tectiog Logic for Digital Computers, McGraw-Hill, New
York, 1968.
15.
Su,
Stephen Y.
Computer
16.
Kohavi;
Unger,
:
Kohavi,:
Transactions
17.
,
Design,
S.
H.
on
,
:
Logic
Design
January,
and
Combinational
Computers,
Hazards
and
Logic
June,
Ne.tworks,
IEEE
1972.
Delays
Switching Circuits, IEEE
Theory, Volume CT-6, March, 1959.
quential.
its Recent Development,
1 974.
in Asynchronous
Transactions
on
Se
Circuit
111
APPENDIX A
EVALUATING THE EFFECTS OF FAILURE MODES BY
CALCULATING THE STABILITY AND
SENSITIVITY OF A CIRCUIT
STABILITY
important
An
instability.
The
I
significantly
CBO
the
changes
,
collector
to
erature
increase
the
device
burns
biased
in
or
ln,
0
OBO
this
saturation
cut-off
is
for
of
result
junction
I
a
this
increase
It
.
become
is
cumulative
exceeded
transistor
in
temp-
this
of
further
itself
find
to
are
example,
result
may
to
events
of
possible
a
a
consequently,
region
as
region
As
current,
For
collector
and
transistor
the
of
It
out.
the
and
saturation
lni...
increase
will
succession
ratings
the
thermal
is
temperature.
with
causes
,
temperature
for
the
that
I
reverse
increasing
with
InT3~,
junction
possible
so
rise
in
transistor's
current,
failure
transistor
causerof
the
operating
and
the
which
is
active
point
instability.
Analysis
the
I
rate
.will
of
of
simple
a
in
change
the
define
illustrate
of
circuit.
a
how
In
collector
failure
the
active
by
circuit
current
with
the
circuit.
modes
can
affect
region,
Figure
examining
respect
of
stability
CBO
will
transistor
the
A-1,
The
to
stability
operation
the
relation-
112
V
R2-Vcc
=
R1+-R2
R2-R1
R,=
b
Rl
R2+R1
Ql
Rk
o-i
V
Vcc
1>
Vce
Ov
r v
SR2
<
in
V
-=:
(b)
Transistor Circuit,
(a) by
in
the
use
of
(b)
Simplification
Thevenin's
FIGURE
Base Circuit
Al
0
CI
J
_DJ
vcc-
Veb
+
=-V,
cbo
'bi.
c
! 'b
i_
of
-i
Theorem.
Icb
'b
|'b+
Rc
(a)
(a)
lc'
Rc
RE-(K
'e| RE
bb
(b)
(a)
PNP Transistor Circuit,
the Leakage
(b)
Equivalent Circuit
Current.
FIGURE
A2
of
113
ship
between I
=
JC
Definition
of
S
is
I
and
)
<1+?
*
}IrG-
Eq.
A-1
with
respect
to
r
i_,
C
consider
constant
di0
+
(A-3)
e
=
1
=
Differentiating
dipB
dlc
(dVdic)
9
-
Voltage
V
(A-2)
AICBO
i
Kirchhoff's
^"1)
ZB
AIpS-
=
s
s
+
ICBO
^
ICBO
Differentiating
by:
(s):
stability
=
given
Lav/
the
around
'
IB
Eq.
-
RB
A-4
+
VBE
and
R-p
E
RE
+
base
'
RE
(IB
letting V-n-c
circuit:
+
be
lc)
(A-4)
independent
of
(A-5)
+
RB
I
114
Substitute
Eq.
into
A-5
Eq.
A-1
it
,
1
S
beta
the
the
zation.
the
cause
+$
va
lue
in
of
its
value
to
circuit
the
R_,
if
transistor's
in
exhibit
a
the
which
R
or
Also,
stabili-
value
of
changes
short-circuit)
increased
an
the
be
will
design tolerance
(or becomes
decreases.
circuit
better
mode
RB
+
the
the
of
failure
a
VRE
'
that
seen
stability
beyond
by decreasing
be
can
Therefore,
increases
R
?
+
the
increased,
smaller
that:
(A-6)
it
A-6,
shown
=
1
From Eq.
be
can
will
instability.
SENSITIVITY
Internal
or
short-circuit
parameters
a
component
as
significant
output
number
variations
sensitivity to
their
effect
performance
I
,
illustrate
to
various
a
circuit
static
and
digital
not
The
variation
transient
will
creating
failure
modes.
of
a
the
effect
of
PUP transistor
the
sensitivity
component
failure
serve
component
circuit,
of
the
modes.
to
open
component
failures.
analyzed
circuit,
in
to
for
accounts
performance
changes
on
of
of
of
of
only.
confined
are
component
Analysis
will
conditions
function
a
failures
as
to
The
its
illustrate
failures
Figure
collector
on
the
A-2,
current,
115
From
in Figure
circuit
=
ZC
^i
+
^BO
JB
+
TCBO
=
TBi
%'
IG=
Assuming that
about
the
is
VEB
+
IB
=
ZB
?
+
(A~7)
ZCBO
(A"S)
(^+ 1)
ICB0
and
(A-9)
assumming the
voltages
loop:
*
=
'
^i
negligible
emitter-base
VBB
A-2 :
+
RB
'
ZE
(A-10)
RE
AND
IE
-
=
^i
Substitute
Eq.
IE
Substitute
Eq.
IBi
ZB
(
+
?
A-13
+
=
Ici
+
(^
IBi
0
(A-11)
(A"12>
^BO
into
A-12
=
+
1)
into
Eq.
A-1
'
(IB
Eq.
(A-13)
ICB0)
+
A-10:
'
'
V^
=
IB
RB
+
(
^
+
1)
(IB
+
ICB0)
RE
(A-14)
116
Solve
Eq.
for
A-14
I
-
I
B
'
"
VBB
B
RB
Substitute
Eq.
into
A-15
Ic
?
Eq.
V^
n
=
RE (?
^BO
+
RE
'
RB
(
^
"
VBE
1
+
(A_15)
)
A-9
( 0
^^
R
InT5TT
^
-
'-^
1>
+
+
RE
.
( ^>
1
+
1
+
)
\ ICBQ
CB0
)
( 9
K
(A-16)
Result
*
VBB
^BO
=
Ic
^+1)-(RE
+
($
+
RB)
+
+
RB
(
RE
p
+
1)
RB
+
RE
1)
(A-17)
Definition
of
(Sy)
sensitivity
The
sensitivity of a quantity
to a parameter (Y) is
respect
dx
y
Sf
to
R
,
Wx5
definition
Using the
quantity
=
I
RE,
in Eq.
and
Q>
=
for
A-17,
are
as
-
.
with
by:
(A-18)
-
sensitivity,
the
(X)
given
Eq.
sensitivity
follows:
A-13,
of
IQ
and
with
the
respect
+
1)
117
R.
B
s
1
R
RE
B
(A-19)
-
(0+1)
RB
2
RE
ZC
S
+
'
Rp
E
'
( ?
+
1
)
(A-20)
"
RE
+
RE
RB
RB
+
RE
+
1
($
1)
+
'
?
QXC
?
+
Rr
LB
RE
(A-21)
( 6
R*
XLE
)
r
It
values
be
can
R
of:
then
(as
will
result
From
Eq.
in
A-19
S.
20ol,
=
shown
Eq.
^
a
a
change
-Mfo
-20^
that
A-19
20,
=
below)
R
Ikjfr,
=
in the
in
current
R
value
I
.
2
20kr
C
=
A-13
dl
and
change
the
the
for
:
20
21kr
RB
From
from Eq.
seen
+
1
0.862
:
0
s
dRB
ZC
R.
R.
B
B
dl,
=
c
Aln
=
(0.862)
(+0.20)
=
17.
nominal
=
of
2'kiL,
R_
118
Various
changes
components
of
the
effect
have
in
tolerances
been tabulated
sensitivity
of
the
failure
of
ic#
modes
on
the
in Table
These
the
of
results
circuit's
A-1
as
a
function
illustrate
performance
of
the
the
circuit.
119
TABLE
SENSITIVITY VS
FOR
CHANGE
IN
COMPONENT
THE
A-1
COMPONENT VARIATIONS
CIRCUIT
IN FIGURE
XC
S
AR^
B
S
IC
A-2
1C
AR-p
*
VALUE
RB
20%
17.2%
19-5%
9.8$
40/o
34.5^
39-1$
19.5$
60$
51.7%
58.6$
+29.3$
EE
120
APPENDIX B
ANALYSIS OF A RTL
In
to
reference
the
V0
=
h
-
V
=
in Figure
circuit
VCC
5
"
CIRCUIT
'
TB
2:
'
(B"1)
RL
WHERE:
(sat)
"
v
::
THEREFORE:
3
RESULTS
YC
'
RT
~~^~
'
(V0
"
VBE(SAT)>
^
:
Y
=
'
RB
VCC
+
RB
+
3
'
RL
'0
In
reference
of
to
Vn
u
R
to
3
Appendix A and
r,
and
>
is
'
VBE(SAT)
(B_4)
RL
Eq.
the
B-4,
sensitivity
:
Jj
RB
OV0
=
R
1
"
R
B
B
3
OT0
=
E
L
1
+
'
5R
B
+
=
3)
(B-5)
(M0UT
=
')
(B"6)
EI
'
R
(MOUT
L
3E
L
121
C
APPENDIX
ANALYSIS
Analysis
based
of
on
the
the
of
TTL
changes
OF A TTL NAND GATE
the
in Figure
gate
in
internal
gate's
internal
4.
failure
The
current
modes
piecewise
verses
is
analysis
parameter
changes
*
the
illustrate
will
failure
potential
modes
of
multiple
r
transistor
for
C-1
the
high-level
to
stages
low-level
output
figure
gate's
output
state,
changes
component
From
in the
as
we
structure.
state
Figure
and
determine
can
Using
the
C-2
Figure
for
the
sensitivity
follows:
C-1 :
z
z
_
VCC
"
VBE ^1>
-VBE <Q2> -YBE ^)
1
^
VCC
'
VCE >2>
VBE (Q5>
~
2
^_^
(c_2)
R2
Let
VBE (Q5)
The
current
=
VBE (Q2)
gain
A.
of
*2
Q2
=
VBE
(Q1
;
is:
VCC
"
VCE ^
1
h
)
R2
"
VBE (Q5>
R1
vcc-vbe(q1^vbs^
(0-3)
122
hi
J*
R2
> RL
Q3
Q4
VOL
Q5
oVcc
R3
<
R4
1
TTL NAND
Gate
with
the
FIGURE
CI
Output in
>
I
a
Low State
K,
Q3
Q4
j
0+
^Q5 V0H
R4
R3
<
TTL NAND Gate
with
FIGURE
the Output in
C2
a
High State.
123
Simplifying;
_
Ai
Ri
(Ycc
'
'
R2
From
Eq.
C-3
and
W
(C-3)
2VBE>
SA1
'
-1
UE
R,
Figure
(VCC
-
-
Appendix A:
sA1
From
vce ^2)
"
C-2 :
_
VCC
VBE <Q1>
"
(C-4)
R<
VCC
R2
+
VCC
The
current
gain
Ai
=
VBE W)
"
Ri
+
of
Q3
-
(C-5)
(+1)
R4
VCE ^
V($
+
(C-6)
R4)
is:
@ 'LVCC-VCE (Q5ll
"VCC-VBE
(Q3
'
5j
"[R2
+
V(
|~(p+1)-R4
? +1L
=T
+
RL
(C-1)
124
From Eq.
C-7
and
Appendix
A
R4
R4
R2
s
(
+
R4
A:
1
+
(
)
^
*4
1
+
$
)
R,
sAi=-
R2
S1
R2
+
R4
(
+
1
)
RL
+
R4
'
($+1)
(
+1)
125
APPENDIX D
ANALYSIS
Analysis
based
on
the
sensitivity
Current
I.
the
of
ECL
to
OF A ECL GATE
gate's
in Figure
gate
component
failure
internal
5.
changes
We
can
modes
determine
is
the
follows:
as
is
=
1^1
VEE
[VBB
L_p^
"
_^
+
VBE
1J_
x_(Q5H
(]>1)
B,
l2
When
all
gate
transistors
The
voltage
drop
at
inputs
through
Q^
the
collector
Q4
of
'
=
\
The
OR
output
h
'
R4
+
\
logic zero, thus
in cutoff.
will be
equal
R4
Q5
is:
(D-2)
is
T0E
=
\
+
YBE <8>
(D"3)
126
Therefore
:
V-
V0R
From Eq.
~
R4
D-4
Appendix
V,
OR
s
Ry
l1
=
-1
R,
V
EE
=
YIN
R
When
are
voltage
OR
is:
h
The
(D-4)
A:
V,
Current
"+IBl'R4+VBE(Q8)
Rr
and
S
VBE (Q5)
+
VBB
EE
or
one
at
drop
at
the
VBE (Q5)]
(D-5)
2
more
logic
a
"
of
one
the gate
level.
of
collector
Q5
inputs
is
r^J
'
=
And
the
NOR
\
h
output
is
VN0R
V
~
R3
+
\
R3
(D-6)
:
+
VBE (Q7)
(D-7)
127
Therefore
V.
VN0R
[VIN
EE
R3
VBE(Q5)
R,
'
R3
^JB3
+
YBE(Q7)
(D-8)
From Eq.
D-8
Appendix
and
V
S
V
NOR
NOR
=
+2
R,
Let
VBE
of
Taking loop
voltage,
A:
Q1
VBB,
,,
through Q8
equations
s
of
R
be
the
2
equal,
bias
VR1
supply
V^-VT
L5 -6-^[YEE-YBE(Q6)Z2^]
BB
?'
W
VR2
=
Vp
circuit,
the
threshold
is:
R^'R^-B-
V
-
+
W
^^m21^
R5=R6+R7iR6
Vra-VE6'VBE+VR7-V:EE
R5-R7+R7-R6+R5'R6
(D-9)
128
APPENDIX E
ANALYSIS
OF A RTL GATE USING
THE
NEWTON-RAPHSON METHOD
Diode
equation:
_
1
Where
Using the
-
I
200K
T2
=
300K
T^
=
400K
I
@
300 K
Q
k
2
=
1
=
1
=
to
plot
to
curve
-QVg/nKT
T
E-1
.
silicon
volt
room
at
temperature
(300K)
10"19
X
.602
.38
X
'
RB
10
of
equations
YIN
(E-1)
1 OnANOAMPERES
=
for
1.1
-
proportional
values
-
Yn
G
Taking loop
is
T1
=
1
3/2
following
n
QVBE/nKT
1,
=
ZB
-23
the
+
circuit
VBE
in Figure
6
(E-2)
129
'
10 oz--= 1
i
r
I
u
o'
I
l/>
^rW
\
U^x
o
1_
D
o
o'
"N
i/>
\
o
c
o
o
cq
"*
o"
h
(Wt
'Ur^
>
l_1
"O
o
v
,
o
o
>
c
o*
i
^j
\
!
z
1
!
\ 1
1
C
o
1
o
(J
o
CO
|
!
CO
l
c
<3.
C
cD
rf
Ln
CN
sdujoiiijuj
ui
J
J.N3cliinD
CURVE
E
o
c
c
130
Using the
Ebers-Moll
transistor
,U^V<
I,
r,-UV,*-]
-0
_
model:
I -oi^
<Kn^
n^J
XE
iS0-UVflEMil
^[^-Q
=
Kn^r
iB=
^L
l-^n^T
(E-3)
(E-4)
(E-5)
-LLc+^J
Therefore
I
B
(E-6)
And
input
the
=
VIN
The
=
0
V
"
o
is
YBE+H\Jco{
voltage
output
V,
voltage
Ynn
"CC
vcc
-
^nlEolt
'/
(E-7)
is:
RTIC
iLLxC
"
^)
=
VBE
"BE,
-
Vc
=
V
(E-S)
rl[
^i\<<Z
131
The
following
=
IQ0
values
0.1298 X
3,14 X
are
IEQ
'
=
Vn
n,
-
0.0655 X 10
2
=
(200K);
10 X
'*
' ^
(200K); 5c
=
450
volts
--
X
=
0.50
(300K)
(300K)
RT
=
640
9
10"y
-i
(400K)
volts
ohms
10"9
10""y
10~6
*
p
curve
3,
4,
(300K);
r\~
fonr\oTr\.
(silicon)
=3.6
Vcc
for
(400K);
^1
0.99
.026
as
10~6
1.5858 X
^n
*
)~9
10
\~
=
specified
ohms
(300K)
and
5:
132
APPENDIX F
ANALYSIS OF A TTL SCHMITT TRIGGER GATE
The
trigger
Schmitt
its
following
circuit
tion
the
of
transistor
the
are
Q9
make
Q5
and
up
Q9
obtain
from
a
Q1
operates
as
a
Schmitt
gate
together
as
at
of
the
and
low
positive-going
low
F-2
voltage
opera
multiple-emitter
Q2
is
is
sat
F-2a
is
used
needed
voltage
inputs
Q3
and
Figure
)
Q3
through
When all
off
(V
and
transistors
The
diodes.
Summing
state.
The
transistors Q4
and
of
integrated
The
Transistors
Q2
level,
in Figure
dependence
F-1.
type.
TTL
emitter-base
a
circuit
a
the
The
diode.
trigger
integrated
parameters.
follows:
drops
to
switch
around
loop;
=
V
VE
The
circuit
as
high to
input
illustrate
will
on
type
TTL
a
illustrated in Figure
function
the
of
is
NAND
a
The
urated.
is
circuit
actual
tied
are
the
circuit
threshold levels
Schmitt
to
analysis
=
-VBE<Q1>
+W2>
+
(F-,)
VB
'
EE
negative-going
V0C/(EBQ_
threshold
VT_
+
(F-2)
EB)
can
be
determined
by
133
3
Q.
>u
o
oo
ro
O
c
n_rz
-vw
-^HT
vw-
3
u
u
CY.
o
\ z
LU
4
in
tJ
io
o
o
CM
aAAA-
-\AAA
^Lr
KO
Qi
CO
10
c^
4
CO
WNA-
I
o
LU
S3
VNAACN
^
Oi
CN
V\AA-
CM
<
Cc.
C
_
^
"HS-
a.
Z
o
r
Integrated
Schmitt Trigger Circuit
with
Positive & Negative
Thresholds.
Vcc-
Rl
R2
4K
2K
0.4v
EQ
750
lJ
Q2
c^^C
TT
(a).VT
with
Ve_
>
RE
J,
1
460
Q2 in Cutoff & Q3 in Saturation.
v,,
2. 1 5
4
Rl
4K
_
77V.J
.
^
2<
R3
1.2 K
V,
C2
Q3
Q2
VI
460
1
(b).VT_
with
Q2
in Saturation
FIGURE
F2
& Q3 in Cutoff.
135
assuming
to
the
Schmitt
on
and
the
Q3
turns
trigger
circuit
ON
=
collector
Figure
in the
is
begins
F-2b
active
to
When
apply.
state
turn
and
its
is:
VCC
current
<2
t
of
Q3
input
the
As
saturated.
transistor
conditions
voltage
VC2
and
drops
transistor Q2
on
collector
The
is
transistor Q2
"
'
X2
of
02
(V1
(E"3)
R2
is
-YBE
^)
(F-4)
=
RE
X9
is
gain
Substituting Eq.
F-4
WQ2>
V,
1
The
into
Eq.
+
[VCC
+
R2/R
"
the
of
F-3
common-base
transistor
Q2
equation
V
=
for V
-VBE(Q1)
assumed
:
WQ3)]
(F-5)
=
1
current
and
E
becomes:
+
VBE^Q2)
"
WQ5)
+
V
(F-6)
V
=
-VBE(Q1)
+
V1
=
1
136
Replacing v1
with
F-5
:
vBE(Q2)
+
-vBE(Q1)
V T-
1
+
+
[ycc
-
vBE(Q3"3
(E-7)
R.
E
Letting VBE(Q1)
V,T-
=
_
VBE(Q2):
vcc
1
-
vbe^)
R2
RE
(F-8)
137
APPENDIX G
LOGIC
For
ible
network
a
are
the
the
only
and
test,
built
circuits
points
i.e.,
FAULT
DETECTION
in
input
and
means
a
applying
integrated
set
input
is
it
analyzing
of
the
access
only
terminals
output
of
form
by
variables
logic
the
of
performing
ob-
and
r
serving
the
network
to
response
if
the
output
find
detection.
and
is
the
The
?
on
the
of
tests
to
the
of
input
it
same
number
faults
locate
of
which
which
be
applied
logic
to
the
to
and
gates
for
is
fault
of
A
is
X
if
it
The
another
the
is
independent
major
failure
given
circuit
only
variables
Also,
not.
the
a
the
and
network.
A but
is
logic
basis
input
for
that
X if
observe
logic
by
it
of
set
the
of
(S-@-0),
failure
number
proportional
of
the
number
available.
detection
(1)
a
response
sensitized
must
terminals
objectives:
of
detection is
network
which
Fault
of
be
may
test
or
fault
in
difficulty
)
check
a
the
be
will
a
that
such
correctly is
application
of
A
given
A,X
pair
to
network
operating
observation
called
(g_@_1
logic
is
circuit
Therefore,
input/output
an
the
of
response.
To
detect
might
element
attempts
or
gate
achieve
least
at
occur
to
in
a
has
following
specified
a
logic
the
the
network,
fault
percentage
(2)
causing
to
the
138
(3)
error,
to
detect
to
retry
to
classify the
the
There
used
for
within
fault
one
tions).
to
are
not
Fault
for
are
detected.
The
is
as
two
easily
they
occur.
should
sequences
operates
as
logic
To
output
logic.
correct
due
Errors
outputs
while
to
to
(3)
and
be
should
other
far
designed
through the
detection
as
soon
being
can
circuitry
It
by failing
to
indicate
is
by
periodically
detection
Another
intended.
of
one.
to
approaches
several
circuit
method
If
one
is
fail
of
a
faults
fault
fault
when
detection
running
test
ensure
that
to
to
fails
fail
can
or
are
be
the
after
possible
that
stop the
should
checked.
so
circuit
indication
instead
be
should
an
the
check
detected,
detection
logic
method
through
(1)
By giving
not,
(4)
falls
usually
ways:
There
One
circuitry.
as
Fault
the
as
different
it
the
circuit
observed.
be
circuits
they
the
and
for.
checked
very
of
in the
incorrect
some
detection
purpose
correct
not
may
propagate
when
on
fault
or
circuit
circuits
checking
deviation from the
any
single
fault,
the
(except possibly during transi
not
fault
in
check
of
allow
cause.
categories:
do
operation
just
a
check
partially
fore
times
faults may
multiple
faults
Their
following
all
to
(2)
due
faults
at
types
of
detection.
possible
Any deviation from the
detected,
output
to
as
number
the
of
output
every
faults
a
to
enough
interrupted by the
operation
are
fast
errors
use
the
two
other
it
checkers
will
139
still
This
give
an
method
output
the
when
that
assumes
logic
both
being
do
checkers
the
logic
does.
the
fault
detection circuitry to detect
A
circuit
A practical
that
detects
therefore
will
LOGIC
FAILURE
catch
design
many
fail
not
is
guideline
faults
single
fails.
checked
all
soon
to
single
after
before
design
faults.
they
occur
faults.
multiple
PROBABILITY
Portions
of
check
any
circuit
which
tested
are
oy
t
some
checkout
sources
will
a
have
test
is
of
sequence
faults.
undetected
a
built-in test
is
sequence
operating
to
then
failure
undetected
as
The
sequence.
the
if
periodically,
considered
the
Sometimes
determine
properly.
being
be
should
calculation
that
check
in the
possible
check
One
function
the
check
circuit
the
of
for
is
can
be
of
such
circuitry
tested
probability
checker
circuitry
of
a
determined
follows:
probability
period
of
time
of
no
undetected
from 0
to
is
T
failures
occurring!
in
a
:
oO
L.
x=0
PX
P
X
CHK
Where
check
it
ft)
^ }
PrTTF
is
circuit
contains
a
the
probability
gives
an
that
indication
fault.
P
(t) is the probability
the checker's logic
In
failures
in the period between 0 and I.
Where
a
that
of
I"
occurring
140
A
common
form
of
(t)
p
X
\X (t)
=
is:
(G-2)
-(^^-
X|
V/,
means
-
gate
the
Therefore,
probability
f (Pchk'XT)^
Ai
vi
XI
x-o
The
time
mean
to
an
of
no
time
to
fail
for
undetected
failures
is:
f-xr_
-XT(i-Pchk)
C
C_C-
failure
undetected
logic
a
.
(G-3)
is:
1
M.T.U.F.
*
Eq.
G-4
is
tested.
the
until
the
will
test
failure
an
test
the
of
of
the
with
W
~
how
period.
average
operating
(1
occurs
undetected
period
smaller
be
a
next
then
tests,
next
Independent
If
(G-4)
=
often
the
If
is
amount
an
check
T
failure
gate
the
is
v/ill
undetected
will
period
found
be
The
time
circuit
circuit
the
run.
of
check
check
operate
between
when
smaller
the
is
T
the
is,
circuit
failure.
TWO -RAIL LOGIC
A technique
for
checking
is
to
use
a
variation
on
141
duplication;
logic
that
technique.
is,
to
For
this
two
lines
the
1
state
of
the
lines
being
at
logic
are
the
Likewise,
first
at
line
logic
1
to
used
0
type
is
variable
1
the
of
logic
at
0
fault
by
represented
line
other
is
variable
the
and
I.e.,
one
being
the
of
line
the
by
being
"bit"
one
0.
logic
at
represented
second
Using two lines to carry
.
detection logic
every variable;
the
and
"Two-Rail"
so-called
of
represent
state
being
the
use
infor-
of
*
mation
11.
will
is
It
represent
00
and
the
With
0
states
are
error
an
detected
by
1
states
the
the
in
All
faults
caused
by
a
and
A
not
be
in
error
will
LOGIC
MULTIPLE
The
the
as
s-@-0
circuit
cut
such
is
that
failures
and
complement
in
due
to
always
will
X
gate
logic
any
x.
and
detected
are
being
open
also
fault
is
present
in
the
detection.
in
a
given
being
or
approached
circuit
since
A
is
or
open
or
that
at
the
the
most
covers
short,
a
at
from
represented
assumption
problem
network
be
can
short,
assumes
One
is
network
This
diode
a
It
faults
a
conditions.
short.
for
faults
multiple
or
multiple
failure
A
and
the
of
of
simultaneously.
open
performed
A
variable
output
single
failures
resistor
a
wire,
being
of
S-@-1
and
state.
FAULTS
subject
viewpoint
fault
true
input
10
and
the
third
or
and
while
the
the
comparing
respectively,
10,
01
states
as
utilized
of
binary
01,
00,
signals;
the
select
and
coexistance
function,
be
the
different
to
possible
to
11
four
yield
a
semiconductor
more
time
a
associated
than
one
test
with
potentially
large
142
number
2
are
of
faults
of
M
possible
-1
isolated
it.
In
does
from the
a
network
faults.
multiple
faults
multiple
are
in
This
include
not
input
or
"M"
with
potential
the
of
pins
number
failures
internal
output
there
lines,
that
logic
gates.
technique
One
faults
single
which
the
When
input
detection
be
application
S-@-1
being
line
on
input
line
c
being
network
of
the
X.
output
ABODE, ABCDE,
network.
presence
under
example
and
the
of
a
set
BCD
Thus,
of
,
line
of
test
of
the
masking,
In
G-2.
is
being
not
all
S-@-0
the
line
a
=
single
=
masks
11.
=
the
a
fault
at
ABCD,
faults
detected
AB
of
AB
network
S
of
fault
detectable
is
this
set
test
line
of
consider
this
variables,
detect
no
,
then
However,
and
01
=
can
application
S-@-1
fault
of
different
The
presence
will
AB.
a
AB
effect
masking
apply
input
b
presence
a
S-@-1
being
the
As
.
S-@-1
both S-@-1,
some
problem
G-1
states,
being
a
a
faults.
Figure
logic
to
being
so
are
to AB.
in Figure
shown
The
we
line
of
line
if
doing
of
line
of
detect
addition
S-@-1
another
consisting
this
in
the
at
and
a_
not
problem
a
fault
the
As
logic
not
are
handle
can
among
circuit
corresponds
the
under
variables
detects
will
This
a
is
masking
AB
of
the
line
If
accomplished.
In
it
detect
to
method
a
that
phenomenon
fault
single
so
faults.
masking
variables
generate
it
extend
consider
the
of
been to
multiple
the
illustration,
an
c
of
is
arises
then
and
types
specified
has
at
ABC,
in
X
11
143
TRUTH
A
^1
o
B
n
L_J
C
T--
Logic
Gates
with
X
o
o
i
o
-
i
-
-
o
-
0
i
Faul ts.
G I
n>
E>
Dl
B
Mul tiple
FIGURE
Bo-
A
X
b
TABLE
d>
d>
Fr
G
H
\r
>
Logic
Network
with
FIGURE
Multiple
G2
Faults.
-
x
144
the
by
not
a
input
detect the
being
S-@-1
to
made
fault
input
variables
input
The
two
Y.
put
for
,
ABC
output
at
output
X
and
S-@-0,
,
(line
a
and
only
Therefore,
any
single
faults
faults
for
also
input
=
C
=
will
line
of
be
can
not
1
Under
.
detectable
included
on
when
the
in the
of
is
not
line
a
S-@-1
of
the
input
in Figure
variables
listed
by
input
G-4
output
and
in Table
A
these
since
input
that
will
the
two
they
detects
a
fault
faults
are
of
multiple
multiple
outputs.
networks,
The
detect
six
any
sets
single
both
ABC
all
all
multilevel
A.
line
variables
detect
with
Table
if
fault
at
only
Hence,
at
The
ABC
at
occurs,
out
variables
detectable
variables
networks
is
However,
the
necessarily
single
lustrated
X
fault
S-@-0
being
indistinguishable
output
not
S-@-1
shown
at
ABC
of
as
make
detectable
input
is
S-@-0
can
The
example.
setting the
being
of
set
may
indistinguishable
distinguishable.
b
fault
undetectable
variables
multilevel
true
fault
fault
a
is
not
by setting
Y
become
c)
an
being
line
detectable
is
is
following
by
X
are
of
consisting
when
S-@-0
which
consisting
line
the
by
being
the
of
the
of
6
gate
being
output
of
consisting
effect
faults
b
fault
at
of
the
line
of
detectable
and
presence
input
this
However,
tests.
G-3
The
b
ABC,
are
distinguishable
consisting
the
line
occurrence
in Figure
the
through
propagate
conditions
of
in
because
these
set
ABODE.
variables
This
as
il
of
input
fault
145
Ao-
B
o-
o
o
Ao-
o
B-
C-
Logic
for
Network
Multiple
ILLustrating
Fault
-o
x
-o
Y
Masking
Outputs.
FIGURE
G3
A
B
o-
>
Co-
Do-
E
o-
^_>
o
X
>
A
FIGURE G4 Logic
for
-o
B
C
i
i
i
o
o
i
E
F
o
i
o
o
o
I
D
o
I
i
I
I
o
i
o
o
I
o
o
i
o
I
I
o
I
o
I
o
I
I
I
Network
Single
showing
Outputs.
Fault
Masking
146
but
of
they
the
do
e
are
line
logic
because
to
the
a
the
faults
that
consist
faults
f
are
the
output
technique
to
network
of
and
multiple
S-@-0
and
line
b
and
S-<>-1
Consequently,
a
four
following
When
the
detect
not
detect
inability
of
the
of
all
to
monitoring
logic
faults
propagate
network.
many
the
is
output
not
faults
of
adequate
through
147
APPENDIX H
LOGIC
STATIC
HAZARDS
HAZARDS
Practical
theoretical
Signals
electronic
the
representing
the
in
largely
circuits
same
delay.
of
presence
from
differ
circuits
switching
may
temporarily
representing
complements
variable
r
take
opposite
take
temporarily
may
assume
values
contain
faults
which
fault
a
by delay,
in
this
as
circuit
oper
may
operation
hazard.
a
may
delays
which
Such
be
corrected
contains
fail-safe
to
have
and
away
circuit
incorrect
to
of
result
a
switching
circuit
the
not
or
whether
a
refered
designed
As
values.
cause
will
commonly
be
cannot
ideal
A logical
incorrectly.
ate
identical
from the
departure
this
signals
values;
gates.
H-1
Figure
function
function.
If
the
new
paths.
by
If
value
One
path
includes
gates
1
of
and
that
A
ABCD
is
4
and
less
Karnaugh
=
0110;
=
1110:
we
expect
F
output
3
and
6;
If
than the
the
total
delay
of
that
F
expect
we
the
1,
switching
of
toward
gates
6.
a
of
map
realization
gate
ABCD
propagates
includes
gates
3
that
assume
so
the
AND/OR
minimum
we
A
change
we
path
a.
and
contains
=
the
1.
1.
But
two
along
second
introduced
delay
gate
=
4
(
T,
+Tj<
T4
)
148
AB
01
oo
CD\
i o
11
Co
oo
1
1
1
n_i
1
o I
LtH^I>
Boi
i
l__
1
-o
F
1
i o
1
A
-
C
|
li
!
i
Switching
Function
and
A
o-
D
o-
Hazardous
a
FIGURE
Realization.
HI
AB
Q
OO
Q\
II
O I
D
G>
o-
oo
i I
O I
I
:
:.:
Y\ !
I
''I
\
V
h
r1
_j
1/
B
C
o-
B
o
Uh
o-
m>
[j>-J"
|J
I o
Ao
Do-
i
i
C
A
Network
Two
Input
which
is
Variables
o-
not
&X
Static
Change.
FIGURE
H2
E>
Hazard
Free
if
-oF
149
then for
a
period
at
all
input
on
the
output
enough
that
so
is
This
terminals
in
3
gates
proper
design,
and
4
vary the
of
the
gate
to
do
not
take
place
value
of
value
1
gate
cant
be
a
If
that
that
to
the
a
AND
gate
is
A
AND
gate
single
prime
minterms
gate
A is
is
variable
of
implicant
and
AND
to
gate
changed.
the
output
0.
If
this
a
problem
maintains
always
we
con
(adjacent
(the
this
an
possible
when
Figure
1110),
signal
time,
only
BCD
AND
implicauts.
to
implicant)
network
0110
additional
when
(prime
1
that
It
varied.
input
the
to
realizes
This
OR
redundant
covers
The
same
solution
add
we
covers
removed.
1
of
the
at
may
H-1
and
from
change
they
output
1
The
when
suitable
a
minterms).
AND
of
a
the
to
network.
prime
appear.
will
addition
changes
sider
F
of
these
0
that
implicant
1110.
cause
from
change
of
Figure
of
to
we
network
given
prime
minterm
AND
false
find
signal,
a
algebra
identified,
one
other
variations
in
are
directly
to
gates
these
to
input
long
remain
magnitudes
network
covers
another
correspond
signal
output
the
designing
when
these
the
delay
specific
appear
will
zero
ideal Boolean
appear
by
of
is
will
$
hazards
one
of
a
the
present
i.e.,
respond,
to
A
signals
be
will
zeros
gate.
input
static
and
When we
can
OR
these
0110
minterm
the
on
eliminated
selected
these
6
gate
Whether
depend
Once
be
if
the
of
contradiction
expression.
will
line
[T^CT^)]
time
of
H-1b
and
prime
hazard
continously
impli
will
presents
Consequently,
F may
150
not
vary
a
result
hazards
static
such
as
networks
function
MULTIPLE
prime
implicant
that
every
pair
two
or
either
the
then false
two
of
hazard
a
work
is
free
of
change
variable
from ABCD
1111
=
then
same
time,
must
change.
gate
before
be
can
and
map
illustrates
If
AND
delay
introduced
F may
appear.
hazard
appear
to X^.
switching
is
minterms
implicant.
prime
the
values
the
output
is
to
the
by
exists
a
of
gates
the
if
and
if
But
i.e.,
output
5
if
A
3
6
hazards.
C
four AND
all
provide
1's
the
(due
to
the
this
type
of
when
the
hazard may
f(Xj)
=
input
is
be
1
gates
to
false
OR
0)
changed
of
value
a
activity,
(or
eliminated
the
at
0's
a
net
varied
changed
are
than
=
The
is
input
the
H-2
input-
single
a
inverters),
f(XX)
of
generalization
function
provide
include
the
of
switching
of
4
and
arise
may
Figure
and
signals
change
hazards.
only
gates
static
static
a
hazards
0101,
AND
by
prevented
allowed.
to
generalization
static
static
is
a
of
generalized
temporarily
This
allowed
realization
Generalizing to
can
a
are
for preventing
that
static
of
variables
One
ways.
and
technique
provides
cover
summary,
by basing
gates
adjacent
selected
input
more
simultaneously,
static
of
In
INPUT-CHANGE HAZARDS
If
in
one
A.
of
from logic
eliminated
least
at
changes
a
on
such
by
covered
htb
these
of
and
f
=
0 (1)
from X
by including
T51
in the
sum-of
f
of
a
pr
.me
implicant
X1
that
covers
XJ
and
implicant BD
Prime
hazard
that
of-products
all
be
prime
expression
of
all
a
hazards
if
arbitrary
impli.ant
prime
included to
implicant s be
inclu
function.
Netw
of
a
input
will
changes
1011
minterms
and
not
1110
in the
sun-
based
upon
rks
be
static
(in general)
.ed
allo\
are
exists.
the
prevent
hazar-s
static
impli cants
prime
covers
such
Eliminating
sum
implicant
if
must
mentioned.
requires
the
expression
-products
free
of
all
ed.
No
prime
in I igure
H-2.
r
input
Thus,
not
the
smallest
of
Figure
both B
to
is
input
an
implicant
In
free
necessarily
If
D
change
4 is to
gate
the
be
such
that
the
OR
gate
and
in
input
then
0,
to
OR
all
,0's
output
and
the
output
1
The
to
.
The
are
X1
and
delays
to
of
the
false
have
the
effect
-ates
of
in
lays
sequence.
are
then D,
can
take
unknown,
or
D
we
then B,
either
the
Because
of
exact
cannot
conclude
the
gate
the
OR
two
paths
will
which
see.
marked
on
of
6
and
3
4
and
to
0.
Dif
and
de
these
sequence;
The
3
AND
of
5
i.e.,
changing B
of
an
gate
presented.
value
not
exists.
AND
g-ites
magnitude-
D
is
and
1110,
nal
si
of
temporarily
X^
wizard
signal
AND
X^
to
101
from
assume
delays
gate
X
function
a
varies
gate.
F may
are
versa
vice
from
the
0
from
change
may
ferences
1
from
or
change
than
function,
the
1110
minterm
covers
which
if
to
to
allowed
change,
to
jZf's
present
the
1011
hazards.
of
is
cube
H-2,
and
from
changes
B
network
the Karnaugh
152
Figure
of
map
H-2.
hazards
Function
dundant
if
gates
multiple
must
be
to
changes
restricted
operation.
Thus,
in
the
manner
are
restricted
when
a
which
to
are
it
second
is
eliminated
allowed
by
that
so
necessary for
restriction
networks
single
be
Function hazards
network.
a
input
cannot
are
is
operated:
input-variable
adding
are
re
common
input
changes
fault-free
placed
Input
upon
changes
variations.
153
APPENDIX I
ANALYSIS OF
THE
CMOS
GATE
M
The
1-1,
following
illustrate
will
P-and
consists
of
as
in Figure
shown
analysis
N-
CMOS
inverter,
The
Figure
It
characteristics.
(MOS)
transistors,
channel
1-2.
its
of
many
the
of
following
connected
equations
describe
t
the
channel
are
connected
together;
The
N-channel
device
"DN
characteristics
K
N
the
operating
'
VOUT
3 :
of
V0UT
-
transistors
in the
^VIN
vtn)
VIN
VTN
when
non-saturated
they
region:
(1-1)
VOUT/2
"
VIN > VTN
%
=
N
=
P
'
N
Surface
Z
*
C
ox/l
mobility
Z
=
Channel
width
L
=
Channel
length
C
=
0X
VTN
=
channel
of
Capacitor
formed
substrate
and
Threshold
voltage
by
metal
of
the
gate
Q2
carriers
silicon
154
1
II
III
I
vDD
10v
1
Q
,
Vout|
>10
,
IV
V
i
l
1
i
i i
I,
\l
I
li
jit
Ql
in
,li
vout
H-
1
1
'
,ll
ID
LVTP,''
Q.
1
Q2
3
ev^i
i
o
N
1 1
1
-^j
_LVss
5
Volt-age, Vj
input
Voltage Transfer Characteristics
FIGURE
CMOS Inverter.
of a
Ql
1
Vout-VTpSV|N>VTN
n
II
VIN
0*VIN*VTN
10
II
Q2
NO N -SAT. CUT-OFF
NON-SAT.
SAT.
vout-V-VINSVut_fVTN
III
SAT.
SAT.
Vot + VTN5VINVDD-VTP
IV
SAT.
NON-SAT.
VDD-VTP-VINVDD
V
Piece
wise
Transistors
CUT-
Equations showing
Ql & Q2 in Figure II
Linear
FIGURE 1-2
OFF
NON-SAT.
Operation
of
155
The
device
N-channel
K
operating
VIN
Where:
YQ^>
device
P-channel
T
^DP
region-.
-K
P
(1-2)
VTN
Y^
VIN>
=
saturated
N
"DN
The
in the
-
V^
VTN
operating
the
in
nou-seturated
(vout-vdd)'(vin-vdd-vtp>
Where
*
VOUT
^
VIN
'VOUI
VDD^
Z,
(1-3)
V,
+
TP
V,
VDD
TP
Threshold
=
Vrpp
VIN
"
region:
Z
jJP
*
voltage
C
Kn
of
Q1
OX
L
up
The
device
p-channel
K
P
=
Surface
mobility
in the
operating
.
"DP
Where :
VQuT
VIN
-
VTP
VDD
VIN
<
VDD
V
+
V-^
+
V
TP
TP
of
channel
saturation
carriers
region:
156
The
defined
in Eq.
in Figure
istics,
These
1-1,
and
in Eq.
in Eq.
and
inverter
the
have
1-1
are
Eq.
a
been
the
equations
1-2
the
transfer
DC
calculated
region
and
III
of
+10VDC
into
five
regions
Q2
are
summarized
for
the
N-
P-channel
channel
transistor
characteristics
of
the
follows:
as
Figure
of
character
voltage
divided
end
illustrated
transfer
supply
as
I-2b:
I7
'
DP
and
i
=
(1-5)
0
into
Eq.
1-5,
the
transfer
is
V
=
VDD
+
VTP
1
The
bz
is
1-4,
voltage
and
V
XD1T
voltage
,
and
inverter,
MOS
pair
transistors Q1
1-4,
transfer
Substituting
the
Using the D
1-1.
1-3
1-3,
VQUT)
of
transistor
In
1-2,
shows
versus
function
in Table
CMOS
complementary
characteristics
the
and
i-2b
(vIN
the
of
operation
equation
for
V0TJT
+
in
+
VTN
i
(1-6)
'"V P
region
II
is
(vdd-ytp-vin
(1-7)
V0UT~VIN~VTPH
_
KP
157
And
VQUT
VOUT
in
IV
region
is
(vin-vtn)2V'(vin-vdd-vtp)2
VIN VTN
(1-8)
^N
Figure
and
1-3
1-8)
inverter
illustrates
transfer
voltage
the
with
=
the
From
voltage,
transfer
transistor
K
the
K-n,
=
the
a
speed.
and
+2'
Kp
it
can
approximately
parameters
symmetry
for K
ing
is
V,
conditions
were
voltage
of
is
which
are
compromise
usually
between
3.0
VDD
=
+10.0VDC
would
apparent.
to
CMOS
4.5
for V
be
the
transfer
V,
TP
equal
However,
the
If
volts.
TN
when
to YT,~J2;
the
values
for
the
gate,
immunity
and
switching
different
noise
that
seen
equal
1-7,
assumed:
=
be
1-6,
the
VTp
obtained
transfer
1-5,
for
characteristics
1"
curve
(Eq.
calculated
following
KN/KP=
VTN
the
reflect
158
VTP:=
-3.0v
VTN=
+
10
i
i
2.0v
i
Q
i
^-V
TN-^
^
/DD=+10v
i
i
n
kn/kp=
1.0
/
A.
1/1
^
o
>
_)
_
A
4
...
.
O
>
0
z
_.
-
;
V
VTP
11
n
1
1
1
I
1
l
i
l
i
"^
i
i
10
11
V|N3VolfS
Complementary
Inverter Transfer Characteristics,
FIGURE
1-3
159
BIBLIOGRAPHY
1.
Lohmann, Dr. H.J. An Electronic Fail-Safe Logic in
Railway Signaling, paper sul5mrtTed"~:E"o institute of
RaTTway "S"ighaT "Engineers, Proceeding, 1966-67.
2.
Starr,
Risk,
Chauncey.
Social
Paper
fits Versus
af
gympd'sTunTon
Technological
Human
TcdTogyT
*
3.
Hammer,
Safety,
Willie,
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