Characterization and Modeling of SiC Power MOSFETs
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in
the Graduate School of The Ohio State University
By
Xiangxiang Fang
Graduate Program in Electrical and Computer Science
The Ohio State University
December 2012
Master's Examination Committee:
Professor Wu Lu, Advisor,
Professor Jin Wang
Copyright by
Xiangxiang Fang
2012
Abstract
SiC power MOSFETs are great candidates for high-voltage power switching
applications because of their lower on-resistance and faster switching speed compared
with silicon power MOSFETs. In this study, a TO-247 packaged, 1.2KV, 15A SiC
MOSFET manufactured by GE has been investigated. The static characteristics of the
device have firstly been performed using an Agilent power curve tracer at room
temperature to get basic device performance, including DC characteristics (currentvoltage characteristics, I-V) and AC characteristics (capacitance-voltage characteristics
C-V). The input, output, reverse transfer capacitance of SiC MOSFET (CISS, COSS, CRSS
respectively) and package stray inductances are of vital importance to the SiC MOSFET
as they determine the dynamic behavior of the device during switching transients.
Based on the characterization results, two different modeling methods have been
implemented for the SiC MOSFET. A double-pulse tester (DPT) was built to perform
switching characteristics of SiC MOSFET at 100V drain bias, 10A load current level and
the same DPT circuit has been implemented in Synopsys Saber to verify the device
models previously built. By comparison of simulated static and dynamic characteristics to
measurement data, both models we built have been verified. Good agreements were
obtained between the device models and experimental results. Approaches to improve the
models have been investigated and limitations of the model have been discussed.
ii
Dedication
This document is dedicated to my family.
iii
Acknowledgments
Firstly, I would like to express my sincere appreciation to my advisor, Dr. Wu Lu
for his kindly guidance and continuous support through my Master study and work at The
Ohio State University. Without his guidance, it’s impossible for me to finish this thesis.
Dr. Lu is an advisor who is always working hard and willing to talk and teach his
students with patience. I really enjoyed the one-to-one meeting with him every week,
discussing the basic semiconductor physics, device characterization and modeling, etc.
He is intelligent and always shows the right way to solve the problem I encountered. I
am very lucky to have him as my advisor.
I am deeply grateful to Dr. Jin Wang for sparing a time to be my Master committee
member, and greatly appreciate his help to build the double-pulse tester and provide test
instruments for power device switching characterization. Without his help, the device
model verification would be impossible to be done. Also thanks to Dr. Longya Xu and Dr.
Siddharth Rajan for their help. Special thanks also go to Ye Shao, Mark Scott and Lixing
Fu for their guidance of experimental measurements and assistance in collecting
experimental data.
Finally, I would like to thank my parents for their love and encouragement in the
past years and their confidence in me.
iv
Vita
2006 to 2010 ..................................................B.S. Electronic Science and Technology,
Shanghai University
July 2012 to August 2012 .............................Graduate Research Assistant, Department of
Electrical and Computer Engineering, The
Ohio State University
Fields of Study
Major Field: Electrical and Computer Engineering
v
Table of Contents
Abstract ............................................................................................................................... ii
Dedication .......................................................................................................................... iii
Acknowledgments.............................................................................................................. iv
Vita...................................................................................................................................... v
List of Tables ..................................................................................................................... ix
List of Figures ..................................................................................................................... x
Chapter 1 Introduction ........................................................................................................ 1
1.1 Fundamental Properties of Semiconductor Power Devices ...................................... 1
1.2 Power MOSFETs Structures ..................................................................................... 4
1.3 Research Motivations and Objectives ....................................................................... 6
1.4 Organization of Thesis .............................................................................................. 7
Chapter 2 Static characterization ........................................................................................ 8
2.1 Introduction ............................................................................................................... 8
2.2 Agilent power device curve tracer and text fixture ................................................... 9
2.3 Characterizations of SiC MOSFET ......................................................................... 10
vi
2.3.1 Drain-source leakage current IDSS..................................................................... 10
2.3.2 Gate-source leakage current IGSS ...................................................................... 11
2.3.3 Output and Transfer Characteristics ................................................................. 12
2.3.4 On-State Resistance Rds(on) ............................................................................ 13
2.3.5 Gate Threshold Voltage VGS(TH) ....................................................................... 15
2.3.6 Body Diode I-V Characteristics ....................................................................... 16
2.3.7 Gate Capacitance (Cg-Vg Curve) ..................................................................... 17
2.3.8 Nonlinear Junction capacitances CISS, CRSS, COSS ............................................ 18
2.3.9 Internal Gate Resistance RGI............................................................................. 23
2.3.10 Package Stray Inductance measurement......................................................... 23
2.4 Conclusion............................................................................................................... 24
Chapter 3 : Modeling of 1.2KV, 15A SiC MOSFETs ...................................................... 25
3.1 Introduction ............................................................................................................. 25
3.2 Modeling of SiC MOSFET using nonlinear curve-fitting method ......................... 26
3.2.1 Sub-circuit model structure of SiC MOSFET .................................................. 26
3.2.2 MOS.................................................................................................................. 26
3.2.3 Three Junction capacitors ................................................................................. 29
3.2.4 Body Diode ....................................................................................................... 29
3.2.5 Other parameters............................................................................................... 31
vii
3.3 Saber Power MOSFET Tool ................................................................................... 32
3.4 Conclusion............................................................................................................... 39
Chapter 4 Characterization and modeling of SiC MOSFET switching behavior ............. 40
4.1 Fundamental of SiC Power MOSFET Switching Characteristics ........................... 40
4.2 Double Pulse Tester (DPT) for Dynamic Switching Performance Characterization
....................................................................................................................................... 46
4.3 Switching characteristics modeling using Saber ..................................................... 48
4.4 Conclusion and Discussion ..................................................................................... 56
Chapter 5 Concluding Remark.......................................................................................... 58
References ......................................................................................................................... 59
viii
List of Tables
Table 1.1 Comparison of Si, GaAs and SiC material properties ........................................ 2
Table 3.1 SiC MOSFET model parameters ...................................................................... 32
Table 3.2 DC Model parameters ....................................................................................... 34
Table 3.3 Capacitance model parameters ......................................................................... 36
ix
List of Figures
Figure 1.1 Comparison of specific on-resistance versus breakdown voltage for Si and 4HSiC....................................................................................................................................... 4
Figure 1.2 Vertical-diffused (VD) MOSFET structure....................................................... 6
Figure 2.1 TO-247 package ................................................................................................ 8
Figure 2.2 Agilent B1505A Power Device Analyzer / Curve Tracer ............................... 10
Figure 2.3 Agilent N1259A High Power Text Fixture ..................................................... 10
Figure 2.4 Drain-Source leakage current vs. Drain voltage. The gate is shorted to the
source ................................................................................................................................ 11
Figure 2.5 Test circuit for IDSS .......................................................................................... 11
Figure 2.6 Test circuit for IGSS .......................................................................................... 12
Figure 2.7 Gate-source leakage current as a function of gate voltage. The drain is shorted
to the source ...................................................................................................................... 12
Figure 2.8 Test circuit for output characteristics .............................................................. 13
Figure 2.9 Output characteristics. The gate is biased from 4 V to 20 V with a step of 4V
........................................................................................................................................... 13
Figure 2.10 Test circuit for transfer characteristics .......................................................... 13
Figure 2.11 Transfer characteristics. The drain bias is 10V ............................................. 13
Figure 2.12 Power D-MOSFET structure ......................................................................... 15
x
Figure 2.13 Test Circuit for characterization of VGS(TH) .................................................. 16
Figure 2.14 Drain current as a function of gate (drain) bias. The drain is shorted to the
gate .................................................................................................................................... 16
Figure 2.15 Test Circuit for body diode I-V ..................................................................... 17
Figure 2.16 Body Diode I-V Curve (Forward) ................................................................. 17
Figure 2.17 Body Diode I-V curve (reverse) .................................................................... 17
Figure 2.18 Test circuit for Cg-Vg .................................................................................. 18
Figure 2.19 Cg-Vg curves ................................................................................................. 18
Figure 2.20 The B1505A high-voltage Bias-T connects to the MFCMU and HVSMU
modules to provide up to 3000 V of DC bias during capacitance measurements ............ 19
Figure 2.21 COSS connection scheme. ............................................................................... 20
Figure 2.22 COSS - VDS curve. The drain is swept from 1 to 500 V with a step of 1 V and
oscillation level of 20 mV at 100 kHz. ............................................................................. 20
Figure 2.23 CRSS connection scheme ................................................................................ 21
Figure 2.24 CRSS -VDS curve. The drain is swept from 1 to 500 V with a step of 1 V and
oscillation level is 20 mV at 100 kHz. .............................................................................. 21
Figure 2.25 CISS connection scheme ................................................................................. 22
Figure 2.26 CISS -VDS curve. The drain voltage is swept from 0 to 500 V with a step of 1
V and oscillation of 20 mV signal at 100 kHz .................................................................. 22
Figure 2.27 C-Vds curves ................................................................................................. 22
Figure 2.28 RGI Measurement setup ................................................................................. 23
Figure 2.29 equivalent circuit (RGI) .................................................................................. 23
xi
Figure 3.1 sub-circuit model for SiC MOSFET................................................................ 26
Figure 3.2 Comparison of measured and modeled output characteristics. ....................... 28
Figure 3.3 Comparison of measured and modeled transfer characteristics at Vds =10 V.28
Figure 3.4 Body diode I-V measurement result (blue) and curve-fitting result (pink) ..... 30
Figure 3.5 Body diode I-V measurement result (blue) and simulation result from
analytical model (red) ....................................................................................................... 31
Figure 3.6 Saber Power MOSFET Tool interface ............................................................ 33
Figure 3.7 Simulated and measured output characteristics ............................................... 34
Figure 3.8 Simulated and measured transfer characteristic .............................................. 35
Figure 3.9 Simulated and measured C- VDS characteristics.............................................. 37
Figure 3.10 Simulated (analytical model) and measured C- VDS characteristics ............. 38
Figure 3.11 Simulated and measured body diode I-V forward characteristic .................. 39
Figure 4.1 Schematic circuit diagram of a clamped inductive load test circuit for SiC
MOSFETs ......................................................................................................................... 41
Figure 4.2 SiC MOSFET turn-on transient process
Figure 4.3 SiC MOSFET turn-off
........................................................................................................................................... 45
Figure 4.4 Double pulse tester switching characterization setup. ..................................... 47
Figure 4.5 SiC MOSFET double pulse tester circuit board top layer ............................... 47
Figure 4.6 SiC MOSFET double pulse tester circuit board bottom layer ......................... 48
Figure 4.7 Diode Forward I-V curve ............................................................................... 48
Figure 4.8 Diode junction capacitance.............................................................................. 48
xii
Figure 4.9 Schematic circuit digram of a clamped inductive load test circuit for SiC
MOSFET ........................................................................................................................... 49
Figure 4.10 Experimental and simulated waveforms. Turn-on process at Rg = 2.7 Ω..... 50
Figure 4.11 Experimental and simulated waveforms. Turn-off process at Rg = 2.7 Ω .... 50
Figure 4.12 Experimental and simulated waveforms. Turn-on process at Rg = 5 Ω........ 51
Figure 4.13 Experimental and simulated waveforms. Turn-off process at Rg = 5 Ω ....... 51
Figure 4.14 Experimental and simulated waveforms. Turn-on process at Rg = 10 Ω...... 52
Figure 4.15 Experimental and simulated waveforms. Turn-off process at Rg = 10 Ω ..... 52
Figure 4.16 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg = 2.7 Ω .......................................................................................... 53
Figure 4.17 Measured and simulated transient response in the turn-off process with gate
drive ressitance of Rg = 2.7 Ω .......................................................................................... 53
Figure 4.18 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg = 5 Ω ............................................................................................. 54
Figure 4.19 Measured and simulated transient response in the turn-off process with gate
drive resistance of Rg = 5 Ω ............................................................................................. 54
Figure 4.20 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg =10 Ω ............................................................................................ 55
Figure 4.21 Measured and simulated transient response in the turn-off process with gate
drive resistance of Rg = 10 Ω ........................................................................................... 55
xiii
Chapter 1 Introduction
1.1 Fundamental Properties of Semiconductor Power Devices
Silicon-based power semiconductor devices have dominated the power electronics
and power systems applications for a long time because of its numerous advantages.
Examples of the silicon-based power devices are diodes, thyristors, bipolar junction
transistors (BJTs), insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor
field-effect transistors (MOSFETs), etc. As the demand for faster switching speed
devices with higher voltage capability growing, silicon-based power devices suffers from
limitations due to some inherent material properties, such as low bandgap energy, small
critical electric field, low thermal conductivity, and switching frequency limitations [1].
Efforts have been made since 1980s to develop power devices using gallium arsenide.
However, interest in this technology has dwindled because much attention has been
focused on the much more promising wide bandgap semiconductor materials for power
devices applications [2].
Compared to silicon-based power devices, devices made of wide bandgap
semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), have superior
advantages as follows: (1) Energy bandgap: wide bandgap semiconductors have wider
energy bandgaps, which result in much lower leakage currents and higher operating
1
temperatures; (2) Critical electric field: wide bandgap semiconductors have higher critical
electric fields so that devices can have higher doping concentrations with thinner
blocking layers, and resulting in lower specific on-resistance. (3) Electron saturation
velocity: wide bandgap semiconductors have higher electron saturation velocity, which
leads to higher operating frequencies compared to equivalent silicon-based devices; (4)
thermal conductivity: SiC has higher thermal conductivity which improves heat
spreading and allows operation at higher power densities [3]. In Table 1.1, the key
materials properties are listed for the main wide bandgap semiconductors SiC compared
with Si and GaAs[4].
Property
Si
GaAs
6H-SiC
4H-SiC
Bandgap Eg(300 K)
1.12
1.43
3.0
3.2
Critical electric field Ec(V/cm)
2.5 105
Thermal conductivity λ (W/cmK at 1.5
105
0.5
2.5 10
3-4
2.2 10
3-4
300k)
Saturated electron drift velocity, vsat
1 107
1 107
2 107
2 107
(cm/s)
Electron Mobility,
Hole Mobility,
p
n
(cm2 / s
(cm2 / s
Dielectric constant
r
1350
8500
500
950
480
400
80
120
11.9
13.0
10
10
Table 1.1 Comparison of Si, GaAs and SiC material properties
2
Silicon carbide exists more than 150 polytypes, and 4H-SiC is the most popular
candidate for power devices since its properties are superior to those of other polytypes of
silicon carbide (e.g. 3C-SiC, 6H-SiC ). As can be obviously seen from Table 1-1, 4H-SiC
has larger bandgap energy of 3.2eV compared to the 1.12eV bandgap of silicon and
1.43eV bandgap of GaAs [5]. Besides, 4H-SiC’s saturated electron drift velocity of
2 107 cm/s is about an order of magnitude larger than silicon’s. 4H-SiC’s high thermal
conductivity of 3-4 W/cmK enhances heat dissipation and allows the devices efficiently
operating at higher temperature up to 350 °C. Moreover, 4H-SiC has a higher critical
electric field of 2.2 10 V/cm, which is about 9 times larger than that of silicon. Specific
on-resistance (Ron) is a critical parameter to the power devices since it determines directly
how much resistive loss a device will generate in forward conduction mode [1,5]. Ron can
be calculated from Eq.1,
Ron =
4 2
(1)
n C
Where VB is the breakdown voltage and Ec is the critical electrical field, the unit of the
on-resistance is mΩcm2. Based on the equation above, Ron is reversely proportional to
Ec, which means a higher Ec leads to a much lower Ron for 4H-SiC. Fig. 1.1 shows the
theoretical specific on-resistance of blocking regions designed for certain breakdown
voltages in Si and 4H- SiC, under optimum punch-through conditions [6]. As can be seen
from the Figure.1.1, the specific on-resistance of 4H-SiC is about 400 times smaller than
that of Si at a given breakdown voltage. It makes the devices able to operate at higher
current level with relatively lower forward voltage drop. Based on various advantages
listed above, SiC turns out to be better than silicon and gallium arsenide as the material of
3
choice for power devices.
Figure 1.1 Comparison of specific on-resistance versus breakdown voltage for Si and 4HSiC
1.2 Power MOSFETs Structures
Power MOSFETs are the most commonly used power devices due to their superior
performance over BJT, IGBT, thyristor, etc [7]. They need lower gate drive power, and
they have faster switching time, no secondary breakdown, and stable gain and response
time over a wide temperature range. Several power MOSFETs structures have been
explored since the 1970s. Most power MOSFETs have a vertical structure with source
and drain on opposite sides of the wafer in order to support higher current and voltage.
The first high-voltage power MOSFET structure (V-MOSFET) was developed by using a
V-groove etching process4 during the 1970s. Then during the late 1980s, the technology
for etching trenches in silicon became available and this process was adopted by the
4
power semiconductor industry to develop the trench-gate or U-MOSFET structure.
Another widely used power MOSFETs structure is vertical DMOSFET, which uses a
double-diffusion process. Figure 1.2 shows the cross section of the basic structure for the
vertical DMOSFET. Firstly, an N- type epitaxial layer grown on a heavily doped N+
substrate. The device channel is formed by the difference in lateral extension of the Pbase region and N+ source region. The p-base region should be diffused deeper than the
n+ source. The n- drift region must be moderately doped so that the drain breakdown
voltage is sufficiently large and the thickness of the n-drift region is made as thin as
possible to minimize drain resistance. Without adding a gate bias, a high voltage can be
supported in the vertical DMOSFET structure when a positive bias is applied to the drain.
In this situation, junction J1 formed between the P-base region and the N-drift region
becomes reversely biased. The voltage is supported mainly within the thick lightly doped
N- drift region. By adding a positive gate bias, drain current flow is introduced in the
vertical DMOSFET structure. A relatively narrow JFET region is generated between the
adjacent P-Base regions. Due to the constriction of the current flow through the JFET
region, the internal resistance would increase in the vertical DMOSFET structure. As a
result, the gate width should be carefully chosen to minimize the internal resistance for
this structure. Several commercialized SiC DMOSFETs manufactured by Cree and GE
can be found in [5, 8]
5
Figure 1.2 Vertical-diffused (VD) MOSFET structure
1.3 Research Motivations and Objectives
A lot of efforts have been made to improve the performance of SiC power devices
recently. The basic characteristics of SiC MOSFETs and their potential utilization in
power electronics and power converter systems have been deeply investigated. Several
different kinds of physical-based models and analytic device models have also been
proposed for SiC MOSFETs.
The objective of this thesis research is to study the fast-switching-speed behavior of
SiC MOSFETs. The background of this work is to support the development a SiC-based
Multi-Mode Integrated Converter Controller (MMICC). The long term goal is to build
the SiC-based Integrated Converter Controller by replacing the existing Si power
modules with SiC devices or modules for the main inverter. A breadboard Integrated
Converter Controller based on SiC devices or modules will be built and tested, and the
results will be compared with those from real time or hardware-in-loop simulations. The
6
goal of this MS thesis project is to develop simplified but accurate device models for SiC
MOSFETs that can be used for real time simulations and MMICC design.
To achieve this goal, SiC MOSFETs manufactured by GE with 1.2 kV voltage and
15 A current rating are characterized. The basic characterization method and processes
will be explained and discussed in detail. Based on the characterization results, SiC
MOSFET models have been established and implemented in a circuit simulator to
compare the simulation results with measurement results. Issues regarding the model
accuracy and approaches to improve the model will also be discussed.
1.4 Organization of Thesis
The following of this thesis described the details of the above mentioned research
goals.
The instruments used to do the measurements and approaches employed to do the
characterization of SiC MOSFETs will be discussed in Chapter 2.
In Chapter 3, an analytic model will be developed and the experimental results will
be used to extract the model parameters. Two different device modeling procedures will
be presented and relative modeling issues will be discussed to improve models’ accuracy.
Chapter 4 shows the switching characterization process for the SiC MOSFET. The
same switching characterization test circuit will be built in Saber to simulate the
switching behavior. Simulation and experimental results will be compared at last.
Chapter 5 summarizes the research work and some future work to improve the
model is also suggested.
7
Chapter 2 Static characterization
2.1 Introduction
This chapter describes the basic static characterization procedures for the SiC
MOSFET. The SiC MOSFET investigated here is a 1.2 KV, 15 A SiC MOSFET
manufactured by General Electric Company (GE) with a T0-247 package (Figure 2.1).
The three leads G, D, S shown in Figure 2.1 are gate, drain and source respectively.
There is no manufacturer datasheet for this device because it has not been
commercialized yet. Therefore, in order to evaluate its potential performance in
Integrated Converter Controller (ICC) and compare it with the existing Si device/module,
characterization of this SiC MOSFET is the first step of this thesis research.
Figure 2.1 TO-247 package
8
The static characterizations of SiC MOSFET mainly include DC characterization
and AC characterization. When we talk about DC characterization of MOSFETs, it
basically contains output and transfer characterization, gate and drain leakage current
characterization, on-state resistance and threshold voltage measurement and body diode
I-V characterization. For AC characterization, it represents input, output and reverse
transfer capacitance characterization, the internal gate resistance characterization and
inductance measurement introduced by the T0-247 package. In this work, both DC and
AC characterization was performed by using a very powerful equipment “Agilent
B1505A power device analyzer/curve tracer” at room temperature [9]. Detail information
about the curve tracer will be introduced in the following section.
2.2 Agilent power device curve tracer and text fixture
Agilent B1050A Power Device Analyzer/ Curve Tracer (Figure 2.2) is designed for
measuring power devices. Its high voltage source measurement unit (HVSMU) supports
high voltage measurement up to 3000 V with a current limit of 4mA and its high current
source measurement unit (HCSMU) supports high current measurement up to 20 A with
a voltage limit of 20 V [10]. Agilent B1505A has both DC and AC parametric
measurement capabilities that provide the DC voltage and current output capability, DC
voltage and current measurement capability, and AC signal output and impedance
measurement capability. For example, it can be used to perform a single or multi-channel
current-voltage (I-V) sweep measurement, capacitance-voltage sweep measurement and
I/V-T sampling measurement, etc. The Agilent N1259A high power test fixture which is
9
used to perform the packaged power device is shown in Figure 2.3. Similar to Agilent
B1505A, N1259A is capable of handling 3000 V maximum voltage and 20 A maximum
current [10]. To do the measurement, the packaged device should be inserted into the
socket on the N1259A text figure. Test leads should be used to make appropriate
connection among the three terminals of the device and those source measurement units,
and corresponding coaxial or triaxial cables are used to connect the text fixture with
curve tracer. The text fixture’s cover needs to be closed and measurement conditions are
set in curve tracer.
Figure 2.2 Agilent B1505A Power Device
Analyzer / Curve Tracer
Figure 2.3 Agilent N1259A High Power
Text Fixture
2.3 Characterizations of SiC MOSFET
2.3.1 Drain-source leakage current IDSS
IDSS is the drain-source leakage current at a specified drain-source voltage when the
gate-source voltage is zero (VGS=0 V). It is used to evaluate the blocking capability of the
device. The High Voltage SMU of the curve tracer is chosen to measure IDSS and the test
10
circuit is displayed in Figure 2.4. Figure 2.5 shows the drain-source leakage current
versus drain-source voltage. As shown in the figure, the drain-source leakage current for
this SiC is about 200 A at 1100 V drain-source voltage, which indicates a very high
drain avalanche breakdown voltage of the device. When the drain voltage is above 1100
V, it can be clearly seen that the current increase dramatically due to the avalanche effect
caused by impact ionization.
Figure 2.4 Drain-Source leakage current vs.
Drain voltage. The gate is shorted to the
source
Figure 2.5 Test circuit for IDSS
2.3.2 Gate-source leakage current IGSS
IGSS is the leakage current that flows through the gate terminal at a specified gatesource voltage while drain-source voltage is zero (VDS = 0 V). The IGSS is obtained to be
about 1.822 nA at VGS = 25 V and VDS = 0 V.
11
Figure 2.6 Test circuit for IGSS
Figure 2.7 Gate-source leakage current as a
function of gate voltage. The drain is shorted
to the source
2.3.3 Output and Transfer Characteristics
The output characteristics are drain current Id versus drain-source voltage VDS
measured under different gate voltage VGS from 4 V to 20 V in 4 V step. The transfer
characteristics are obtained at VDS = 10 V while VGS is swept. Figure 2.8 and 2.9 show the
test circuits for output and transfer characteristics respectively and Figure 2.10 and Figure
2.11 are the output and transfer characteristic for the SiC MOSFET at room temperature.
12
Figure 2.8 Test circuit for output characteristics
Figure 2.9 Output characteristics. The gate is
biased from 4 V to 20 V with a step of 4V
Figure 2.10 Test circuit for transfer characteristics
Figure 2.11 Transfer characteristics. The
drain bias is 10V
2.3.4 On-State Resistance RDS(on)
The on-state resistance RDS(ON) is a critical parameter to the device since it
determines the conduction power dissipation. Figure 2.12 shows the power D-MOSFET
structure with its eight internal resistance components between the drain and source
13
electrodes when the device at turned-on state. The total on-state resistance is the sum of
the eight resistances, which can be expressed as RDS(on) = RCS + RN+ + RCH + RA + RJFET
+ RD + RSUB + RCD. Where RCS is source contact resistance, RN+ is the source resistance,
RCH is channel resistance, RA is accumulation resistance, RJFET is JFET resistance, RD is
drift region resistance, RSUB is the substrate resistance and RCD is the drain contact
resistance. Detailed introduction about each resistance component can be found in
[11].There are several different definitions for the RDS(ON), and some papers define it to
be the maximum slope of the output curve at a given turn-on gate voltage[12-13]. This
definition gives the minimum possible RDS(ON) for a given VGS, which resulting in RDS(ON)
= 0.129 Ω at VGS = 20 V in our case. While in most commercialized SiC MOSFET
datasheets, RDS(ON) is defined at a specific drain current [14]. In this work, RDS(ON) can be
read directly from the output characteristic curves. RDS(ON) is defined to be the value
extracted at a specific turn-on gate voltage VGS and drain current IDS. Here, RDS(ON) is
obtained to be about 0.141 Ω at
GS
= 20 V and IDS =15 A.
14
Figure 2.12 Power D-MOSFET structure
2.3.5 Gate Threshold Voltage VGS(TH)
Gate threshold voltage, VGS(TH), is defined as the minimum gate bias required to
form a conducting channel between the source and drain regions or to turn on the device .
If VGS(TH) is defined as the gate-source voltage which produces 10 A drain current when
the drain and gate terminals are shorted (VGS = VGD) [15], we can obtain VGS(TH) = 1.57
V. If we use bigger drain current such as 10 mA, a higher threshold VGS(TH) = 3.30 V is
obtained. Figure 2.13 and 2.14 show the test circuits for output and transfer
characteristics, respectively.
15
Figure 2.13 Test Circuit for characterization of
VGS(TH)
Figure 2.14 Drain current as a function of gate
(drain) bias. The drain is shorted to the gate
2.3.6 Body Diode I-V Characteristics
Different from a conventional lateral structure MOSFET, SiC MOSFET has intrinsic
body diode due to its vertical device structure. The measurement of body diode is the
same to a two-terminal ordinary diode measurement, except that the gate and source of
the SiC MOSFET should be shorted (VGS = 0 V). The test circuit for the body diode
characterization is shown in Figure 2.15 .The forward biased body diode I-V curve and
the reverse biased body diode I-V curve are shown in Figure 2.16 and Figure 2.17.
16
Figure 2.15 Test Circuit for body diode I-V
Figure 2.16 Body Diode I-V Curve
(Forward)
Figure 2.17 Body Diode I-V curve (reverse)
2.3.7 Gate Capacitance (Cg-Vg Curve)
Figure 2.18 shows the measurement setup to obtain the Cg-Vg curves at five
different frequencies (Figure 2.19). Cg-Vg Curves differ from each other in the following
three regions: accumulation region, depletion region and strong inversion region [16]. As
can be seen, compared to relatively lower frequency levels (e.g. 100 MHz, 1 KHz, 10
KHz, 100 KHz), the capacitance is much smaller in accumulation and strong inversion
region when the frequency is 1 MHz. This is due to the inability of the holes in
accumulation regions and electrons in inversion region to response to higher frequency
signals [17].
17
Figure 2.18 Test circuit for Cg-Vg
Figure 2.19 Cg-Vg curves
2.3.8 Nonlinear Junction capacitances CISS, CRSS, COSS
Usually, by using a LCR Meter or impedance analyzer only is not a feasible way to
do the input, output and reverse transfer capacitance measurement since the general LCR
Meters or impedance analyzers don’t have a high DC voltage source (e.g. maximum 40 V
for Agilent 4248A LCR Meter). A usual way to solve this problem is to build a complex
test circuit with a DC power supply to support higher drain bias as well as a LCR Meter
to measure capacitances [18-19]. In our case, a better way to do the measurement is to
use the Agilent B1505A Power Device Analyzer/Curve Tracer mentioned above since it
supports a high-voltage source/monitor unit (HVSMU), a multi-frequency capacitance
measurement unit (MFCMU), and a high-voltage bias-T that makes it very easy to
directly measure the three nonlinear capacitances up to 3000 V [20]. Figure 2.20 shows
the connection between the high-voltage Bias-T, MFCMU and HVSMU to provide dc
bias up to 3000V during the capacitance measurements.
18
Figure 2.20 The B1505A high-voltage Bias-T connects to the MFCMU and HVSMU
modules to provide up to 3000 V of DC bias during capacitance measurements
(1) SiC MOSFET output capacitance: COSS (= CDS + CGD)
For the capacitance measurement, we use the multiple frequency capacitance
measurement unit (MFCMU), which has four ports (Hp,Hc,Lp,Lc). Hp and Hc are
shorted together (labeled as “CMH” and Lp and Lc are shorted together (CML).To
measure COSS, we simply need to short the gate and source terminals using a wire as
shown in Figure 2.21. At the same time, HVSMU, high-voltage bias-T and MFCMU
should be connected properly for biasing. In this work, COSS (Figure 2.22) is measured
under F = 100 KHz, VDS from 0 V to 500 V with 1 V step. The oscillation level is = 20
mV.
19
Figure 2.21 COSS connection scheme.
Figure 2.22 COSS - VDS curve. The drain
is swept from 1 to 500 V with a step of 1
V and oscillation level of 20 mV at 100
kHz.
(2) SiC MOSFET reverse capacitance CRSS (= CGD)
CRSS is equivalent to CGD, so to make this measurement we need to remove any
interference from CDS and CGS by using the AC guard. The AC guard is used to provide
an alternative current path so that the current flowing through CDS does not flow back
through CGS into the CML node. So what we measured between the CMH node and CML
node is only CGD. In this work, CRSS is measured under F = 100 KHz, VDS from 0 V to
500 V with 1 V step. The oscillation level is = 20 mV. Figure 2-23 shows the connection
scheme of CRSS and Figure 2.24 shows the CRSS -VDS curve.
20
Figure 2.23 CRSS connection scheme
Figure 2.24 CRSS -VDS curve. The drain is
swept from 1 to 500 V with a step of 1 V
and oscillation level is 20 mV at 100
kHz.
(3) SiC MOSFET input capacitance CISS (=CGD+CGS)
For the input capacitance measurement, we need to use an external blocking resistor
(100 kΩ) and capacitor (1 F). The capacitor has to be much larger than CGD or CDS
(junction capacitances are usually in the range of tens of pF to several nF), and it acts as a
DC blocking capacitor. Conversely, we need to connect the HVSMU to the drain through
a relatively large resistor to prevent the HVSMU from interfering with the AC signal
coming from the MFCMU. The measured capacitance should be CGS in parallel with the
series combination of CGD and (1 F + Cds—1 F capacitor is in parallel with CDS).
Finally, we can get the measured capacitance Cm ≈ CGD + CGS = CISS. In this work, CISS is
measured under F = 100 KHz, VDS from 0 V to 500 V with 1 V step. The oscillation level
is = 20 mV. Figure 2.25, 2.26 shows the connection scheme of CISS, CISS -VDS curve
respectively and Figure 2.27 shows the three junction capacitance as a function of VDS.
21
Figure 2.25 CISS connection scheme
Figure 2.26 CISS -VDS curve. The drain
voltage is swept from 0 to 500 V with a
step of 1 V and oscillation of 20 mV
signal at 100 kHz
Figure 2.27 C-Vds curves
22
2.3.9 Internal Gate Resistance RGI
Besides the three nonlinear capacitances, the internal gate resistance is also a vital
parameter since it affects the switching speed of the device. The measurement of RGI is
carried out with a LCR Meter measuring the gate and source terminals while the drain
and source terminals are shorted (Figure 2.28,2.29) [21]. The RGI is measured to be
0.55Ω at 100 KHz.
Figure 2.28 RGI Measurement setup
Figure 2.29 equivalent circuit (RGI)
2.3.10 Package Stray Inductance measurement
The device is packaged in a TO-247 package. The stray impedances introduced by
the package can be expressed as three inductances LG, LD and LS, which are in series with
the gate, drain and source terminals respectively [22]. Inductances are measured between
the root of the leads and center of die contact. In this case, inductances are measured to
be LG = 9.23 nH, LD = 5.93 nH and LS = 7.52 nH.
23
2.4 Conclusion
This chapter has presented the static characterization of the 1.2 kV, 15 A SiC
MOSFET, including output and transfer characterization, gate and drain leakage current
characterization, on-state resistance and threshold voltage characterization, body diode IV characterization and three junction capacitance, the internal gate resistance and
package stray inductance characterization. The static characterization results show the
SiC MOSF ’s superiority in blocking higher voltage while still keeping a very low onresistance value.
24
Chapter 3 : Modeling of 1.2KV, 15A SiC MOSFETs
3.1 Introduction
In order to make the device model adoptable and suitable in the system-level
simulation for the later Multi Mode Integrated Converter Controller design, a concise
model is preferred in our case to make the system-level simulation run as fast as possible.
So far, a lot of efforts have been made on the SiC MOSFET modeling, many of which is
focused on developing physics-based models for the SiC MOSFET [23-25]. To develop
physics-based device models, it’s necessary to be familiar with the whole device
fabrication process and all parameter information like the device channel length and
width, the thickness of the gate oxide layer, N- drift region and substrate, doping
concentration of the JFET region ,P-wells and N-drift region, etc. However, most of
these parameters which are needed to develop models are not avaiable to us. In this case,
we decided to develop sub-circuit models for SiC MOSFETs. The advantage to build
sub-circuit models is that by doing characterization of devices, model parameters can be
directly extracted from characterization results without knowing detailed structure
information of devices [26].
25
3.2 Modeling of SiC MOSFET using nonlinear curve-fitting method
3.2.1 Sub-circuit model structure of SiC MOSFET
Figure 3.1 shows the sub-circuit model structure of SiC MOSFET. It includes a
MOS, three junction capacitors, a reverse body diode, an internal gate resistor and three
package stray inductors.
Figure 3.1 sub-circuit model for SiC MOSFET
The following described the details of main components in the above SiC MOSFET subcircuit model.
3.2.2 MOS
The MOS part is modeled as a voltage controlled current source which can be used
to describe the static I-V output and transfer characteristics of the device. We developed
an analytic model to describe the output characteristics [27].
26
=0,
=2
=2(
S-
H
S [2(
H )-
S-
H)
S-
where = n CO
0
W
L
,
2
(1 λ
S ](1
S ),
0
λ
S ),
S-
0
H
S
S-
(Cut-off regime)
(2)
(Linear regime)
(3)
(Saturation regime)
(4)
H
S
is the charge-carrier effective mobility, CO is the capacitance of
the oxide layer, L is channel length and W is the channel width. Since the device
dimensions (gate oxide thickness and channel width/length ratio) are not available, the
parameter
is used here to represent the product of these four parameters. VTH is the
threshold voltage and λ is the channel-length modulation parameter. A non-linear curvefitting method is carried out in OriginLab to extract these parameters. The results are
shown in Figure 3.2 and 3.3. A good agreement is achieved between the measurement
and simulation results.
The blue lines are the measurement results and the dashed lines are the curve-fitting
results. The threshold voltage VTH is 5.86 V,
obtained through extraction.
27
is 0.5006 AV-2 and λ is 0.04 47
Figure 3.2 Comparison of measured and modeled output characteristics.
Figure 3.3 Comparison of measured and modeled transfer characteristics at Vds =10 V.
28
3.2.3 Three Junction capacitors
Here the three junction capacitors CISS, COSS, CRSS are just modeled simply as
constant values and the parameter values are extracted from the capacitance measurement
results at a drain voltage is + 500V at 100 kHz. At this condition, as shown in Fig.2.27,
CISS is 1.30 nF, COSS is 155 pF and CRSS is 22.6 pF. A more accurate and complicated
capacitance model that varies with drain voltage will be proposed later.
3.2.4 Body Diode
The diode can be modeled as a power diode connected in anti-parallel with the
MOSF
. he model is built using the “ iode ool” in Saber and the device
characteristics (ISD-VSD) can be tuned visually to fit the measurement result [28-29]. In
the “diode ool”, the model can be characterized at three different temperatures and each
temperature has its own parameter set. Since we are characterize the device at room
temperature, so the temperature parameter tnom is set to be 27°C. The parameters need to
be extracted from diode I-V characteristics include: (1) rs: series resistance; (2) isl:
saturation current for low-level injection; (3) vtl: threshold voltage for low-level injection
(4) ish: saturation current for high-level injection (5) vth: threshold voltage for high-level
injection. After extracted reasonable values for all these five parameters, the optimizer in
diode tool can be used for fine tuning of parameters. The comparison of simulated and
measured result is shown in figure 3.4.
29
Figure 3.4 Body diode I-V measurement result (blue) and curve-fitting result (pink)
Besides, an analytical model has also been built for the body diode. The body diode
current/voltage characteristic is given by Eq. 5-7
S
=
S
=
S
=
SL
{e p (
SH
{e p (
) 1} , 0
S
) 1} , 0.
L
S
H
1
RS
Where
S
SL
S
5 . ,
S
0.
S
(5
.55
.55
(7
is saturation current for low level injection,
low level injection,
SH
(
L
is the emission coefficient for
is saturation current for high level injection,
coefficient for high level injection,
H
is the emission
is the series resistance. The comparison of
simulated result from the analytical model and measured result is shown in figure 3.5.
30
The extracted parameters values are as follows:
H =17.
SL =
.7
-1 A,
L =1.
17,
SH =0.00
, RS =0.0557 Ω
Figure 3.5 Body diode I-V measurement result (blue) and simulation result from
analytical model (red)
3.2.5 Other parameters
The internal gate resistance RGI and package stray inductance LG, LD, LS are
modeled using the characterization results. All the parameters for the SiC MOSFET
model are listed in Table 3.1.
31
A,
Parameter
MOS
VTH
λ
Junction Capacitors
CGD at VDS =500 V
CGS at VDS =500 V
CDS at VDS =500 V
Power Diode
rs
isl
vtl
ish
vth
Internal Gate Resistor
RGI
Package Stray Inductors
LG
LD
LS
Value
Unit
0.5006
5.86
0.04647
AV-2
V
V-1
13.2002p
1.27256
63.3855
pF
nF
pF
0.04457
1.669
Ω
A
V
A
V
0.55
Ω
9.23
5.93
7.52
nH
nH
nH
0.207
Table 3.1 SiC MOSFET model parameters
3.3 Saber Power MOSFET Tool
A more convenient way to develop an accurate SiC MOSFET model is to use the
Power MOSFET Tool in Saber. The Power MOSFET Tool provides support to generate
level-1 MOSFET models intended for use in power electronic circuits. These models are
well suited for examining switching transients and losses in power supplies. An optimizer
is also provided to help matching the model DC characteristics with experimental data.
The interface of the Power MOSFET Tool is displayed in Figure 3.6.
32
Figure 3.6 Saber Power MOSFET Tool interface
The information needed for the Power MOSFET Tool includes DC characteristics
(output and transfer characteristics), capacitance characteristics (input, output and reverse
transfer capacitance characteristics), body diode characteristics, internal gate resistance
and package stray inductances, all of which could be obtained from measurement results
described in chapter 2.
First, in DC characterization form, a set of parameters are given in Table 3.2 for a
specified device temperature.
33
Parameter
Tempj (°C)
Value
27
Vt (V)
vgs0(V),vds0(V),ids0(A)
5.88
12, 6,11.45
rds0(Ω)
0.25
rs(Ω)
rd(Ω)
rg(Ω)
Lambda (V-1)
0.0038
0.028
0.55
0.062
Description
Temperature at which the subsequent
parameters are specified
threshold voltage
Coordinates of a point on the id(vds0,vgs0)
surface located at the boundary between
quasi-linear and saturation regions.
Device resistance when drain bias is close to
zero and gate bias is equal to vgs0
Series resistance at the source terminal
Series resistance at the drain terminal
Series resistance at the gate terminal
Channel-length modulation parameter
Table 3.2 DC Model parameters
Figure 3.7 and 3.8 show the simulated and measured result of output and transfer
characteristics.
Figure 3.7 Simulated and measured output characteristics
34
Figure 3.8 Simulated and measured transfer characteristic
The capacitance characteristics form shows the standard measured capacitance
curves provided by most data sheets that three nonlinear capacitances are measured as a
function of drain bias: CRSS (= CGD), COSS (= CGD + CDS) and CISS (= CGD + CGS). In the
models produced by the tool, CGD and CDS are non-linear whereas CGS is assumed to be
constant, which is commonly verified by measured data. Table 3-3 shows the list of
capacitance model parameters extracted from C-V characteristics of the SiC MOSFET.
35
Parameter
crss0(nF)
crss1(nF)
crss2(nF)
coss0(nF)
coss1(nF)
coss2(nF)
ciss0(nF)
v1(V)
v2(V)
profile
Value
1.66
0.425
0.083
2.709
1.159
0.493
2.963
1.38
6.7
0.46
Description
maximum crss value
crss value for reference voltage v1
crss value for reference voltage v2
maximum coss value
coss value for reference voltage v1
coss value for reference voltage v2
maximum ciss value
first reference voltage
second reference voltage (v2>v1)
doping profile parameter (typical values range
between 0.3 and 0.6).
Table 3.3 Capacitance model parameters
The maximum CRSS value and COSS value are obtained when the drain bias is
negative value. During the capacitance characterization, VGS is set to be 0 V to block the
device channel for VDS dependency, VDS is swept from 0 V to 500 V. The relationship
between the capacitance characteristics can be obtained. CGS is hardly changed with the
variation of VDS since VDS does not govern the expansion of the depletion region across
the gate and source. In other word, CGS is a gate bias dependent parameter. CGD and CDS
decrease with the increase of VDS in accordance with the expansion of the depletion
region [30]. The measured and simulated C- VDS characteristics of the SiC MOSFET are
shown in Figure 3.9.
36
Figure 3.9 Simulated and measured C- VDS characteristics
Besides, the C-VDS characteristics of the SiC MOSFETs are modeled by using Eqs.
8-10. It can be expressed in the following compact form:
( ) (
)
( )
( )
(
)
( )
√
( )
(
Where
(
)
(
)
( ) is the gate-source zero-bias gate capacitance,
zero-bias capacitance,
drain oxide capacitance,
capacitance,
)
( ) is the gate-drain
( ) is the drain-source zero-bias capacitance,
is the gate-
is the drain depletion layer beneath the gate oxide
is the drain threshold voltage ,
is the built-in potential and M is the
grading coefficient. The comparison of simulated result from the analytical model and
measured result is shown in figure 3.10. The extracted parameters values are as follows:
37
( )
,
( )
,
( )
,
,
, M=0.47.
Figure 3.10 Simulated (analytical model) and measured C- VDS characteristics
The body diode is characterized with the Diode Characterization Tool which we
have discussed above. Figure 3.11 shows the simulated and measured body diode I-V
forward characteristics.
38
,
Figure 3.11 Simulated and measured body diode I-V forward characteristic
3.4 Conclusion
This chapter has presented two ways to build SiC MOSFET models that are suitable
for system-level simulations using the simulator “Saber”. In section 3.2, an analytical
model for SiC MOSFET has been developed and non-linear curve fitting has been
performed to extract the parameter values. Then the sub-circuit model is developed with
those extracted parameters. The sub-circuit model can be run in many commercial
simulators such as Pspice, Topspice, Psim, etc. besides Saber. On the other hand, the
built-in Power MOSFET Tool in saber provides a much convenient way to build the SiC
MOSFET which is good enough for switching transients analysis. A good agreement has
been successfully achieved between simulation and measurement results. At last, the
limitations of the model also have been discussed.
39
Chapter 4 Characterization and modeling of SiC MOSFET
switching behavior
4.1 Fundamental of SiC Power MOSFET Switching Characteristics
SiC power MOSFETs are usually used as switches in high-power circuits due to
their high breakdown voltage and fast switching capability [31-32]. Their switching
behavior is mainly affected by the three capacitances between the three device terminals,
namely gate-drain capacitance, gate-source capacitance, drain-source capacitance, due to
the charge and discharge phenomenon during the device turn-on and turn-off process. To
have a better understanding of the power MOSFET switching behavior, a basic inductive
load switching behavior test circuit is shown in Figure 4.1, followed by a brief
introduction of the power MOSFET turn-on and turn-off transient (Figure 4.2 and 4.3)
[33-35].
40
Figure 4.1 Schematic circuit diagram of a clamped inductive load test circuit for SiC
MOSFETs
Turn-on transient:
The turn-on transient process is illustrated in Figure 4.2. The initial condition for the turn
off process is:
( )
( )
( )
(1) 0-t1 time period
When the gate bias VGS increases, it begins to charge the capacitors of the SiC
MOSFET. Before the gate voltage exceeds (VGS < VTH) the threshold voltage, no drain
current flows through the SiC MOSFET device, which means ID will remain zero and the
device drain voltage VD also keeps its initially value, which is equal to the drain bias
voltage VDS. Since the gate drain capacitance CGD varies with the applied drain voltage in
41
accordance with the thickness of depleted region, it remains constant at this situation due
to the constant VDS. The gate voltage reaches the threshold voltage at time t1 given by:
(
)
( )
( )
( )
(2) t1-t2 time period:
When the gate bias is higher than the threshold voltage, drain current starts to flow
through the SiC MOSFET device and the current value increases. At this period, the drain
voltage still remains constant since the freewheeling diode cannot be used to provide any
voltage until all the load current is transferred to the SiC MOSFET device. As a result,
the gate drain capacitance CGD still remains constant. The drain current keeps increasing
until it reaches the same value as the load current IL. At this moment, the time t2 can be
expressed as:
√
where
is the inversion layer mobility,
channel width and
is the gate oxide capacitance,
is channel length.The gate voltage at time t2 called as plateau
voltage and can be expressed as:
( )
is
√
( )
42
( )
(3) t2-t3 period:
At time t2, the entire load current IL has transferred from the diode to the SiC
MOSFET and the diode begin to support voltage, which means the drain voltage VD will
begin to reduce until it reaches the on state voltage Von:
( )
( )
( )
(4) t3-t4 time period:
During this time period, the gate voltage keeps increasing until it reaches the gate
bias voltage. As the gate bias increases, at the same drain current level, the on-state
resistance will be reduced which results in a small reduction of the drain voltage during
this period:
( )
( )
( )
Turn off transient:
The turn-off transient process is illustrated in Figure 4.3. The initial condition for the turn
off process is:
( )
( )
43
( )
(1) 0-t4 time period:
As the gate bias decreases, neither drain voltage nor drain current will change until
the gate voltage reaches the plateau voltage VGP, which is the voltage allows the SiC
MOSFET to operates at its saturation current level equal to the load current level. The
time t4 is given by:
[
]
( )
( )
( )
(2) t4-t5 time period:
During t4-t5 time period, the drain voltage begins to increase while the drain current
is still remains constant because the current is not able to be transferred to the
freewheeling diode until the drain voltage VD exceeds the drain bias and makes the diode
working at the forward bias condition. In this case t5 can be expressed as
( )
( )
( )
(3) t5-t6
44
At this time period, the load current begins to transfer from the SiC MOSFET to the
freewheeling diode, resulting in a current drop for the device. The current flowing
through the gate resistance discharges both the gate-to-drain and gate-to-source
capacitance, leading to an quickly fall in gate voltage.
(4) beyond t6
At time t6, the gate voltage drops to the threshold and beyond that point, the drain
current turns to zero and the drain voltage equals to the drain bias voltage.
(
)
( )
( )
( )
Figure 4.2 SiC MOSFET turn-on transient process
Figure 4.3 SiC MOSFET turn-off
transient process
45
4.2 Double Pulse Tester (DPT) for Dynamic Switching Performance
Characterization
To evaluate the dynamic characteristics of a SiC MOSFET, a double pulse tester
(DPT) is built to obtain the switching waveforms and data. In this work, an inductor is
used for double pulse tests since the system load is inductive for a majority part of power
electronics and power systems applications. The basic operation principle of the DPT is
similar to that of the inductive load test circuit we introduced in section 4.1. Figures 4.4
to 4.6 show the schematic and board layout of the double pulse tester.
For dynamic tests, two pulses are applied to the gate of the SiC MOSFET with very
low frequency, which is usually below 10 Hz to help the device under test (DUT) avoid
deviation caused by self-heating. During the first pulse period, appropriate DC bias and
pulse width is chosen to charge the inductor to a certain load current. Then turn-off of the
first pulse can help to obtain the turn-off characteristics of the SiC MOSFET under the
desired current and voltage level. The turn-off time, propagation delay of DUT can be
derived from the measured Vgs, Vds and Id. Besides, data exported from oscilloscope are
used to accurately calculate the turn-off loss according to its definition. After the first
pulse, the current is blocked by the MOSFET so that it circulates through a parallel SiC
diode. Thus, the power loss is induced by the forward voltage of the diode. Since the
interval between the first and second pulse is short enough, the current during this period
can be considered to be constant.
The second pulse is utilized for the turn on characterization of the SiC MOSFET.
Since the current value is determined by the first charging pulse, the SiC MOSFET is
46
turned on under the same current and voltage bias level as the first pulse. Similarly to the
turn-off procedure, the turn-on time, turn on delay, turn on switching loss can be
evaluated. Since the main purpose to add a second pulse is to measure the turn on
characteristics, the pulse width is always set to be very short.
Moreover, since the gate resistance affects the charging speed of the input
capacitance, three different gate resistances are added to observe the change of the
switching transients. In our work, the switching characterization is performed under 100
V drain bias, 10 A inductive load, -5V/20V gate voltage with three different gate
resistance value RG = 2.7 Ω, RG = 5 Ω and RG = 10 Ω.
Figure 4.4 Double pulse tester switching characterization setup.
Figure 4.5 SiC MOSFET double pulse tester circuit board top layer
47
Figure 4.6 SiC MOSFET double pulse tester circuit board bottom layer
4.3 Switching characteristics modeling using Saber
To verify the two SiC MOSFET models we have built, the same double pulse tester
circuit is simulated in Saber [36]. In the simulation, the gate drive circuit is replaced by
an ideal voltage source to generate the two pulses. A CREE SiC Schottky diode, which is
characterized and simulated using the saber “diode ool”, works as the freewheeling
diode at this work. A comparison of experimental and the simulated result of SiC
Schottky diode I-V and C-V characteristics are shown in Figure 4.7 and 4.8.
Figure 4.7 Diode Forward I-V curve
Figure 4.8 Diode junction capacitance
48
An inductive load test circuit for the switching characterization built in Saber is
shown in Figure 4.9. Comparisons of experimental switching waveforms and the
simulated waveforms based on the device model built in section 3.2 are displayed in
Figure 4.10-4.15.
Figure 4.9 Schematic circuit digram of a clamped inductive load test circuit for SiC
MOSFET
49
Figure 4.10 Experimental and simulated waveforms. Turn-on process at Rg = 2.7 Ω
Figure 4.11 Experimental and simulated waveforms. Turn-off process at Rg = 2.7 Ω
50
Figure 4.12 Experimental and simulated waveforms. Turn-on process at Rg = 5 Ω
Figure 4.13 Experimental and simulated waveforms. Turn-off process at Rg = 5 Ω
51
Figure 4.14 Experimental and simulated waveforms. Turn-on process at Rg = 10 Ω
Figure 4.15 Experimental and simulated waveforms. Turn-off process at Rg = 10 Ω
The measured and simulated switching characteristics based on the device model
built in section 3.3 are shown in figure 4.16-4.21.
52
Figure 4.16 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg = 2.7 Ω
Figure 4.17 Measured and simulated transient response in the turn-off process with gate
drive resistance of Rg = 2.7 Ω
53
Figure 4.18 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg = 5 Ω
Figure 4.19 Measured and simulated transient response in the turn-off process with gate
drive resistance of Rg = 5 Ω
54
Figure 4.20 Measured and simulated transient response in the turn-on process with gate
drive resistance of Rg =10 Ω
Figure 4.21 Measured and simulated transient response in the turn-off process with gate
drive resistance of Rg = 10 Ω
The turn-on time Ton is defined as the time from Id reaching 10% of the steady-state
current to Vds falling to 10% of the DC bus voltage and turn-off time Toff is defined as
Vds rising to 10% of the bus voltage to Id falling to 10% of the load current. As we can
55
seen in both cases, when Rg = 2.7ohm, Ton and Toff is around 10 ns; when Rg =5 ohm,
Ton and Toff is around 15 ns; when Rg = 10 ohm, Ton and Toff is around 20 ns.
4.4 Conclusion and Discussion
This chapter has introduced the basic concept of power MOSFET switching
characterization. A double-pulse tester was built to perform the switching behavior. By
comparing the simulation with the experimental waveforms, the effectiveness of the
device models has been verified.
Although, the double pulse test provides a good solution for evaluating switching
dynamic characteristics, there’s still accuracy problem related to it:(1) For the circuit
main loop, because of the high dv/dt and di/dt, the current overshoot can be high. As a
result, the energy stored in the stray inductance will have oscillation with the output
capacitor of the MOSFET. (2) For the gate charge loop, the stray inductance will also
slow down the charging time or even cause the mis-trigger of the MOSFET if it causes
too large oscillation on gate charge signal. (3) For the measurement side, the parasitic
capacitance and the stray inductance in the current shunt will affect the accuracy of
measurement on Vds and Id. This is because under high frequency resonance in the
circuit, even very limited parasitic parameters will induce relatively high impedance,
which can affect the accuracy obviously.
Therefore, the double pulse tester design has very high requirement for the PCB
layout and measurement even though the circuit is simple. In this design, both the gate
charge loop and the main power loop lengths have been minimized for stray inductance
56
reduction. Thus, in the switching waveforms, the minimized switching overshoot and
oscillation is realized. Also, to guarantee the measurement accuracy, a self-made current
shunt is tested to perform a better switching current waveform while Tektronix TPP0850
voltage probe provides small parasitic capacitance and bandwidth as high as 800 MHz. In
this case, the hardware can output optimized switching characteristics and the
measurement error can be reduced to an acceptable range.
57
Chapter 5 Concluding Remark
Silicon carbide power MOSFETs have enormous potential for replacing silicon
based devices in high power, high temperature applications. The advantages of SiC over
Si lie in its material properties such as high bandgap, high thermal conductivity and very
high breakdown field. These properties make SiC MOS devices ideal for high power
electronics applications.
In this thesis, we studied the static and switching characteristics of the SiC
MOSFET. Characterization methods and procedures, which are very generic and can also
be applied to the study of SiC JFETs, have been discussed in detail. An Agilent power
curve tracer, which is designed for the power devices characterization, has been
introduced to provide a much easier, faster and accurate way to perform characterization.
Based on the characterization results, two device sub-circuit models have been built and
verified by comparing simulation results with experimental results. The limitations of the
model have been discussed as well.
58
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