A Two-Path Bandpass Σ∆ Modulator for Digital IF
Extraction at 20 MHz*
Adrian K. Ong and Bruce A. Wooley
Center for Integrated Systems
Stanford University
Stanford, CA 94305
Correspondence Address (5/19/99):
Adrian K. Ong
Bell Laboratories, Lucent Technologies
Room 2d-341
Murray Hill, NJ 07940
Phone: (908) 582-2560
FAX: (908) 582-6000
Email: adriano@lucent.com
Abstract — Oversampled bandpass A/D converters based on sigma-delta (Σ∆) modulation
can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals
that arise in radios and cellular systems. This paper proposes a two-path architecture for a
fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high
sampling speeds than conventional implementations based on the use of switched-capacitor
biquadratic filters. An experimental prototype employing the two-path topology has been
integrated in a 0.6-µm, single-poly, triple-metal CMOS technology with capacitors
synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz
digitize a 200 kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while
suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the
mixing of spurious tones at dc and fs /2 with the input appears to degrade the performance
of the modulator; out-of-band sinusoidal dither is shown to be an effective means of
avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3-V
supply.
Index Terms — Analog-digital conversion, sigma-delta modulation, N-path filters,
resonator filters, switched-capacitor circuits, mixed analog-digital integrated circuits,
sampled data circuits, radio receivers, IF systems.
*
This research was supported in part by the Semiconductor Research Corporation under Contract 95-DJ-703,
and by the Hewlett-Packard Corporation.
1
A Two-Path Bandpass Σ∆ Modulator for Digital IF
Extraction at 20 MHz*
Adrian K. Ong and Bruce A. Wooley
Center for Integrated Systems
Stanford University
Stanford, CA 94305
Correspondence Address:
Adrian K. Ong
Center for Integrated Systems, #072
Stanford University
Stanford, California 94305-4070
Phone: (415) 725-4542
FAX: (415) 725-3383
Email: alois@mushroom.Stanford.EDU
I. INTRODUCTION
The recent explosion of interest in wireless personal communications systems is motivating the
development of fully integrated radio receivers with particular attention directed towards reducing
power dissipation and ensuring flexibility in the system architecture. By increasing the level of
integration in the signal path, a receiver can be realized with a more compact form factor at
reduced cost and with greater reliability. In addition, higher levels of integration reduce the need
for the constituent analog and mixed-signal circuit blocks to drive large pad and package parasitic
capacitances, thereby conserving power. Aggressive utilization of VLSI technology also enables
the combined integration of a bandpass or baseband analog-to-digital (A/D) converter along with
the traditional front-end receiver building blocks. In this manner, the back-end signal processing
can be shifted from the analog domain into the digital domain. Digital processing of the baseband
signal is rapidly becoming a necessity because emerging standards such as IS-54, IS-95 CDMA,
and GSM encompass bandwidth-efficient modulation schemes, as well as compression, error
correction, and possibly spread spectrum techniques, that require substantial digital processing
[1], [2].
To meet the anticipated requirements imposed by emerging standards, the next generation of
portable, agile, and reprogrammable radio receivers is evolving towards an integrated digital
*
This research was supported in part by the Semiconductor Research Corporation under Contract 95-DJ-703,
and by the Hewlett-Packard Corporation.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 2
solution in which the RF is translated down to a low intermediate frequency (IF) or to baseband
before being digitized and processed. In this type of architecture, the processor can control
narrowband channel characteristics such as bandwidth and the rejection of adjacent interferers by
means of numerical parameters. Also, the radio will be able to dynamically adapt as the
characteristics of the wireless channel itself change as a function of time. These advantages open
the possibility of implementing software-controlled radios that can support multiple standards and
are suitable for use in widely varying propagation environments.
Digitization of the signal in a superheterodyne receiver is typically accomplished with one of
the two methods diagrammed in Fig. 1(a) and (b). The bandpass signal can either be converted
into the digital domain at the IF location, or the digitization can be delayed until the signal has
been separated into its lowpass in-phase, I, and quadrature, Q, components [3]. It is also possible
to digitize the signal directly at the front-end of the receiver. However, this approach is rarely
viable because of excessive power dissipation and the limited dynamic range that can be achieved.
Conversion to digital at the IF location confers several advantages. First, the I and Q components
of the signal will be separated in the digital domain rather than in the analog domain.
Consequently, the quality of the downconversion will not be compromised by analog
imperfections such as mismatch between the I and Q paths or the need to implement precise
analog quadrature mixers. Second, by converting to digital at the IF location, the problems of low
frequency (1/f ) noise and dc offset are avoided. However, as analog signal processing stages are
eliminated, and the A/D conversion is moved away from the baseband, the converter must sample
at a higher rate, and the signal that must be digitized has a larger dynamic range. The challenge of
building a converter with a sufficiently high sampling speed and dynamic range for wireless
applications while preserving low power operation is considerable.
This work explores the possibility of digitizing an IF signal with an oversampled bandpass
sigma-delta (Σ∆) modulator. Oversampled bandpass converters can be used to robustly digitize
the types of narrowband IF signals that arise in radios and cellular systems [4]-[9]. However, in
many such converters, the sampling frequency of the modulator is often restricted to be exactly
four times the passband frequency. By centering the passband at one-quarter of the sampling
frequency, fs /4, comparatively simple structures can be used to implement the modulator.
Moreover, the bandpass topology can easily be derived from lowpass prototypes with a simple
mathematical transformation. Also, I and Q demodulation is especially simple when the passband
is centered at fs /4 [9]. The tradeoff for this architectural choice is that the dynamic range of the
modulator becomes increasingly constrained by circuit nonidealities at the high sampling rates
needed to digitize signals at IF locations above 10 MHz. Consequently, for applications requiring
a dynamic range of 70 dB or greater, the signal passband in previously reported work [5], [6] has
been located at a relatively low IF (under 5 MHz). This limits the utility of bandpass modulators
for IF digitization because in receivers that handle RF carriers between 1 and 2 GHz, a second IF
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 3
location between 10 and 20 MHz is conventionally chosen to meet the competing requirements
for image rejection and channel selectivity [10]. Although there can be considerable latitude in
determining the exact location of the IF, the choice of location may not be under the control of the
A/D converter designer. As a result, the modulator may be required to operate at sampling speeds
up to 80 MHz, significantly stretching the capability of state-of-the-art switched-capacitor
circuits.
This paper introduces a two-path, switched-capacitor architecture for bandpass Σ∆ modulation
that relaxes the stringent requirements imposed upon the analog circuits as the sampling
frequency of the modulator is increased. The experimental prototype described herein can operate
with an effective sampling frequency as high as 80 MHz, digitizing narrowband signals centered
at one-quarter of the sampling frequency, fs /4. The performance impairments at high sampling
rates that motivated the use of a two-path architecture are identified in Section II, and aspects of
N-path filtering as applied to bandpass modulator design are discussed in Section III. The design
of the experimental modulator is presented in Section IV, followed by a discussion of the
measured results in Section V. Tones in the noise spectrum are shown to cause substantial
degradation at low input signal levels, and dithering is identified as a solution to this problem in
the experimental modulator.
II. HIGH FREQUENCY PERFORMANCE IMPAIRMENTS
The architecture of the experimental discrete-time, fourth-order bandpass modulator is shown
in Fig. 2. This topology is derived from the well-known second-order, noise-differencing, lowpass
prototype by substituting bandpass resonators for lowpass integrators [5], [9]. In the z-domain, the
lowpass-to-bandpass transformation is realized by replacing z–1 with –z–2. By this means, the
zeros of the noise transfer function are shifted from dc to fs /4. Also, similar to antecedent lowpass
and bandpass modulators [9], [11], the system gains in the modulator of Fig. 2 have been scaled in
order to restrict the signal excursions at internal nodes, thereby maximizing the dynamic range of
the modulator.
If the quantizer in Fig. 2 is approximated as a gain, GQ, with an additive, uncorrelated noise
source, E(z), the output of the modulator is described in the z-domain by
– 0.2G Q ⋅ z –4 X ( z ) + ( 1 + z –2 ) 2 E ( z )
Y ( z ) = ------------------------------------------------------------------------------------------------- .
1 + ( 2 – 0.5G Q ) ⋅ z –2 + ( 1 – 0.3G Q ) ⋅ z –4
(1)
Extensive behavioral simulations of the experimental modulator using MIDAS [12] indicate that
the power of the quantization noise in the signal passband is accurately estimated from (1) by
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 4
setting the gain of the quantizer, GQ, to 5. The transfer function of the modulator can then be
approximated near fs /4 with the simplified expression
Y ( z ) ≈ – z –4 X ( z ) + ( 1 + z –2 ) 2 E ( z ) .
(2)
Thus, the output of the modulator consists of the input, X(z), delayed by four sample periods, plus
a bandstop shaping of the additive quantizer noise, E(z). Note that this model ignores the
correlation between the quantization noise and the input that is inherent in any oversampling
modulator employing a single one-bit quantizer. This correlation results in spurious noise tones.
At high sampling speeds, the performance of the fourth-order modulator in Fig. 2 is limited
primarily by the nonideal behavior of the bandpass resonators. The ideal resonator has a
biquadratic transfer function of
z –2
H ( z ) = G ⋅ --------------1 + z –2
(3)
where G is the gain of the resonator. As illustrated in Fig. 3, the magnitude response of (3) peaks
at fs /4. Nonidealities in the operational amplifiers used to implement the resonator contribute
potentially significant errors to (3). In the presence of finite dc gain and limited amplifier
bandwidth, the resonator transfer function takes on the form
z –2
H ( z ) = G ⋅ ( 1 – δ ) ⋅ ------------------------------------------------1 + εz –1 + ( 1 – γ )z –2
(4)
where δ, ε, and γ model small deviations from the ideal transfer function. The factors δ, ε, and γ
limit the height of the peak in the magnitude response and shift the peak away from fs /4.
The impact of limitations in the operational amplifier is especially severe if the biquadratic
resonator transfer function is implemented using conventional switched-capacitor structures, such
as the undamped, two-integrator loop illustrated in Fig. 4(a) and (b) [8]. In this type of topology,
the transfer function is synthesized with two operational amplifiers enclosed within a single
feedback loop. As a consequence, each output sample of the resonator includes errors introduced
by both amplifiers; the errors combine in an additive manner. This accumulation of error can
result in large deviations from the ideal response of (3) predicted by δ, ε, and γ. In particular, as
the sampling rate of the two-integrator loop resonator increases, δ, ε, and γ, grow in magnitude,
compromising the ability of a modulator implemented using such resonators to attenuate the
inband noise centered at fs /4.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 5
The effect of nonideal operational amplifiers on the behavior of switched-capacitor circuits has
been analyzed extensively [14], [15], and these analyses can be applied toward understanding the
behavior of two-integrator loop resonators at high sampling rates. Because a switched-capacitor
integrator of the type depicted in Fig. 5 is the key constituent of a two-integrator loop resonator,
degradation in the performance of such a resonator can be studied by considering how
nonidealities in the integrators introduce errors into its transfer function, (3). In the analysis that
follows, it is demonstrated that incomplete amplifier settling limits the performance of a twointegrator loop resonator to a greater extent than finite dc gain. For simplicity, the errors
contributed by finite operational amplifier gain are considered separately from those errors arising
from limited amplifier bandwidth.
A. Errors Owing to Finite DC Operational Amplifier Gain
In the presence of finite operational amplifier gain, A, the switched-capacitor integrator
implementation in Fig. 5 has the transfer function
CS
z –1 / 2
H ( z ) = ------ ⋅ ( 1 – m 1 ) ⋅ ----------------------------------CI
1 – ( 1 – p 1 )z –1
(5)
where the terms m1 and p1 model perturbations in the gain and pole locations of the integrator,
respectively, and are given by
C
1
m 1 = --- 1 + -----S- 
A
CI 
(6)
and
1 C
---  -----S- 
ACI 
- .
p 1 = ---------------------------------CS
1
1 + --- 1 + -----A
CI 
(7)
The effect of finite amplifier gain on the resonator in Fig. 4(b) is assessed by modeling the two,
nominally identical, switched-capacitor integrators with (5) and independent error terms m1, p1,
m2, and p2. The system gains of both integrators, CS /CI, are chosen to be 1. With this
representation, the nonideal transfer function of the resonator is approximated by
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 6
z –2
H ( z ) = G ⋅ ( 1 – m 1 – m 2 ) ⋅ --------------------------------------------------------------------------------------------------------------------1 + ( p 1 + p 2 – 2m 1 – 2m 2 )z –1 + ( 1 – p 1 – p 2 )z –2
(8)
when second-order terms are neglected. When the perturbations are small, namely m1, p1, m2, and
p2 <<1, the fractional deviation in the center frequency, fo, of the resonator is approximately
∆f
p 1 + p 2 – 2m 1 – 2m 2
--------o- ≈ ------------------------------------------------- .
fo
π
(9)
Thus, if the switched-capacitor integrators in Fig. 4(b) are implemented with operational
amplifiers having a nominal dc gain of 60 dB, it follows from (8) and (9) that the magnitude peak
of the resonator transfer function shifts by only 0.2% of fo, or 40 kHz, when its ideal center
frequency is 20 MHz. Because of a fortuitous partial cancellation in (9) between perturbation
terms p1, p2 and m1, m2, the deviation in fo is relatively small, even with a modest amplifier gain
of only 60 dB. Within the context of a bandpass modulator, this shift in the peak of the magnitude
response of the resonator results in a corresponding shift in the minimum of the noise transfer
function away from fs /4.
The increase in inband noise in the fourth-order modulator of Fig. 2 that results from finite
amplifier gain has been estimated with behavioral simulations that model the constituent
resonators with (8). Resonator perturbation terms, m1, p1 and m2, p2, were determined by
assuming an amplifier gain of 60 dB. In a 200 kHz passband centered at fs /4, the simulations show
that the loss in dynamic range is approximately 5 dB in a modulator with performance that is
limited solely by quantization noise.
In an efficient practical implementation of the modulator in Fig. 2, the performance should
generally be limited by circuit, rather than quantization, noise. In such a case, the noise floor
within the signal passband is determined by noise introduced at the input to the modulator, since
this noise is not attenuated by noiseshaping. Sources of this unshaped noise include thermal noise
in the first resonator, as well as kT/C noise from the input sampling network. When the shaped
quantization noise lies well below the noise floor within the passband, small shifts in the exact
minimum of the noise transfer function have a negligible influence on the total inband noise. This
is not true, however, if the fractional shift in fo becomes large enough to begin shifting the large
out-of-band quantization noise into the signal passband.
The above analysis is limited by the assumption that the response of the amplifier is linear
across its entire output range. Under this assumption, a dc gain of only 60 dB was shown to
suppress any appreciable loss in the dynamic range. In practice, however, higher dc gains may be
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 7
needed to suppress harmonic distortion in the integrators that can result from nonlinearity in the
amplifier transfer characteristic.
B. Errors Owing to Finite Operational Amplifier Bandwidth
In the presence of limited operational amplifier bandwidth, the switched-capacitor integrator of
Fig. 5 suffers from incomplete settling. If the integrator is assumed to settle linearly with a singlepole response, incomplete settling only manifests itself as an integrator gain error [11]. In this
case, the transfer function of the integrator is
CS
z –1 / 2
H ( z ) = ------ ⋅ ( 1 – g 1 ) ⋅ --------------CI
1 – z –1
(10)
where gain error term, g1, is
g1 = e
–T ⁄ τ
,
(11)
T is the time allotted for settling, and τ is the closed-loop time constant of the integrator. If the
resonator is implemented using two-phase, non-overlapping clocks with 50% duty cycles, T, is
slightly less than Ts /2, where 1/Ts = fs, the sampling frequency. The closed-loop time constant of
the integrator, τ, is approximately
CS + CI + CP
1
τ ≈ ------------ ⋅ -------------------------------CI
2π f u
(12)
where fu is the unity-gain frequency of the operational amplifier and CP is the parasitic
capacitance at the input to the operational amplifier. As the sampling rate is increased, the
available settling time, T, decreases, and the gain error in (10) becomes increasingly large.
As a caveat, it should be noted that, in practice, settling in switched-capacitor circuits is rarely
governed by a strictly linear, single-pole response. Rather, the settling process usually includes a
signal-dependent slewing component and is influenced by nondominant poles of the amplifier
[16], [17], as well as finite switch resistances in the switched-capacitor network. In such cases,
errors in a switched-capacitor integrator due to incomplete settling are understated by (10) and
(11), with nonlinearities in the settling process not even reflected in these expressions. For
tractability, only linear settling is considered in this analysis.
The effect of incomplete, but linear, integrator settling upon the resonator in Fig. 4(b) can be
assessed by modeling the two switched-capacitor integrators with (10) and independent gain error
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 8
parameters g1 and g2. When second-order terms are neglected, the perturbed resonator transfer
function is found to be
z –2
-.
H ( z ) = G ⋅ ( 1 – g 1 – g 2 ) ⋅ ---------------------------------------------------------1 – ( 2g 1 + 2g 2 )z –1 + z –2
(13)
From this result, it follows that the fractional shift in resonator center frequency, fo, due to
incomplete settling is approximately
∆fo
2g 1 + 2g 2
--------- ≈ – -----------------------.
fo
π
(14)
The unfortunate implication of (11), (13), and (14) is that as the sampling frequency increases and
the time allotted for settling, T, decreases, the fractional shift in fo becomes larger and the
minimum of the modulator noise transfer function deviates by an increasing amount from fs /4,
eventually moving out of the signal passband all together.
As an example, if the modulator shown in Fig. 2 operates at a sampling rate of 80 MHz, from
two-phase, non-overlapping clocks, less than 6 ns during each clock phase is available for settling.
If it is further assumed that a high bandwidth amplifier design results in a closed-loop time
constant, τ, of approximately 1.3 ns, the settling time is limited to roughly 4τ. From (13) and (14),
it then follows that the center frequency of the resonators will shift by –470 kHz. Under these
assumptions, the penalty in dynamic range can be assessed in MIDAS by modeling the
constituent resonators with (13). Simulations show that the dynamic range in a 200 kHz passband
centered at fs /4 is reduced by 30 dB if the modulator is limited by quantization noise.
As discussed in the previous subsection, the loss in dynamic range due to resonator
degradation will be less severe if a modulator is limited by thermal, rather than quantization,
noise. However, as is evident from (11) and (14), the shift in the minimum of the noise transfer
function from fs /4 increases with increasing sampling rate, in contrast to the shift that results from
finite amplifier gain. Consequently, at the high sampling rates needed to digitize signals at
conventional radio IF’s, the minimum of the noise transfer function may shift by an amount large
enough to move high levels of nominally out-of-band quantization noise into the passband.
III. N-PATH DESIGN ISSUES
Degradation in the resonators of a bandpass oversampling modulator that results from nonideal
operational amplifier performance can be attacked at the architectural level by implementing the
resonators with an N-path filter structure [18]-[23]. In the block diagram of a generalized N-path
filter shown in Fig. 6, the N filters comprising the structure, H1(zp), H2(zp),...,HN(zp), are
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 9
nominally identical. From the clocking diagram in Fig. 6, it is seen that the paths are clocked in an
interleaved fashion and that the sampling rate of each path filter is reduced by a factor of N
relative to the effective throughput rate of the overall N-path structure. Thus, the constituent
circuits of the individual path filters have settling requirements that are relaxed by a factor of N
with respect to the requirements imposed by a direct single-path implementation of the same
transfer function.
If the paths in the N-path filter of Fig. 6 are assumed to match perfectly, such that H1(zp) =
H2(zp) = ... = HN(zp) = H(zp), then the z-domain transfer function of the structure is
Y (z)
----------- = H ( z p )
X (z)
,
(15)
z p = zN
where H(zp) denotes the transfer function of each identical path filter [24]. In this expression, zp
corresponds to the z variable of a single path, and zp–1 is interpreted as a single delay with respect
to the sampling rate of a single path. z–1 represents a single delay with respect to the effective
throughput rate of the N-path filter, as implied by the relationship zp =zN.
Because the desired resonator transfer function, (3), can be expressed as a function of zp in the
following manner,
–1
zp
z –2
---------------H ( z ) = G ⋅ --------------=
G
⋅
1 + z –2
1 + z –p1
,
(16)
z p = z2
the bandpass resonator can be naturally partitioned into a two-path structure consisting of two
nominally identical highpass filters, as illustrated in Fig. 7. In this structure, the constituent
highpass path filters are clocked at one-half of the overall resonator output rate, so the demand on
the amplifier settling is relaxed by a factor of two. It is also important to note that the highpass
transfer function,
z –p1
,
H ( z p ) = G ⋅ ---------------1 + z –p1
(17)
can be implemented as a switched-capacitor filter with only one operational amplifier. Moreover,
there is no interaction between this amplifier and its counterpart in the other path. Consequently,
each resonator output sample will include errors due to finite dc gain and incomplete settling from
only one amplifier, rather than two. The exact nature of the errors arising from amplifier
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 10
limitations depends upon the particular switched-capacitor topology chosen to implement the
highpass transfer function of (17) and is discussed in Section IV.
In the two-path resonator of Fig. 7, fixed-pattern noise arising from clock feedthrough, offset,
and other signal-independent errors manifests itself as tones at dc and at multiples of the path
sampling frequency, fs /2, where fs is the sampling frequency of the resonator [24]. However,
because the magnitude peak of the resonator is centered at fs /4, these tones can virtually be
ignored because they lie far removed from the frequency band of interest at fs /4.
Gain and phase mismatch between the signal transfer functions in the two paths of Fig. 7
presents a more serious problem than fixed-pattern noise because such mismatch compromises
the suppression of mirror images of the desired signal that appear in the passband [24]. General
expressions describing incomplete image suppression have been derived for the related case of
asymmetry between A/D converters employed in a time-interleaved array of converters [25]-[27].
A similar analysis can be applied to the two-path resonator. If the transfer functions of the two
paths in Fig. 7 are denoted by H1(zp) and H2(zp), where zp=z2 for this two-path structure, the
output of the resonator can be expressed in the z-domain as
1
1
2
2
2
Y ( z ) = --- ( H 1 ( z 2 ) + H 2 ( z ) ) ⋅ X ( z ) + --- ( H 1 ( z ) – H 2 ( z ) ) ⋅ X ( – z ) .
2
2
(18)
If z=exp(j2πfTs) is substituted into (18), the spectrum of Y(z) is found to be
Y (e
j2πf T s
j2πf 2T s
j2πf 2T s
j2πf T s
1
) + H 2(e
)) ⋅ X (e
)+
) = --- ( H 1 ( e
2
j2πf 2T s
j2πf 2T s
j2π ( f – f s ⁄ 2 )T s
1
--- ( H 1 ( e
) – H 2(e
)) ⋅ X (e
)
2
(19)
This equation indicates that the resonator output consists of a desired response that is the average
of H1 and H2, together with a spurious image response that depends entirely upon the difference
between H1 and H2. If the gains of H1 and H2 are mismatched by 1%, (19) predicts that the
undesired image in the output of the resonator will be suppressed by approximately 40 dB.
Because of gain and phase mismatch inherent in both resonators, the output of a modulator
implemented using two-path resonators will contain an undesired image of the input signal at a
mirror location centered around fs /4, as illustrated in Fig. 8. This image lies within the signal
passband so it cannot be suppressed by filtering. Furthermore, for a given level of matching within
the modulator, the degree of mirror signal suppression is likely to be worse than that predicted by
(19) because both resonators undermine the suppression. Also, (19) does not account for other
factors that limit the mirror signal suppression, such as systematic errors in the path sampling
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 11
times and mismatched transistor switch networks in the path filters. Fortunately, because the
mirror image is merely a scaled version of the desired signal, as opposed to being an unrelated and
possibly much larger signal, only 25 dB of image suppression is considered adequate for many
applications [28].
The incomplete image suppression caused by path mismatch is analogous to the unwanted
image that is introduced by phase and gain errors during conventional analog I and Q
demodulation [29]. If the LO signals are balanced in amplitude but differ in phase by 90 + φ
degrees, it can be shown that rejection of the undesired image is given by
π φ 2
IR =  --------- ⋅ ---  .
 180 2 
(20)
Without special trimming or analog tuning techniques, it is difficult to reduce the phase error
between the LO signals significantly below 1° [30]. Therefore, assuming a phase error of 1°, the
unwanted image signal will be suppressed by approximately 40 dB, which is comparable to what
can be achieved by relying on path matching in the proposed two-path approach.
IV. MODULATOR IMPLEMENTATION
An experimental prototype of a fourth-order bandpass modulator shown in Fig. 2 has been
designed in a 0.6-µm, single-poly, triple-metal CMOS technology using a two-path architecture.
The goal of this design was to implement a modulator with an effective sampling frequency as
high as 80 MHz and a dynamic range exceeding 70 dB for a 200 kHz passband centered at fs /4. At
a sampling frequency of 80 MHz, the fourth-order modulator digitizes a signal passband of 200
kHz centered at 20 MHz with an oversampling ratio of 200. For this oversampling ratio, the
fourth-order architecture theoretically suppresses inband quantization noise by 95 dB with respect
to the full-scale input signal level. Because the quantization noise is attenuated by a large margin
compared to the targeted performance goals, it can virtually be disregarded. The modulator is
designed to be limited by circuit noise and nonidealities.
Fig. 9(a) is a block diagram of the experimental bandpass modulator. The modulator consists
of two resonators employing the two-path topology described in Section III, followed by a
comparator that serves as the 1-b quantizer and a two-level (1-b) D/A converter. The modulator is
controlled by a two-phase, nonoverlapping clock. The clocking diagram in Fig. 9(a) shows that
during Φ1, the outputs of one set of highpass path filters are sampled, while on Φ2, the outputs of
their counterparts are sampled. The quantizer is clocked on both Φ1 and Φ2; thus, the sampling
rate for the overall modulator is twice that of each path filter.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 12
In a switched-capacitor implementation of Fig. 9(a), the summation of the resonator input
signal with the quantizer feedback can be merged into the constituent path filters of each
resonator. Upon redrawing the block diagram to reflect this fact, Fig. 9(b) shows that the
experimental bandpass modulator is essentially comprised of two independent, interleaved
highpass modulators that are clocked 180° out of phase with each other. Fig. 9(b) also indicates
that the single 1-b quantizer in Fig. 9(a) has been partitioned into two independent 1-b quantizers.
If the offset and hysteresis in the two quantizers are identical, then the output from the modulator
in Fig. 9(b) is identical to the case where only a single quantizer is used. Although it is not
necessary to partition the quantizer in this manner, the use of separate quantizers allows for a
more modular design and simpler layout. Two independent quantizers were used in the
experimental prototype. To the extent that the quantizers are not perfectly matched, there will be
an equivalent gain and phase error between the transfer functions of the two independent paths.
Consequently, the mirror image of the input signal will not be completely suppressed. However,
this effect is likely to be small in comparison with mismatch in the resonators because errors
introduced at the quantizer inputs are attenuated by both noiseshaping and oversampling. In
general, the performance of 1-bit bandpass and lowpass oversampling modulators is relatively
insensitive to offset and hysteresis in the quantizer [11], [31]. It is important to note that the total
quantization noise power in the modulator of Fig. 9(b) is not doubled by the presence of two
quantizers because the quantizers are clocked on alternate clock cycles and the outputs of the two
paths are interleaved, not summed.
The circuit diagram of a fully-differential, switched-capacitor highpass path filter is shown in
Fig. 10. On the sampling phase, a charge proportional to VIN is stored on C1A and C1B, and a
charge proportional to VOUT is stored across C2A and C2B. On the subsequent chargeredistribution phase, –VREF is sampled onto C1A,B, and charge is transferred from C1A to C3A, C1B
to C3B, C2A to C3B, and C2B to C3A. Because the capacitors C2A and C2B are cross-coupled around
the operational amplifier, the charge transferred from C2A and C2B effectively undergoes an
inversion during the charge-redistribution phase. In the z-domain, the output of the highpass path
filter is
C1 A
z –p1
V OUT ( z p ) = --------- ⋅ ---------------------------------------- ⋅ ( V IN ( z p ) + V REF ( z p ) )
C3 A
C 2B
–1
1 +  --------– 1 z p
C 3 A

(21)
where, as explained in Section III, zp–1 denotes a single delay with respect to the path sampling
rate. When C2B,A = 2⋅C3A,B, the path filter realizes the desired highpass transfer function of (17).
Within the context of the bandpass modulator of Fig. 9(b), the timing diagram in that figure
shows that the Φ1 path, which can be regarded as one of two independent parallel modulators
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 13
with interleaved outputs, samples the input, X(z), on phase Φ1 and redistributes charge on phase
Φ2, whereas the Φ2 path operates 180° degrees out of phase with the Φ1 path, sampling the input
on phase Φ2 and redistributing charge on phase Φ1.
Because no explicit analog capacitor option was available in the technology used to implement
the experimental modulator, the capacitors were synthesized from metal 3–metal 2–metal 1
stacks. The capacitance per unit area of this sandwich structure is low, on the order of 0.074 fF/
µm2, and the bottom-plate parasitic capacitance is estimated to be 70% of the nominal
capacitance value. Although the path filter topology of Fig. 10 is parasitic-insensitive, large
bottom-plate capacitances increase the capacitive load that the operational amplifiers must drive,
thereby increasing the power dissipation. With such large bottom-plate parasitics, it is imperative
to keep the size of the capacitors as small as allowed by kT/C noise and matching considerations.
With the preceding considerations in mind, the input sampling capacitors in the first stage,
C1A,B, were sized at 300 fF. The feedback capacitors, C3A,B, are determined by the desired
resonator gain, C1A,B /C3A,B, and the output sampling capacitors, C2A,B, are determined by (21) to
be twice the value of C3A,B. Smaller capacitors can be used in the second-stage resonator because
it has relaxed requirements with respect to kT/C noise and capacitor mismatch as compared to the
first-stage resonator. Errors introduced after the first stage of the modulator are attenuated by
noiseshaping in addition to oversampling [11]. Thus, sampling capacitors of the second-stage
were scaled to 200 fF to reduce the loading on both the first and second-stage operational
amplifiers.
A close consideration of (21) reveals the disturbing possibility that the highpass path filter will
be unstable if the ratio C2B/C3A is greater than two. In that case, the path filter has a pole outside
the unit circle, |z| = 1, indicating that the impulse response of the filter is unbounded and may
saturate the filter. Fortunately, extensive behavioral simulations empirically indicate that the
experimental modulator is stable if capacitor matching is good to at least 1%. With this level of
matching, simulations show that the internal states of the modulator remain bounded under all
non-overload conditions. Furthermore, the modulator can recover from being overdriven at the
input, or when initially placed in an overload state. In effect, the nonlinear feedback loop
encompassing the unstable path filters and the 1-b quantizer drives the poles of the unstable filter
back within the unit circle. With careful layout techniques, capacitor matching of 0.3% can be
routinely achieved in modern CMOS processes, and matching as good as 0.1% has been observed
[32]. Furthermore, in this design, the matching between capacitors is aided by the physically large
areas needed to implement the desired capacitance values.
Finite dc gain and bandwidth in the operational amplifier degrade the performance of the
highpass path filter in a manner similar to the switched-capacitor integrator discussed in Section
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 14
II. It can be shown that with finite dc gain, A, the transfer function of the filter can be
approximated as
z –p1
C1 A
V OUT ( z p ) = --------- ⋅ ( 1 – δ ) ⋅ -------------------------------------------------------------- ⋅ ( V IN ( z p ) + V REF ( z p ) )
C3 A
C 2B
–1
1 + ( 1 – γ ) ⋅  --------– 1 z p
C 3 A

(22)
where δ and γ are small perturbations proportional to 1/A. If the dc gains of the two amplifiers
used to implement the path filters in the two-path resonator of Fig. 7 differ, there will be a gain
and phase mismatch between the two filter transfer functions. From (18) and (19) it is apparent
that this leads to incomplete suppression of the mirror signal at the output of the two-path
resonator. Behavioral simulations of the experimental two-path modulator that take (22) into
account show that an amplifier dc gain of 1500 (63.5 dB) is sufficient to suppress the mirror signal
by at least 40 dB, while ensuring that the inband quantization noise power remains negligible with
respect to the estimated noise floor that results from thermal noise contributed by the input
sampling network of the first-stage resonator.
Under linear settling conditions, incomplete amplifier settling only introduces a gain error in
the highpass filter transfer function, such that
C1 A
z –p1
V OUT ( z p ) = --------- ⋅ ( 1 – ε ) ⋅ ---------------------------------------- ⋅ ( V IN ( z p ) + V REF ( z p ) )
C3 A
C 2B
–1
1 +  --------– 1 z p
C 3 A

(23)
where ε=exp(–T/τ), T is the time available for settling, and τ is the closed-loop settling time
constant. In the two-path resonator of Fig. 7, if the two constituent highpass path filters settle with
slightly different time constants, τ1 and τ2, then the mirror signal is again incompletely
suppressed because the gains of the two path filters are mismatched. Consequently, at least 5τ to
6τ are required for settling so that small variations in τ between the two filters do not cause a
substantial gain mismatch. If the amplifier settling has a signal-dependent slewing component,
then the effects of incomplete settling upon the two-path resonator cannot be assessed by
modeling the highpass path filters with (23) [16], [17]. The amplifiers in the first-stage resonator
must, in fact, be designed to settle to the full precision of the modulator, which requires a closedloop settling time of no less than 9τ for a dynamic range of 78 dB. It should be emphasized that
distortion due to amplifier slewing can be a concern even at low input signal levels because the
full-scale differential reference voltages are fed back to the path filters on every cycle, as indicated
in Fig. 10. In Section V, incomplete nonlinear settling is identified as the primary mechanism that
limits the performance of the prototype modulator.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 15
With attention toward the requirements for high bandwidth and a modest dc gain of 1500, the
folded-cascode operational amplifier shown in Fig. 11 was used to implement the switchedcapacitor highpass path filters. This topology was chosen over the potentially faster telescopiccascode topology because its input and output common-mode levels are decoupled from one
another and can be set independently. In this design, both the input and output common-mode
levels were set to the mid-supply voltage. The simulated unity gain frequency of the amplifier
when driving a 2 pF load on each output is approximately 400 MHz with a phase margin of 61°.
The corresponding closed-loop settling time constant, τ, is approximately 2 ns, allowing
approximately 6τ for settling when the highpass path filter is clocked at 40 MHz. The simulated
dc gain of the amplifier is 2200. The output common-mode level is set by switched-capacitor
feedback to the bottom NMOS current source transistors.
Quiescent conditions in the folded-cascode amplifier are established with the biasing circuit
shown in Fig. 12. The drains of the transistors in the amplifier are biased at several hundred mV
above VGS –VT to insure that the transistors remain well within the saturation region of operation
so as to maintain a high output resistance. Low-voltage cascoded current mirrors [33] are used to
bias the NMOS and PMOS current source transistors of the amplifier, M5–M6 and M11–M13,
respectively. The gates of the NMOS cascode transistors, M7 and M8, are biased with a string of
devices, M22–M25, that are operated in the linear region [34]. In the same fashion, the gates of the
PMOS cascode transistors, M9 and M10, are biased by the string of linear devices, M28–M31.
Small transistors MN and MP insure that the bias circuit settles to the desired operating point
instead of a stable, zero-current state. All transistors in Fig. 12, with the exception of MN and MP ,
have nonminimum channel lengths in order to reduce the influence of channel length modulation
on the bias voltages. The bias circuit is programmed by a current supplied from off chip. In order
to reduce layout complexity, but at the expense of increased power dissipation, the experimental
modulator contains four independent biasing circuits, one for each operational amplifier.
The two 1-b quantizers in Fig. 9(b) are realized using a fast dynamic latch [35].
Preamplification is not required because each path of the modulator shown in Fig. 9(b) is
relatively insensitive to errors introduced at the inputs to their respective quantizers. However,
simulations indicate that gross mismatch of offset and hysteresis between the two quantizers can
adversely affect the degree of mirror signal suppression that is achieved at the output of the
modulator. In the interest of reducing the input-referred offsets of each quantizer, nonminimum
channel length transistors are used in the regenerative cores of both comparators.
V. EXPERIMENTAL RESULTS
A die photo of the experimental prototype is shown in Fig. 13. Mirror symmetry was strictly
observed in the layout to enhance the rejection of common-mode disturbances in the fully-
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 16
differential circuit. The digital circuits, seen at the right of Fig. 13, are physically separated from
the analog circuits and are powered from a separate supply. Within the chip, the digital ground is
also separate from the analog ground. The two grounds are shorted externally at the power supply.
The active area measures 1.3 mm × 2.1 mm.
When operated from a 3.3-V supply, the experimental modulator dissipates 49 mW, and the
clock generator dissipates an additional 23 mW. An estimated 40% of the power dissipated in the
analog circuitry is devoted to driving the large bottom-plate parasitics of the feedback and
sampling capacitances. Thus, the power dissipation could be reduced significantly in a technology
with a smaller bottom-plate parasitic. Also, the currents and device sizes in the second stage of the
modulator could be scaled more aggressively. In this prototype, to expedite the design, the first
and second stages of the modulator were implemented using identical operational amplifiers.
Only capacitances were scaled in the second stage.
The modulator was characterized by driving an external center-tapped transformer with a highquality, single-ended sinusoidal source locked to 20.003 MHz and applying the resulting
differential signal directly to the inputs of the modulator. The reference voltages of the modulator
were tied to VREF+=1.85 V and VREF–=1.35 V. In the subsequent plots of performance as a signal
level, 0 dB corresponds to a full-scale differential sine wave input of 1.0 Vp-p.
A low-swing, differential clock from an external pulse generator triggered by a low phasenoise signal source locked at 40 MHz was brought on chip and amplified to full swing before the
requisite clock phases are generated. A custom interface board was used to collect 640,000
samples from each of the two independent paths of the modulator, A and B. This data was then
transferred to a workstation for interleaving, filtering, and analysis. Fig. 14 shows an FFT of the
interleaved bitstream, prior to decimation, when a –10 dB input signal is applied to the modulator.
The degree of mirror signal suppression in the modulator was evaluated by demodulating the
bandpass signal down to baseband with quadrature carriers in the digital domain and performing
an FFT on the resulting complex-valued signal, xI[n]+jxQ[n]. The spectrum of the demodulated,
complex-valued baseband signal is shown in Fig. 15. It is seen that the mirror signal is suppressed
by 42 dB with respect to the desired signal.
The plots of the SNR and SNDR versus input signal level shown in Fig. 16 indicate that the
experimental prototype achieves a peak signal-to-noise ratio (SNR) of 72 dB in a passband of 200
kHz centered at 20 MHz. However, the noise floor degrades as the input signal level drops below
about -40 dB. This degradation is most likely the result of mixing between the input signal and
tones in the noise spectrum.
As the input signal level drops below approximately –40 dB, large families of tones arise at dc
and fs /2, where fs is the effective sampling frequency of the modulator, 80 MHz. These tones, seen
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 17
in the undecimated output spectrum of Fig. 17, defy explicit analytical representation, but their
influence can be qualitatively assessed. First, it should be emphasized that high-level tones at dc
and fs /2 are not unique to the two-path architecture. Rather, they are present in many classes of
bandpass, as well as lowpass [36], modulators, and they are readily observed in behavioral
simulations. The existence of tones at dc and fs /2 are especially significant in bandpass
modulators that center the signal passband at fs /4 because, through nonlinear mechanisms, the
tones can mix with the input signal and fall into the passband.
At an 80 MHz sampling frequency, as the input signal level decreases, increased harmonic
distortion and a higher noise floor are observed in the experimental prototype. However, if the
sampling frequency is reduced to 40 MHz, the harmonic distortion disappears and the noise floor
remains essentially constant for all input signal levels. The fact that the degradation is more
pronounced at high sampling speeds suggests that nonlinear operational amplifier settling is the
root cause of mixing between the signal and the tones at dc and fs /2.
Out-of-band sinusoidal dither was applied at the input of the experimental modulator to
improve its low-input level performance. In the presence of a –40 dB dither signal at 20.155 MHz,
the modulator is always being exercised by an active signal, regardless of the actual input signal
level. Consequently, the magnitude of the tones at dc and fs /2 is greatly reduced. The dither signal
is removed by the ensuing decimation filter, and so has no impact upon the performance of the
modulator, other than reducing the dynamic range by about 1 dB. Fig. 18 illustrates how a –40 dB
dither tone was applied to the input of the modulator through a power combiner. In an actual radio
environment, it is likely that out-of-band signals will provide the necessary dithering.
The plots of the SNR and SNDR versus input signal level when dither has been applied are
shown in Fig. 19. The experimental prototype is seen to achieve a measured dynamic range of 75
dB in a bandwidth of 200 kHz around 20 MHz and a peak signal-to-noise ratio of 72 dB. The peak
signal-to-noise plus distortion ratio is 70 dB. The measured dynamic range is limited by circuit
noise, not quantization noise. Therefore, by holding the sampling frequency constant and
reducing the signal bandwidth from 200 kHz to 100 kHz, the dynamic range is increased by 3 dB
to 78 dB. Similarly, for a 30 kHz passband, as is used in IS-54 digital cellular systems, the
dynamic range exceeds 80 dB. The measured performance of the modulator is summarized in
Table 1.
VI. CONCLUSION
Direct single-path implementations of bandpass modulators typically utilize bandpass
resonators that are implemented with conventional switched-capacitor biquadratic filters.
However, as the sampling speed of the modulator is increased, the performance of the resonators
degrades because of incomplete operational amplifier settling, causing a commensurate decline in
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 18
the performance of the modulator. Two-path architectures are proposed as a means of relaxing the
settling requirements for the operational amplifiers.
An experimental implementation has demonstrated that a two-path, fourth-order bandpass
modulator can digitize signals in a 200-kHz passband centered at 20 MHz with 75 dB of dynamic
range. Measured results from the experimental prototype indicate that the mirror signal inherent
to the two-path architecture is suppressed by at least 42 dB, which is considerably better than the
25 dB required by many applications. The experimental prototype was found to suffer from
increasing levels of harmonic distortion and a higher noise floor as the input signal level was
decreased. The measured results suggest that incomplete, nonlinear settling in the amplifiers
causes mixing of tones at dc and fs /2 with the signal in the passband centered at fs /4. Out-of-band
sinusoidal dither has been shown to be an effective remedy for this problem. The phenomenon of
tones at dc and fs /2 is not unique to the two-path architecture. Because these tones can occur in
many classes of modulators, they pose a hazard to any modulator that centers the signal passband
at fs /4.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 19
ACKNOWLEDGEMENTS
The authors thank W. McFarland and Dr. D. Su for providing ongoing guidance and support
for this work. They are also indebted to Dr. D. Shen, Dr. S. Rabii, Dr. S. Sidiropoulos, J. Ingino,
and K. Falakshahi for technical assistance and numerous helpful discussions.
ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 20
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ONG and WOOLEY: A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz............................ 23
FIGURE CAPTIONS
Fig. 1
Receiver architecture with (a) lowpass A/D conversion, and (b) bandpass A/D conversion.
Fig. 2
Fourth-order bandpass Σ∆ modulator architecture.
Fig. 3
Ideal resonator magnitude response.
Fig. 4
(a) Block diagram and (b) circuit diagram of resonator implemented using two-integrator loop
Fig. 5
Switched-capacitor integrator with output delayed by one-half sample period.
Fig. 6
Generalized N-path filter structure.
Fig. 7
Two-path implementation of bandpass resonator.
Fig. 8
Mirror image of signal introduced by gain and phase mismatches.
Fig. 9
(a) Fourth-order bandpass modulator implemented using two-path resonators; and (b)
partitioning of bandpass modulator into two independent highpass paths.
Fig. 10 Switched-capacitor implementation of highpass path filter.
Fig. 11 Folded-cascode operational amplifier.
Fig. 12 Low-voltage biasing circuit for folded-cascode amplifier.
Fig. 13 Die photo.
Fig. 14 Spectrum of undecimated bitstream.
Fig. 15 Spectrum of complex baseband signal.
Fig. 16 Measured SNR and SNDR.
Fig. 17 Tones in the undecimated spectrum.
Fig. 18 Application of out-of-band sinusoidal dither.
Fig. 19 Measured SNR and SNDR when dither is applied to the modulator.
Table 1 Modulator performance summary.
BPF
LNA
Radio
Frequency
(1-2 GHz)
LO 1
BPF
LO 2
BPF
Intermediate
Frequency 2
(10-20 MHz)
sin ωIF2t
cos ωIF2t
LOWPASS
ADC
LOWPASS
ADC
Baseband
Q
I
Fig. 1(a): Receiver architecture with lowpass A/D conversion. (Ong and Wooley)
AMP
Intermediate
Frequency 1
(100-200 MHz)
BPF
LNA
Radio
Frequency
(1-2 GHz)
BPF
LO 2
BPF
fs = 4 * fIF
Intermediate
Frequency 2
(10-20 MHz)
Bandpass
Σ∆ ADC
Digitization
BITS
Fig. 1(b): Receiver architecture with bandpass A/D conversion. (Ong and Wooley)
LO 1
AMP
Intermediate
Frequency 1
(100-200 MHz)
X(z)
+
+
+
–0.4
+
–
+
z–2
+
0.5
+
–
+
z–2
Y(z)
Fig. 2: Fourth-order bandpass Σ∆ modulator architecture. (Ong and Wooley)
+
+
E(z)
–fs/2
–fs/4
fs/4
fs/2
Fig. 3: Ideal resonator magnitude response. (Ong and Wooley)
|H(j2πf)|
X(z)
Gz–1/2
+
z–1/2
1–z–1
2
z–1/2
1–z–1
z–1/2
Y(z)
Fig. 4(a): Block diagram of resonator implemented using two-integrator loop. (Ong and Wooley)
–
+
VIN
Φ1
Φ2
GC1
Φ1
Φ1
Φ2
Φ2
2C1
C2
Φ1
Φ2
Φ1
Φ2
–1
C2
Φ1
VOUT
Fig. 4(b): Circuit diagram of resonator implemented using two-integrator loop. (Ong and Wooley)
Φ1
Φ2
C1
Φ2
CS
Φ1
Φ2
CP
Φ2
VOUT
Fig. 5: Switched-capacitor integrator with output delayed by one-half sample period. (Ong and Wooley)
VIN
Φ1
CI
TIMING
X(z)
1
2
ΦN
Φ2
Φ1
Tp
1
2
ΦN
Φ2
Y(z)
Fig. 6: Generalized N-path filter structure. (Ong and Wooley)
N
HN(zp)
H2(zp)
H1(zp)
Φ1
–20 MHz
Φ2
20 MHz
Path filter (40 MHz)
|Hp(j2πfp)|
X(z)
Φ1
–20 MHz
20 MHz
Entire structure (80 MHz)
|H(j2πf)|
Φ2
Φ1
Y(z)
40 MHz
Fig 7: Two-path implementation of bandpass resonator. (Ong and Wooley)
–40 MHz
1+zp–1
zp–1
1+zp–1
zp–1
–fs/2
–40 MHz
image
–fsig
fsig
fs/2
100 kHz
Fig. 8: Mirror image of signal introduced by gain and phase mismatches. (Ong and Wooley)
–fs/2
–100 kHz
image
desired signal
|Y(j2πf)|
ct
40 MHz
20 MHz
– jω
fs/2
desired signal
fs/4
image
upon complex demodulation, e
–fs/4
–20 MHz
desired signal
|Y(j2πf)|
X(z)
Φ2
Φ2
Φ1
+
+
+
Φ1
+
–
+
–
+
zp–1
zp–1
Φ2
Φ1
+
+
+
Φ2
Φ1
0.5
0.5
+
+
–
+
–
+
D/A
zp–1
zp–1
Φ2
Φ1
E(z)
Y(z)
Fig. 9(a): Fourth-order bandpass modulator implemented using two-path resonators. (Ong and Wooley)
–0.4
–0.4
+
X(z)
Φ2
Φ1
Φ2
Φ1
+
+
+
+
+
+
+
–
+
–
+
zp
zp
–1
–1
+
+
+
+
+
+
0.5
0.5
+
+
–
+
–
+
zp
–1
zp–1
D/A
D/A
Φ2
Φ2
Φ1
Y(z)
Fig. 9(b): Partitioning of bandpass modulator into two independent highpass paths. (Ong and Wooley)
–0.4
–0.4
+
Φ1
–
ΦT
–
+
ΦS
C1B
C1A
ΦS
ΦT
ΦT
ΦT
+
–
ΦS ΦT
C2B
C3B
+
–
C3A
C2A
ΦS
ΦS
ΦS
ΦS
–
VOUT
+
Fig. 10: Switched-capacitor implementation of highpass path filter. (Ong and Wooley)
ΦT: CHARGE-TRANSFER PHASE
ΦS: SAMPLING PHASE
ΦS
ΦT
VIN VREF
+
ΦS
ΦT
ΦS ΦT
in_p
Gnd
bias p1
Vdd
M1
M13
cmfb
M2
1500 µA
M3
out_n
in_n
750 µA
M5
M7
M9
bias n1
bias n2
bias p2
M12
M6
M8
out_p
M10
M4
750 µA
cmfb
Fig. 11: Folded-cascode operational amplifier. (Ong and Wooley)
M11
bias p1
Gnd
M15
M14
Vdd
external current
M18
M19
MN
M25
M24
M28
M29
Gnd
M30
MP
M31
M26
M27
bias n1
bias n2
bias p2
Fig. 12: Low-voltage biasing circuit for folded-cascode amplifier. (Ong and Wooley)
M16
M17
Vdd
M23
M22
M21
M20
bias p1
Fig. 13: Die photo. (Ong and Wooley)
Power Spectral Density (dB)
-150.0
-120.0
-90.0
-60.0
-30.0
0.0
0.0
10.0
30.0
40.0
Fig. 14: Spectrum of undecimated bitstream. (Ong and Wooley)
Frequency (MHz)
20.0
-10 dB, 20.003 MHz INPUT
Power Spectral Density (dB)
-160.0
-100.0
-120.0
-80.0
-40.0
0.0
-50.0
0.0
50.0
100.0
Fig. 15: Spectrum of complex baseband signal. (Ong and Wooley)
Frequency (kHz)
UNDESIRED IMAGE
42 dB
Signal-to-Noise+Distortion (dB)
20.0
-50.0
30.0
40.0
50.0
60.0
70.0
80.0
-40.0
-10.0
0.0
Fig. 16: Measured SNR and SNDR. (Ong and Wooley)
Input Signal Level (dB)
-30.0
-20.0
INPUT FREQUENCY = 20.003 MHz
SAMPLING FREQUENCY = 80 MHz
PASSBAND = 200 kHz centered at 20 MHz
Low level degradation
SNDR
SNR
Power Spectral Density (dB)
-150.0
-120.0
-90.0
-60.0
-30.0
0.0
0.0
10.0
20.0
40.0
Fig. 17: Tones in the undecimated spectrum. (Ong and Wooley)
30.0
-60 dB, 20.003 MHz INPUT
Frequency (MHz)
LARGE TONES
LARGE TONES
Dither Tone,
20.155 MHz,
–40 dB
Signal Tone,
20.003 MHz
MODULATOR
Fig. 18: Application of out-of-band sinusoidal dither. (Ong and Wooley)
POWER
COMBINER
Signal-to-Noise+Distortion (dB)
-40.0
-20.0
INPUT FREQUENCY = 20.003 MHz
SAMPLING FREQUENCY = 80 MHz
PASSBAND = 200 kHz centered at 20 MHz
DITHER TONE = 20.155 MHz, –40 dB
Input Signal Level (dB)
-60.0
SNDR
SNR
0.0
Fig. 19: Measured SNR and SNDR when dither has been applied to the modulator. (Ong and Wooley)
0.0
-80.0
20.0
40.0
60.0
80.0
200 kHz centered at 20 MHz
200
75 dB
72 dB/70 dB
3.3 V
49 mW – Modulator,
23 mW – Clock generator
0.6-µm single-poly, triple-metal
CMOS
1.3 mm × 2.1 mm
Passband
Oversampling ratio
Dynamic range
Peak SNR/SNDR
Supply Voltage
Power dissipation
Technology
Active Area
Table 1: Modulator performance summary. (Ong and Wooley)
80 MHz
Value
Sampling Speed
Parameter
Table 1: Modulator Performance Summary