Practical Issues Designing Switched-Capacitor Circuit
ECEN 622 (ESS)
Fall 2011
Practical Issues
Designing
Switched-Capacitor Circuit
Material partially prepared by
Sang Wook Park and Shouli Yan
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 MOS switch
G
G
S
S
Cov
D
Cox
Cov
D
Ron
o Excellent Roff
o Non-idea Effect
 Charge injection, Clock feed-through
 Finite and nonlinear Ron
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Charge Injection
G
Qch1
Qch2
C
VS
o During TR. is turned on, Qch is formed at channel surface
 Qch = WLC OX (VGS − Vth )
 When TR. is off, Qch1 is absorbed by Vs, but Qch2 is injected to C
o Charge injected through overlap capacitor
o Appeared as an offset voltage error on C
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Charge Injection Effect
CLK
Ideal sw.
Vout
MOS sw.
1V
0.1pF
CLK
o When clock changes from high to low, Qch2 is injected to C
o Compared to ideal sw., MOS sw. creates voltage error on Vout
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Decrease Charge Injection Effect (1)
CLK
Vout
1V
W/L = 1/0.4
0.1pF
W/L = 10/0.4
o Decrease the effect of Qch
o Use either bigger C or small TR. (small ratio of Cox/C)
o Increased Ron
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Decrease Charge Injection Effect (2)
CLK
10/0.4
CLKb
3.1/0.4
Vout
With dummy sw.
0.1pF
1V
Single sw.
o Use dummy switch which provides opposite charge
o Adjust size of dummy sw. for exact canceling
o Needs opposite clock
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Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Decrease Charge Injection Effect (3)
CLK
10/0.4
Vout
CMOS sw.
23/0.4
0.1pF
1V
CLKb
NMOS sw.
o Use N/PMOS complementary switch
o Both Qch cancel out due to their opposite polarity
o Needs opposite clock, increased parasitic capacitance
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Nonlinear Ron
VDD
7.5/0.4
Ron
1.5V
18/0.4
PMOS
Vin
NMOS
GND
N/PMOS
Vin
o Ron varies with signal amplitude
o CMOS sw. can adopt large signal
o Needs opposite clock, increased parasitic capacitance
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Slow Settling due to high Ron
CLK
CLKb
V1
Vin
Vout
20pF
10pF
o Ron varies with signal amplitude
o CMOS sw. can adopt large signal
o Needs opposite clock, increased parasitic capacitance
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Slow Settling due to high Ron
Vout
Vout
Ideal sw.
NMOS sw.
V1
V1
o Small NMOS sw. (5/0.4)
o With high Ron, output is not settled
o In case of large signal input, N/PMOS sw. should be used
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Slow Settling due to high Ron
Vout
Vout
Ideal sw.
NMOS sw.
V1
V1
o Large NMOS sw. (20/0.4)
o Low Ron makes output settled fast
o Close to ideal sw.
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Switch and Clock Arrangement
CKb
M5
C3
CK
M6
CK
CKbe
CK
CKb
CKbe
C1
M1
CKe
M2
CKb
C
CKe
M3
M4
C2
o M2, M4 : small sw., Others : large sw.
o M2, M4 turn off earlier : minimize charge injection effect
o Charge injection
 M2, M4 (M3, M6) : Signal independent
 Others : Signal dependent
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Switch and Clock Arrangement
Ideal sw.
Different sw. (30/0.4, 5/0.4)
Early CLK
Same sw. (5/0.4)
Same CLK
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Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 PSS vs. Transient Simulation
PSS-PAC simulation
fin = 10KHz
fin = 100KHz
fin = 200KHz
o PSS simulation is used to check the frequency
response for Switched-capacitor circuit
o Should be compared with transient simulation
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Capacitor Layout
Cfr
Cfr
Cfr
D
D
D
D
D
D
C1
C2
D
D
Cox
Cfr
Cfr
Cox
D
C2
C1
C2
D
D
D
D
D
D
C1 2
=
C2 3
Cfr
o Capacitor is implemented with PIP (poly) or MIM (metal)
o Total capacitance is the sum of Cox and Cfr’s
o Ratio is more important than absolute value
o Multiples of unit capacitor can minimize ratio error
o Unit capacitor can be determined by process
o Surrounding capacitor bank with dummies is preferred
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
 Layout Example
o Example of SC biquad circuit (TSMC 0.35um)
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Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
Low Voltage Switched Capacitor Circuits
• Challenges of LV SC circuit
design [cas95]
GON
– SC circuits are widely used in filters,
data converters, sample and hold,
and other analog signal processing
building blocks.
– LV SC circuit design is very
challenging due to the difficulties
involved in turning on MOS
switches.
• Solutions
– Low and/or multi Vt process
– Clock boostering or bootstrap
– Switched opamp
VDD
VDD-VT,N
VT,P
Switch conductance for high
VDD(such as 5V)
GON
VDD
VDD-VT,N VT,P
Switch conductance for low VDD
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Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
Low Voltage Switched Capacitor Circuits (Cont’d)
• Low and/or multi Vt process
VDD
[ada90]
– Expensive
M1
– Switch leakage while it is off
– Vt is not tightly controlled for low
C1
Vt transistors
M2 2VDD
C2
M3
M4
• Clock boostering or bootstrap
– Earlier work ( see right figure )
required that transistors could
sustain maximum breakdown
voltage of 2Vdd [nak91, cho95,
rab98]
– This could not be used in finer
technologies due to reduced
breakdown voltage
ELEN 622
Fall 2011
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2VDD
VDD
0
0
Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
Low Voltage Switched Capacitor Circuits (Cont’d)
– Constant overdrive bootstrap clock driving solved this problem
[abo99]
– Reliability is improved as each transistor just sustains Vdd as
maximum voltage
– More power consumption and lower speed due to its complexity
– Potential reliability problem during transient
VDD
φ1
VDD
φ1
φ1
At φ1
Msw
CB
A
CB
φ1
φ1
At φ1
A
Msw
CB
B
A
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Fall 2011
B
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B
Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
– Detailed schematic and wave form [abo99]
• M1, M2, C1, C2 and the inverter could be shared by the switches
with the same phase, other components need to be repeated for
every switch.
M2
VDD
M3
M1
φ1
M10
M8
M7
M4
C3
C1
M13
C2
φ1
φ1
M12
ELEN 622
Fall 2011
M5
Msw
M9
A
B
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
CFB
• Switched opamp [cro94,bas97,
pel98]
– In conventional SC circuits, S1
is the critical switch, as it sees
wide signal swing
– Switched opamp eliminated S1
by switching on and off the
amplifier
– True low voltage operation
– Potential of low power
consumption
– Slower speed ( usually clock
freq. is around several KHz to 1
or 2 MHz ) due to the need to
switch on and off the opamp
ELEN 622
Fall 2011
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CIN
S4
S1
S3
S2
VREF
Conventional SC circuits
CFB
CIN
S2
S4
S3
VREF
Switched opamp circuits
Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
• Low voltage also poses difficulties for designing the
SC Opamps
– To maximize output voltage swing, cascoding of output
transistors should be avoided
– To achieve required DC gain, two stage architecture may
have to be used instead of single stage OTA
– Frequency compensation is an essential issue to make the
amplifier stable and fast settling
– Input common mode bias voltage need to close one of the
supply rails to make input transistors operate correctly (
close to Vss -- PMOS input; close to Vdd – NMOS input )
– Input and output need to be biased at different DC levels,
level shift may be necessary for switched opamp circuits
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example I [abo99]
– Two-stage architecture is adopted to achieve high enough
gain
– Simple output stage maximizes output voltage swing
– First stage is folded-cascode stage with cascode load to
obtain a high gain, as nodes A and B have a small signal
voltage swing, and supply
VDDvoltage
=1.5 V and VTN permit this
luxury
M12
VO+
M14
ELEN 622
Fall 2011
M4
Cc
A
M6
VI+
M3
M1
M5
M7
V
M2 I- B
M8
M9
M10
M11
23 / 27
M13
Cc
VO-
M15
Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
– Cascode frequency compensation [ahu83] is used to have
a higher bandwidth over conventinal Miller compensation
– The functionality of the circuit is independent of VIN_CM
setting, thus VIN_CM could be set to a DC level which
makes the amplifier work properly
Cf
S1
VIN
VOUT
S1
1.5b ADC
output
Cs
S1
VIN_CM
+VR
0
-VR
The X2 residue amplifier for 1.5b/stage pipeline A/D converter
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example II [rab97]
– Two-stage architecture with miller compensation
– Push-pull operation of the second stage maximize driving
capacity
– Two common-mode feedback loops are required to
stablize the bias condition
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example III [pel98]
– One-stage architecture is used due to relaxed system
requirement for the DC gain
– Class AB operation lowers power consumption
– Low voltage current mirror makes more room for the input
transistors
ELEN 622
Fall 2011
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Switched-Capacitor practical issues
Practical Issues Designing Switched-Capacitor Circuit
References
[abo99]
A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital
converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999
[ada90]
T. Adachi, A. Ishikawa, A. Barlow, and K. Takasuka, “A 1.4 V switched capacitor filter,”
IEEE CICC 1990, pp. 8.2.1-8.2.4, 1990
[ahu83]
B. K. Ahuja, “An improved frequency compensation technique for CMOS operational
amplifiers,” IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629-633, Dec. 1983
[bas97]
A. Baschirotto and R. Castello, “A 1-V 1.8-MHz CMOS switched-opamp SC filter with
rail-to-rail output swing ,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1979-1986, Dec. 1997
[cas95]
R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, “Low-voltage analog filters,”
IEEE Trans. Circuits and Systems – I, vol. 42, no. 11, pp. 827-840, Nov. 1995
[cho95]
T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE
J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March 1995
[cro94]
J. Crols and M. Steyaert, “Switched-opamp: an approach to realize full CMOS switchedcapacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp.
936-942, Aug. 1994
[nak91]
Y. Nakagome, et al. “An experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits,
vol. 26, no. 4, pp. 465-472, April 1991
[pel98]
V. Peluso, P. Vancorenland, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 900mV low-power Σ∆ A/D converter with 77-dB dynamic range,” IEEE J. Solid-State Circuits, vol. 33,
no. 12, pp. 1887-1897, Dec. 1998
[rab97]
S. Rabii and B. A. Wooley, “A 1.8-V digital audio sigma-delta modulator in 0.8 um
CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783-796, June 1997
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Fall 2011
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Switched-Capacitor practical issues