Five-State Logic Using MOS-HBT-NDR Circuit by
Standard SiGe BiCMOS Process
Kwang-Jow Gan, Dong-Shong Liang*, Cher-Shiung Tsai, Yaw-Hwang Chen, and Chun-Ming Wen
Department of Electronic Engineering
Kun Shan University
Tainan Hsien, Taiwan, R.O.C.
gankj@mail.ksu.edu.tw
suln@mail.ksu.edu.tw
e5040@mail.ksu.edu.tw
yhchen@mail.ksu.edu.tw
Abstract—The MOS-HBT-NDR device is made of metal- oxidesemiconductor field-effect-transistor (MOS) and heterojunction
bipolar transistor (HBT) devices, but it can show the negativedifferential-resistance (NDR) current-voltage characteristic by
suitably arranging the MOS parameters. We demonstrate a fivevalued logic circuit using the two-peak MOS-HBT-NDR circuit
as the driver and another two-peak MOS-HBT-NDR circuit as
the load. The design and simulation is based on the technique of
the standard 0.35µm SiGe process.
I. INTRODUCTION
In the past few years, several novel applications based on
the negative differential resistance (NDR) have been
developed. Due to their folding current-voltage (I-V)
characteristics, the NDR devices have high potential as
functional devices. Especially, the multiple-peak NDR devices
offer much promise for multiple-valued logic circuits [1]-[3].
Compare to binary logic, multiple-valued logic has a great
advantage to propagate more information.
technique. Therefore we can implement this MOS-HBT-NDR
device and circuit by the standard 0.35µm SiGe process.
The conventional method to bias the multiple-peak NDR
device into the multiple-valued logic is to utilize a resistor or a
constant current source as load. In this paper, we demonstrate a
five-valued logic circuit using the two-peak MOS-HBT-NDR
circuit as the driver and another two-peak MOS-HBT-NDR
circuit as the load. By using this nonlinear load, the states
number of the multiple-valued logic can be doubled and the
bias voltage can be lowered.
II.
MOS-HBT-NDR DEVICE
The NDR device used in this work is made of MOS and
HBT devices. During suitably controlling the MOS
parameters, we can obtain the NDR I-V characteristic.
Therefore we call this NDR device as MOS-HBT-NDR
device.
Most of the previously published NDR-based circuits are
implemented by the quantum-well resonant tunneling diode
(RTD). These devices and circuits require perfect compound
semiconductor and heterojunction growth process. Also, the
fabrication of such RTD-based devices and circuits is based on
the molecular-beam-epitaxy (MBE) or metal-organic-chemicalvapor-deposition (MOCVD) technique of III-V compound
semiconductors, which are not compatible with main stream Sibased CMOS or SiGe-based BiCMOS process.
Recently, the Si/SiGe-based resonant interband tunneling
diodes (RITD) have been successfully developed and applied is
some applications [4]. However the fabrication of these devices
and circuits is utilized the MBE system, which is still not
suitable for the standard CMOS or BiCMOS process.
Therefore, we proposed a new MOS-HBT-NDR device that is
composed of three Si-based metal-oxide-semiconductor fieldeffect-transistor (MOS) devices and one SiGe-based
heterojunction bipolar transistor (HBT) device. We can obtain
the NDR I-V curve by suitably arranging the MOS parameters.
The HBT structure is the standard cell in the SiGe BiCMOS
1-4244-0387-1/06/$20.00 ©2006 IEEE
Fig. 1 Circuit configuration of a MOS-HBT-NDR device
Fig. 1 shows the circuit configuration of a MOS-HBTNDR device, which is composed of two NMOS, one HBT and
one PMOS. The structure of the HBT is the standard cell in
the SiGe BiCMOS technique. This circuit is derived from a Λ-
APCCAS 2006
1.2
Current (mA)
(VP,IP)
RP1-1
0.4
RN-1
0
0.4
Current (mA)
0.8
WMP1=90µm
WMP1=60µm
0.6
WMP1=30µm
0.4
without
MP1
0.2
0
0
0.4
0.8
Voltage (V)
1.2
(a)
2
modulating Vgg
1.6
Vgg=2.0V
1.2
Vgg=1.8V
0.8
Vgg=1.7V
0.8
Voltage (V)
0
0
0.4
0.8
Voltage (V)
1.2
(b)
Fig. 3 The relative I-V curves by modulating (a) the widths of MP1,
(b) the Vgg values.
RP2-1
III.
(VV,IV)
0
modulating WMP1
0.4
WMN1=30µm,WM N2 =60µm
WMP1 =30µm,Vgg=1.7V
0.8
1
Current (mA)
type topology described in [5]. Fig. 2 shows the simulated Ntype I-V curve with respect to the parameters designed as
WMN1=30µm, WMN2=60µm, WMP1=30µm, and Vgg=1.7V. The
lengths of all MOS devices are fixed at 0.35µm. The segment
resistance of the I-V characteristic can be distinguished with
three regions described as the first PDR region (RP1-1), the
NDR region (RN-1), and the second PDR region (RP2-1). The
operation of this MOS-BJT-NDR device can be described as
follows.
The first PDR region describes a situation as MN1 is
saturated, MN2 is cutoff, HBT1 is saturated, and MP1 is
cutoff. The NDR region indicates the case as MN1 is
saturated, MN2 is saturated, HBT1 is active, and MP1 is
saturated. The second PDR region corresponds to the state as
MN1 is saturated, MN2 is linear, HBT1 is cutoff, and MP1 is
saturated. If we replace the HBT by a MN3 device, yet it will
be the type of MOS-NDR circuit [6]. Comparing to the
electrical parameters of the MOS-NDR device, our MOSHBT-NDR device possesses the smaller peak voltage and
better peak-to-valley current ratio (PVCR). That is because of
the smaller turn-on voltage and higher current gain of the
HBT.
1.2
Fig. 2 The negative-differential-resistance I-V curve under
suitable MOS parameters and Vgg values.
By modulating the parameters of the MOS-HBT-NDR
device, we can obtain different NDR I-V characteristics. Fig. 3
shows the relative I-V curves by modulating the widths of
MP1 and the magnitude of Vgg, respectively. Referring to Fig.
3(a), we can obtain the Λ-type I-V characteristic if the MP1
device is removed from the MOS-HBT-NDR circuit. Fig. 3(b)
shows the magnitude of the voltage Vgg can be utilized to
modulate the IP, which is the important parameter in some
logic circuits design based on the monostable-bistable
transition logic element [7].
MULTIPLE-VALUED LOGIC DESIGN
Numerous multiple-valued logic often use two or more
vertically integrated NDR devices to create the multiple-peak
I-V characteristics. However, we design the multiple-peak I-V
characteristics by connecting two MOS-HBT-NDR devices in
parallel as demonstrated in Fig. 4.
The I-V curves of the MOS-HBT-NDR1 and MOS-HBTNDR2 are Λ-type and N-type characteristics, respectively. The
device MN5 is used to shift the turn-on voltages of MOSHBT-NDR2. We can obtain two peaks and valleys in the
combined I-V characteristics. The first peak can be controlled
by the parameters of MOS-HBT-NDR1. On other hand, the
second peak can be controlled by the parameters of MOSHBT-NDR2.
Fig. 5 shows the combined I-V characteristics for the
circuit shown in Fig. 4. As seen, the first peak current can be
modulated by the Vgg1 values. The Vgg2 is fixed at 1.7V, and
the Vgg1 is changed from 1.7V to 2V, gradually. Similarly,
the second peak current can be modulated by the Vgg2 values,
as demonstrated in Fig. 6.
represented by the dashed lines. The magnitudes of the four
peak currents are different. The I-V characteristics for the
multiple-peak MOS-HBT-NDR circuit with the load line
intersect the PDR regions with five stable operation points
from Q1 to Q5.
Fig. 4 Configuration for two MOS-HBT-NDR devices connected in parallel.
Vgg1=2 V
Vgg1=1.9 V
0.8
Vgg1=1.8 V
Vgg1=1.7 V
0.4
0
Vgg2=1.7 V
0
0.5
1
1.5
Voltage (V)
2
Fig. 7 The multiple-valued logic is made of two sets of parallel circuit of two
MOS-HBT-NDR devices.
2.5
Fig. 5 The first peak current of the I-V characteristics can be controlled by the
Vgg1 values.
Vgg2=2 V
Current (mA)
1.2
Vgg2=1.9 V
0.8
Q3
Q5
0.4
Q1
Vgg2=1.8 V
0.8
0
Vgg2=1.7 V
Vgg1=1.7 V
0.4
0
driver
load
1.2
Current (mA)
Current (mA)
1.2
0
Q2
0.5
Q4
1
1.5
2
Voltage (V)
2.5
3
Fig. 8 The load-line analysis of the multiple-valued logic
0
0.5
1
1.5
Voltage (V)
2
2.5
Fig. 6 The second peak current of the I-V characteristics can be controlled by
the Vgg1 values.
To demonstrate the multiple-valued logic circuit, two sets
of two parallel-connected MOS-HBT-NDR devices are
connected, as shown in Fig. 7. By suitably controlling the Vgg
values, we can obtain the I-V characteristics as shown in Fig.
8.
The I-V characteristics of the driver are represented by
the solid lines, and the I-V characteristics of the load are
The voltage to be stored is provided at the cell input and
loaded by enabling the write clock in sequence. The input
voltage then controls the voltage at the multiple-peak MOSHBT-NDR node. When the write clock is off, the voltage
across the MOS-HBT-NDR device adjusts to the nearest stable
operating point, thereby storing the one of the five discrete
levels.
A saw-tooth wave is applied to the input of the memory circuit
with amplitude of 3.3V. A square wave is applied to the write
gate that alternately turns the MOS on and off. The output of
this memory circuit gives the five stable states from V1 to V5,
as shown in Fig. 9. The five operating points at V1, V2, V3,
V4, and V5 represent the logic levels 0, 1, 2, 3, and 4,
respectively.
4
Vout
Vin
3.5
This work was supported by the National Science Council of
Republic of China under the contract no. NSC94-2215- E-168001.
3
Voltage (V)
ACKNOWLEDGMENT
Vclock
2.5
V5
2
V4
1.5
1
V1
0.5
0
0
REFERENCES
[1]
V3
V2
[2]
100
200
300
[3]
Times (ms)
[4]
Fig. 9 Simulated results for the logic operation.
IV.
CONCLUSIONS
We have shown the two-peak I-V characteristics with two
MOS-HBT-NDR devices connected in parallel. Using the twopeak I-V characteristics with another MOS-HBT-NDR device
as a load, a five-valued logic circuit is demonstrated and
simulated by the standard 0.35µm SiGe BiCMOS process.
Because all of the devices used in this circuit are fully
composed of MOS devices, this MOS-HBT-NDR logic circuit
will be convenient to integrate with other Si-based or SiGebased devices and circuits to achieve the system-on-a-chip.
[5]
[6]
[7]
S. Sen, F. Capasso, A. Y. Cho, and D. Sivco,“ Resonant tunneling
device with multiple negative differential resistance: digital and signal
processing applications with reduced circuit complexity,”IEEE Trans.
Electron Devices, vol. 34, pp. 2185-2191, 1987.
S. J. Wei and H. C. Lin, “Multivalued SRAM cell using resonant
tunneling diodes,” IEEE J. Solid-St. Circuits, vol. 27, pp. 212-216, 1992.
A. C. Seabaugh, Y. C. Kao, and H. T. Yuan, “Nine-state resonant
tunneling diode memory,” IEEE Electron Device Lett., vol. 13, pp. 479481, 1992.
N. Jin, S. Y. Chung, R. M. Heyns, P. R. Berger, R. Yu, P. E. Thompson,
and S. L. Rommel, “Tri-state logic using vertically integrated Si-SiGe
resonant interband tunneling diodes with double NDR,” IEEE Electron
Device Lett., vol. 25, pp. 646-648, 2004.
C. Y. Wu and K. N. Lai, “Integrated λ-type differential negative
resistance MOSFET device,” IEEE J. Solid-State Circuits, vol. 14, pp.
1094-1101, 1979.
A. F. Gonzalez, M. Bhattacharya, S.Kulkarni, P. Mazumder, “CMOS
implementation of a multiple-valued logic signed-digit full adder based
on negative-differential-resistance devices,” IEEE J. Solid-State
Circuits, vol.36, pp. 924-32 ,2001.
K. Maezawa, H. Matsuzaki, M. Yamamoto, and T. Otsuji, “High-speed
and low-power operation of a resonant tunneling logic gate MOBILE,”
IEEE Electron Device Lett., vol. 19, pp. 80-82, 199