DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
Sekolah Pendidikan Profesional dan Pendidikan Berterusan (SPACE) JABATAN KEJURUTERAAN ELEKTRIK
PUSAT PENGAJIAN DIPLOMA (PPD), SPACE
UNIVERSITI TEKNOLOGI MALAYSIA
KUALA LUMPUR DDPE 1711 ELECTRICAL ENGINEERING LABORATORY
(DIGITAL ELECTRONICS)
EXPERIMENT 3
FLIP-FLOP, COUNTER AND REGISTER
Update: December 2012 (Othman Jais) Page 1 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
EXPERIMENT 3 : FLIP-FLOP, COUNTER AND REGISTER
OBJECTIVES:
1. To investigate the operation of NAND gate S'-R' latch
2. To investigate the operation of clocked S'-R' flip-flop.
3. To investigate the operation of D-latch.
4. To investigate the operation of edge-triggered D-flip-flop.
5. To investigate the operation of edge-triggered J-K flip-flop.
6. To construct and operate a counter that counts from 0-15 using 7476 IC.
7. To construct and operate a counter that counts from 0-15 using 7493 IC.
8. To construct 7474 ICs to operate as a 4 bit serial load register
MATERIALS & EQUIPMENTS:
1. Digital Lab Trainer
2. IC 7400 – 1 unit
3. IC 7476 – 1 unit
4. IC 7493 – 1 unit
5. IC 7474 – 2 units
6. Required data sheets
EXPERIMENT PROCEDURES
Part A : NAND S’-R’ (Set Reset) Latch
1. An S'-R' flip-flop can be designed using cross-coupled NAND gates as shown in Figure 1
2. Using a 7400 quad 2-inputs NAND gate, construct the circuit given in Figure 1
3. By following the logic input conditions of S' and R' given in Table 1, record your result
and complete Table 1.
Note: Do not disconnect the circuit after completing this part of experiment
Update: December 2012 (Othman Jais) Page 2 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
Result
S
R
0
0
0
1
1
0
1
1
Q
Q(V)
Q’
Q’(V)
Condition
Table 1
Observation
Q1. When is the latch in SET condition?
……………………………………………………………………………………………………………………..
Q2. When is the latch in RESET condition?
……………………………………………………………………………………………………………………..
Q3. What is the active logic level of the input?
……………………………………………………………………………………………………………………..
Q4. What happens when both of the inputs S' and R' are in LOW logic level? Can the logic
conditions be logically accepted?
……………………………………………………………………………………………………………………..
Q5. Why is the flip-flop regularly termed as S'-R' flip-flop?
……………………………………………………………………………………………………………………..
Part B : Clocked (Enabled) S-R Flip-flop.
1. Connect the-circuit as shown in Figure 2. Part 1 of the circuit has been connected
previously as in Figure 1.
2. Record your result-by completing Table 2.
Note: When recording the result at every entry make sure that the particular logic level
of enable input (E) is set first before setting the data (S-R) inputs.
Update: December 2012 (Othman Jais) Page 3 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
E
S
R
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
Q
Q(V)
Q’
Q’(V)
Operation
Table 2
Observation
Q1. Explain the differences in function of the circuits between Figure 1 and Figure 2.
……………………………………………………………………………………………………………………..
Q2. What is the function of the Enable (E) input in Figure 2.
……………………………………………………………………………………………………………………..
Part C : Edge-triggered J-K flip flops (IC 7476)
1. Install 7476 IC on the circuit board and make the connections as shown in Figure 5.
2. Refer to Table 5(a).
i.
Initially-set-the-direct inputs of CLR to logic HIGH and PRE to logic LOW.
Record the output result of Q and Q' at entry no. 0.
Update: December 2012 (Othman Jais) Page 4 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
ii.
Then, set both direct inputs of CLR and PRE to logic HIGH. Observe the
operation of the flip-flop by properly completing Table 5(a) from entry no.1.
3. Refer to Table 5(b). Set both direct inputs of CLR and PRE as specified in the table.
Observe the operation of the flip-flop by completing Table 5(b).
Note: When recording the result at every entry make sure that the particular logic
level of data inputs J and K are settled first before setting the pulse at the clock
input (CP).
CP (Pulse Switch A or B)
J
K
Q
Q’
Operations
CLR = 0 , PRE = 1
x
x
CLR = 1 , PRE = 1
0
x
1
Press switch
0
0
2
Hold
0
0
3
Release switch
0
0
4
Press switch
0
1
5
Hold
0
1
6
Release switch
0
1
9
Press switch
1
0
10
Hold
1
0
11
Release switch
1
0
Table 5(a)
Update: December 2012 (Othman Jais) Page 5 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
CP
J
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
K
Q
Q’
Operations
PRE = 1 , CLR = 1
0
1
0
1
PRE = 0 , CLR = 1
0
1
0
1
PRE = 1 , CLR = 0
0
1
0
1
PRE = 0 , CLR = 0
0
1
0
1
Table 5(b)
Observation
Q1. From the observation made on Table 5(a), when can the data at input J and K be used
to change the output state of the flip-flop?
……………………………………………………………………………………………………………………..
Q2. Give a brief discussion on the observation made from the Table 5(b) of the edge
triggered J-K flip-flop.
……………………………………………………………………………………………………………………..
……………………………………………………………………………………………………………………..
Q3. What are the functions of PRE and CLR direct inputs in J-K flip-flop?
……………………………………………………………………………………………………………………..
Update: December 2012 (Othman Jais) Page 6 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
Q4. S'-R' flip-flop (in Part A) and J-K flip-flop (in Part E) are both 2-data input flip-flops.
state 3 differences in operations between them?
……………………………………………………………………………………………………………………..
Part D : Asynchronous Binary Up Counter
Assemble circuit as shown in Figure 1 using two (2) 7476 IC. Follow the instructions
carefully and answer the questions accordingly.
Step 1: Set all J,K, PRE',CLR' input to high.
Step 2: Connect all output pins to the LED display. Arrange accordingly from LSB to MSB.
(Clear all pins by touching the CLR pins to GND)
Step 3: Observe the flip-flop outputs when the logic pulse button is pressed for the first time.
QD=……………. QC=……………. QB=……………., QA=…………….,
Step 4: Observe the flip-flop output when the logic pulse button is pressed for the second time.
QD=……………. QC=……………. QB=……………., QA=…………….,
Step 5: Using a wire/jumper connected to Ground (OV), touch the CLR pins for each flip-flop.
What happens to:
QD=……………. QC=……………. QB=……………., QA=…………….,
Step 6: Repeat the experiment by pressing the logic pulse for each state starting from 0000.
Observe all flip-flops output and record the observation in Table 1.
Note: You may want to use a 1Hz square wave signal from the Digital Lab Trainer signal
generator to replace the Clock Pulse signal.
Update: December 2012 (Othman Jais) Page 7 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
CP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QD
QC
QB
QA
Table 1
Part E : 7493 Binary Counter.
Assemble circuit as shown using a 7493 IC as shown in Figure 2. Follow the instructions
carefully and answer the questions accordingly.
Step 1: Connect all outputs to the LED display of the Digital Lab Trainer. Arrange the output
accordingly from LSB to MSB.
Step 2: Press the pulse switch to the first flip-flop, State the observation.
QD=……………. QC=……………. QB=……………., QA=…………….,
Step 3: Connect RO1 and RO2 to Ground. State your observation.
QD=……………. QC=……………. QB=……………., QA=…………….,
Step 4: Clean all flip-flop output by touching all CLR pins to Vee. Make sure all pins are cleared.
Step 5: Start the experiment by pressing the logic pulse for each state starting from 0000.
Observe all flip-flop output and record the observation in Table 2.
Update: December 2012 (Othman Jais) Page 8 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
CP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QD
QC
QB
QA
Table 2
Turn off the power.
Step 6: Clear all pins.
Step 7: Connect QB to RO1 and QD to RO2. State all observation in Table 3.
CP
QD
QC
QB
QA
Table 3
Update: December 2012 (Othman Jais) Page 9 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
Part F : Serial Load Register
ƒ
The circuit uses two 7474 ICs consisting of two D flip-flops each.
ƒ
A common clock input is connected to each flip-flop in the register.
ƒ
When a synchronous clock pulse is applied, all the bits in the register shift
together one place to the right.
ƒ
The circuit can be used as a SISO or SIPO register.
Step 1: Assemble circuit as shown in Figure 3.1.
Step 2: Connect the output pins, QA, QB, QC and QD to the LED Display of Digital Lab Trainer.
Step 3: Connect all PRE' inputs to the Data switch of Digital Lab Trainer and Set to HIGH (1).
Step 4: Turn the power-ON of Digital Lab Trainer.
Step 5: Switch momentary the CLEAR inputs to LOW (0). So the data in the register is cleared
out (data 0000 is in the register).·
Step 6: Then, Set the switch of CLEAR inputs back to HIGH (1).
Step 7: Complete Table 3.1.
Update: December 2012 (Othman Jais) Page 10 DDPE 1711 Electrical Engineering Laboratory 1
Digital Electronics
Experiment 3 : Flip-flop, Counter and Register
Input
Outputs
Line
Clear
Data
Input
Line
Clock
Pulse
(CP)
A
O
X
B
1
0
C
1
1
CP
D
1
0
CP
E
1
1
CP
F
1
1
CP
G
0
1
H
1
1
CP
I
1
1
CP
J
1
0
CP
K
1
0
CP
L
1
0
CP
M
1
1
CP
N
1
0
CP
O
0
0
P
1
1
CP
Q
1
0
CP
R
0
1
CP
LED Indicators
QA
QB
QC
QD
Table 3.1
Update: December 2012 (Othman Jais) Page 11