INTERNATIONAL
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International Journal of JOURNAL
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6480(Print), ISSN 0976 – 6499(Online),
Volume 6, Issue 4, April
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ISSN 0976 - 6480 (Print)
ISSN 0976 - 6499 (Online)
Volume 6, Issue 4, April (2015), pp. 24-33
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IJARET
©IAEME
RANDOM PULSEWIDTH MODULATION TECHNIQUE
FOR A 4-LEVEL INVERTER
David Solomon George
Associate Professor, Dept. of Electronics and Communication
Rajiv Gandhi Institute of Technology, Kottayam, Kerala
Shiny G
Associate Professor, Dept. of Electronics and Communication
College of Engineering Trivandrum, Thiruvananthapuram, Kerala
ABSTRACT
Random Pulse Width Modulation (RPWM) technique for a 4-level inverter in open-end
winding induction motor configuration is proposed in this paper. Reference voltage space vector is
randomly sampled and it is realized in average sense by switching its three nearest vectors.
Switching frequency is randomly varied within the bounds to get randomly spaced samples. The
method requires no sector identification. The reference phasor is converted into a vector lying in the
basic 2-level inverter to calculate switching time vectors. The proposed scheme is implemented and
experimental results are presented for a dual inverter fed 4-level open-end winding induction motor
drive using DSP platform, TMS 320LF2407A.
Keywords : Random Pulse Width Modulation, Space Vector, 4-Leevel Inverter, Open-End Winding.
1.
INTRODUCTION
Due to reduced acoustic noise, mechanical vibration and electromagnetic interference,
various Random PWM (RPWM) techniques have been emerged as an alternative to deterministic
PWM methods [1]-[11]. In these techniques, the energy concentrated at the harmonics of switching
frequency is spread into a continuous frequency spectrum. Conventionally random switching,
random switching frequency and random pulse position are widely used for spectral spreading [1].
Most of the RPWM techniques are of carrier based. But there exist a few Random PWM
implementations using the principles of space vector [5], [9]-[10]. Digital implementation of Space
Vector PWM (SVPWM) techniques is easy. Moreover, better utilization of DC bus is also ensured in
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
SVPWM [12].
For medium and high power applications, due to reduced stress on power switches, low
output voltage distortion and less harmonic distortion, multilevel inverters are widely used [13], [14].
Multilevel inverter topologies - Neutral Point Clamped, Flying Capacitor, Cascaded and Open-end
winding induction motor based inverters and their modulation schemes are researched extensively
[13]-[17]. Sine triangle PWM (SPWM) and Space Vector PWM are the most commonly used
modulation strategies for multilevel inverters.
Principles of random modulation techniques originally researched for 2-level inverters are
currently being applied for 3-level inverters also [8]-[11]. The advantages of random techniques are
combined with the advantages of multilevel inverters such as less harmonic distortion, less stress on
power devices and lower common mode voltage. A RPWM technique with weighted switching
decision which combines the advantages of deterministic and non deterministic methods is proposed
in [8]. By randomizing the sequence of switching vectors RPWM can be achieved and is proposed in
[9]. RPWM technique implemented in [10] uses the concept of distribution ratio used for voltage
balancing of linked capacitors. A random switching scheme with a decoupled strategy can be
adopted for a dual inverter fed 3-level open-end winding induction motor drive [11].
A space vector based RPWM scheme for a 4-level inverter using the principle of variable
switching frequency is presented in this paper. Samples of reference voltage space vector, which are
obtained by random sampling, are realized in the average sense by switching nearest vectors with
appropriate switching times. In the proposed scheme, by randomizing vectors for a 2-level inverter
only, random switching vectors for the multilevel inverter are generated. The proposed space vector
based scheme uses algorithm in which no sector identification methods are required. From
instantaneous amplitudes of three phase reference voltages switching vectors are automatically
generated.
The proposed scheme is implemented for a 2 hp open-end winding induction motor based 4level inverter using TMS320LF2407 DSP platform and the experimental results are presented. Virtex
II PRO XC2VP30 FPGA board is used along with the DSP platform for the generation of switching
vectors.
2.
4-LEVEL INVERTER BASED ON OPEN-END WINDING INDUCTION MOTOR
CONFIGURATION
Open-end winding induction motor is realized by opening the neutral point of a star
connected induction motor. Multilevel inverter structures can be obtained by feeding it with 2-level
inverters from both ends [15]-[17]. In open-end winding induction motor configuration, when
individual inverters are applied with asymmetric DC link voltages of (2 / 3)Vdc and (1/ 3)Vdc , the
resultant switching vector combination is equivalent to a 4-level inverter [17]. A 4- level inverter in
open-end winding configuration and the space vector combinations of individual 2-level inverters are
shown in 1(a) and Fig. 1(b) respectively. The space vector locations of the resultant 4-level inverter
are shown in Fig. 2. As each 2-level inverter can assume 8 states independently, there are 64 (28)
switching combinations for the resultant 4-level inverter. These 64 switching combinations are
distributed over 37 locations as shown in Fig. 2.
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
Fig. 1(a): 4-level inverter in open-end
winding induction motor configuration
Fig. 1(b): Space vector locations of
two 2-level inverters with
asymmetric DC link voltages
The hexagonal structure in Fig. 2 is having an inner sub hexagon with its center as O and its
six vertices marked as A to F. With these vertices as center, six other sub hexagons (referred to as
middle sub hexagon) can be identified. Centered on the vertices of middle sub hexagons marked as
G to S (except O), there are twelve outer sub hexagons.
3.
PRINCIPLE OF THE PROPOSED SCHEME
By sampling the reference space vector at random intervals randomization can be achieved.
Switching frequency is randomly varied to obtain randomly spaced samples of the reference phasor
for every PWM cycle. These random samples of random phasor are realized by SVPWM. The PWM
signals resulting from this random sampling are non periodic, leading to spectral spreading. In
different cycles of reference signal samples are obtained at different angular positions as shown in
Fig. 3. This non periodic time domain PWM signal generated leads to spreading of the frequency
spectrum.
Fig. 2: Space vector combinations of 2-level inverters with
asymmetric dc link voltages resulting in space vector
locations of 4-level inverter
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
Fig. 3: Non periodic PWM signals generated for A-phase of the reference signal for
two different cycles consequent to random sampling of the reference phasor
In the proposed method, the reference space vector is sampled at randomly spaced intervals
determined by the random frequency generated by the Linear Congruential Generator (LCG)
implemented by the DSP. LCG is given by the equation (1).
X n +1 = ( aX n + c ) ( mod l )
(1)
where the coefficients a, c and l are multiplier, increment and modulus.
X n +1
is the current
value of random number generated from the previous value X n . X 0 is the seed for the LCG [6]. In
the proposed scheme, switching frequency is randomly varied in the range 2.5±1KHz by properly
selecting the parameters.
The space vector diagram can be viewed as consisting of 3 layers marked as L1 , L2 and L3 and
are shown in three different shades in Fig. 4 [20]. The layer in which the tip of the reference space
phasor lies is given by the equation


 v



j max
L = 1 + int 

  3 Vdc  
  2 n − 1  
(2)
In this figure, locus of reference space vector for three different modulation index lying in
layers L1 , L2 and L3 and randomly sampled vectors OT1, OT2 and OT3 respectively are shown.
Depending on the modulation index, the tip of the reference space vector is either in layer L1 , L2 or
L3 and the 4-level inverter operates in 2-level, 3-level or 4-level.
3.1
Two-level operation of the inverter
When the tip of the reference space vector in layer L1 , and m < 0.288 (as for vector OT1 in
Fig. 4), 2-level operation results. Then the reference phasor can be realized by a 2-level inverter
only. In the proposed scheme inverter-2 switches SVPWM and inverter-1 is clamped to origin.
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
3.2 Three-level operation of the inverter
When the tip of the reference space vector is in layer L2 and m < 0.577 , 3-level operation
results and reference phasor is realized by switching both the inverters. In Fig. 5, OT2 shows the
randomly sampled reference space vector. The vector is resolved into two components with sub
hexagon center nearest to the tip of reference space vector as one of the vectors (OC). The second
component, CT2, which is completely lying in layer L2 is mapped into OT2’, a vector lying in layer
L1 . Switching time of the vectors is found out for the mapped reference vector by using algorithm for
switching time calculation for a 2-level inverter.
Fig. 4: Space vector diagram of a 4-level
inverter with three switching vectors marked
as OT1, OT2 and OT3 and three layers marked
as L1, L2 and L3
Fig. 5: Three-level operation of the inverter
Determination of the center of sub hexagon nearest to the tip of reference space vector is
done from instantaneous amplitudes of reference space vector. The instantaneous polarity of the 3phase reference signal directly give center of the nearest sub hexagon if a positive polarity is denoted
by ‘1’ and negative polarity by ‘0’ [19], [21].
3.3
Four-level operation of the inverter
4-level operation of the inverter results when the tip of the reference space vector is in layer
L3 and m < 0.866 . In Fig. 6, vector OT3 represents a reference space vector lying in layer L3 . The
vector is resolved into component vectors OL and IT3. OL is the center of the sub hexagon nearest
to the tip of the reference space vector.
When the reference space vector lies between ωt=120º and ωt=180º as shown in Fig. 6, from
the polarity of 3-phase reference signal, vector 110 is obtained. By adding the vector 110 to itself, its
preceding (100) and succeeding vectors (010), the possible nearest sub hexagon centers 210
(=110+100), 220 (=110+110) and 120 (=110+010) are generated. Of these sub hexagon centers, the
one which is having minimum distance to the tip of the reference space vector is chosen as the
nearest sub hexagon center. In the figure, vector OT3 is realized by adding IT3 to vector OI (220).
The actual switching vectors are generated after calculating the switching timings of mapped
reference vector OT3’.
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
Fig. 6: Four-level operation of the inverter
Fig. 7: Instantaneous mapped reference
signals, corresponding gating pulses and
effective (active) switching time
3.4 Mapping of reference phasor and switching time calculation
Let (α, β) coordinates of the sub hexagon center nearest to the tip of reference vector is
denoted by Vα and Vβ . The (α, β) coordinates of the mapped reference vector is the distance of Vα and
Vβ from the (α, β) coordinates of the tip of reference phasor.
A simple algorithm based on instantaneous amplitudes of 3-phase reference signal is reference
used to determine the switching time of 2-level inverter [18].
The instantaneous values of 3-phase phase reference voltages vas , vbs and vcs are calculated from the
mapped reference phasor.
The switching times Txs is given by
Txs = ( Ts / Vdc ) vxs where x ∈ a, b, c
(3)
Fig. 7 shows instantaneous 3-phase mapped reference voltages, corresponding switching
signals and the effective switching time. The effective time Teff is the time for which the load is
connected to the source. It is given by
(4)
Teff = Tmax −Tmin
where Tmax and Tmin are maximum and minimum of Txs .
By adding an offset to the imaginary switching time, actual gating signal for the 2-level inverter
can be generated. In SVPWM, centralized pulses are obtained by placing the effective vector at the
center of the sampling period by adding an offset given by
Toffset
= T0 / 2 − Tmin
(5)
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
3.4
Generation of switching vectors for 4-level inverter
The switching vector for 4-level inverter is obtained by adding the randomized switching
vector for 2-level inverter with the center of the sub hexagon nearest to the tip of reference space
vector. Thus, from the random signals generated for the 2-level inverter, random signals for the 4level inverter are obtained.
4
EXPERIMENTAL RESULTS
The proposed RPWM scheme is implemented for a 2 hp induction motor drive for different
modulation index. By using the DSP platform TMS 320LF2407A, the algorithm is implemented and
the control signals are generated. The actual switching signals of the individual 2-level inverters are
generated by Xilinx Virtex II PRO XC2VP30 FPGA board. Experimental results for different
modulation index for a switching frequency of 2.5±1 KHz. is presented.
The plot of gate timing signal Tga for the proposed scheme for different modulation index is
shown in Fig. 8 to 10. Fig.8 shows DAC output of
Tga
for modulation index of 0.2, which is the
condition of 2-level operation. Fig. 9 and Fig. 10 show plot of Tga for modulation index of 0.5 and
0.8 where inverter is operating in 3-level and 4-level respectively. Randomly varying switching
frequency produces abrupt variations in Tga . For all ranges of speed, Tga shows random variations
which indicate the effectiveness of the proposed technique. The phase voltage and current of the
proposed scheme for a modulation index, of 0.8 is shown in Fig. 11.
The pole voltage of A-phase for a modulation index of 0.8 is shown in Fig. 12. The upper
trace shows the pole voltage, VAO, of Inverter-I and the middle trace shows the pole voltage, VA’O’,
of Inverter-II (in Fig. 1(a)). The lower trace shows the effective pole voltage of the 4-level inverter
which is the difference between the pole voltages of the individual inverters.
Fig. 8: Plot of gate timing
signal Tga of proposed scheme
for modulation
index of 0.2.
X-axis: 20ms/div;
Y-axis: 500mV/div
(experimental result - DAC
output)
Fig. 9: Plot of gate timing
signal Tga of proposed
scheme for modulation
index of 0.5.
X-axis: 10ms/div;
Y-axis: 500mV/div
(experimental result DAC output)
30
Fig. 10: Plot of gate
timing signal Tga of
proposed scheme for
modulation
index of 0.8.
X-axis: 4ms/div;
Y-axis: 500mV/div
(experimental result DAC output)
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
The spectrum of the phase voltage, for the proposed scheme and that of SVPWM (for a fixed
switching frequency of 2.5 KHz) for a modulation index of 0.5 is shown in Fig. 13(a) and 13(b). It is
observed that for the proposed RPWM scheme, the spreading of spectrum
spectrum is achieved and no
harmonic components of the switching frequency are present. But for the SVPWM, energy is
concentrated at amplitudes for all harmonic components.
Fig. 11: Trace of phase voltage and phase
current for modulation index
of 0.8. (4-level operation)
Upper trace: A-phase voltage;
Scale: X-axis: 5ms/div; Y-axis: 50V/div
Lower trace: A-phase current;
Scale: X-axis: 10ms/div;
Y-axis: 2A/div
Fig. 12: Trace of pole voltage for modulation
index of 0.8. (4-level operation)
Upper trace: A-phase
A
pole voltage of inverter-I;
Middle trace: A-phase
A
pole voltage of inverterII;
Lower trace: Pole voltage of equivalent 4-level
4
Fig. 13 (a) Spectrum of phase voltage for
modulation index of 0.5 for the
proposed scheme
Scale: X-axis: 5KHz/div;
Y-axis: 20dB/div
Fig. 14(a) and 14(b) show the spectrum of the phase voltage of the proposed method and that
of SVPWM for a modulation index of 0.8. The proposed method is proved to have better spectral
spreading characteristics.
Fig. 13 (b) Spectrum of phase
voltage for modulation index of 0.5
for SVPWM with constant
switching frequency
Scale: X-axis: 5KHz/div;
Y-axis: 20dB/div
Fig. 14 (a) Spectrum of phase
voltage for modulation index of
0.8 for the
proposed scheme
Scale: X-axis: 5KHz/div;
Y-axis: 20dB/div
31
Fig. 14 (b) Spectrum of phase
voltage for modulation index
of 0.8 for SVPWM with
constant switching frequency
Scale: X--axis: 5KHz/div;
Y-axis:
axis: 20dB/div
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 6, Issue 4, April (2015), pp. 24-33 © IAEME
5
CONCLUSION
In this paper a space vector based random PWM scheme for a 4-level inverter is presented.
The sampling of reference space vector is made at random intervals to achieve randomization.
Random switching frequency in the range of 2.5±1KHz. is used in the experimental verification of
the proposed scheme. Mapping technique used in this scheme can be used for extending the
proposed scheme to any n-level inverter. The experimental results show the effectiveness of this
scheme in spreading the energy of output into continuous spectrum for all modulation indexes. The
scheme is verified for a 4-level open-end winding induction motor based drive with asymmetric DC
link voltage and can be, implemented for any inverter topology.
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