Digital Circuit Hierarchy
COEN 451 W_8
Static Circuit:
In General, digital circuits are divided into two classes:
Combinational: The outputs are function of the inputs only.
Sequential: The outputs are a function of the inputs as well as the states of the circuit.
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CMOS Combinational Logic
Shown in figure below, is the general structure of this family of circuits. It has two major parts, the path to V
DD
, through the pull up network and the path to Vss through the pull down network. The pull up is a pmos network, while the pull-down is an nmos network.
Each gate will take 2N transistors, where N is the number of inputs.
Simple Example: an inverter
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
2-input NAND Gate
The NAND gate has two nmos transistors in series in the pull-down and two pmos transistors in parallel in the pull-up network as shown below.
The basic functionality of a 2-input NAND gate is given in the figure above Whenever input A is ‘0’ and for any value of B, transistor A is active and will conduct, pulling the output node high. Similarly, whenever input B is ‘0’ and irrespective of input A, transistor B will drive the output node high. The only time that the output is low is when both A and B are high, in which case the pull down network will become active at the same time, pulling the output node low. This behavior is typical of ‘inverting logic’.

3-input NAND Gate
Increasing the pull-down and the pull-up series and parallel networks transistors by one as shown in the diagram the 3-input NAND is constructed.
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
2-input NOR gate
2-input NAND Gate Sizing
Consider the following circuit
What will be the optimum size of the transistors which can optimize the circuit in terms of power, delay and area?
The Aspect Ratio of an inverter is made to be Wp/Wn =µ r
(the mobility ratio) so that the pull up and the pull down have the same drive strength, ie the same resistance.
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The aim is to equalize rise and fall time, assuming that minimum width of an inverter is
Wn min
, for t r
= t f
,
W p
W n
  r
let L p
= L n
= L min
. That is, if

=3, then Wp = 3Wn. Then, the r sizing of Wn and Wp is shown in the figure above.
NOTE
This is an approaximate method. Approaximating PD and PU network by a single transistor is wrong due to body effects of different regions of the circuit and internal node capacitances.
Sizing of Transistors
Generally, assume L n
=L p
=L min
unless otherwise stated,
For series pass transistors,
(
W
L
) effec

[(
W
1
L
1
)

1 
(
W
2
L
2
)

1
]

1
, that is we add the lengths together ie increase in resistance. Please note this is an approximation method.
For parallel pass transistors,
(
W
L
) effec

(
W
1
L
1
)

(
W
2
L
2
) , that is we add the widths together. ie increase in conductance.
VTC and the impact of transistor sizing
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With one input being ‘0’ or ‘1’, only one transistor is on while with two inputs being
“00”, two transistors become on, increasing the effective width to 2W min
. Similarly, with an input of “11”, the 2 NMOS transistors are on and this will divide the length by two giving W eff
= 1/2.
Weff pull up
Weff pull down

2
1 / 2

4
To obtain the same VTC and noise margin as with an equivalent inverter, W n
and W p need to be adjusted so as to give equal rise and fall time or W p
=

W r n effective
.
2-input NOR Gate Sizing
Since the PMOS transistors are in series, the resistance adds up. As such, we need to multiply the width in order to reduce resistance. That is, for W n
=W n min
in this circuit,
W p
=6W min
, where 6 = 2x3, 2 for resistance and 3 for
 r
.
NOTE
Design Technique
NOR gates are costly. For the same performance (computation efforts), it results in increased area, power, delay, output load capacitance (due to an increase in drain diffusion capacitance) and increase in input capacitance presenting higher load to driver circuits in comparison to NAND. Convert your circuit to all NAND whenever you can and avoid use of large fanin NOR.
Page 6 of 17

Complex Gates Design
Implement the following Boolean function:
F

A

B

( D

C )
The general idea is to start with the pull down structure, using series transistors for
“AND” and parallel transistors for OR as shown below. Transistor sizing is done for the pull up path and pull down path to be equal to the design inverter. In the circuit below we have sized the transistors for
 r
of 2.
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Transistors sizing is performed, now we look at the transistors ordering!
By replacing the branches, we may obtain a better performance for the same function. In this circuit, put the smaller drain capacitances nearer to the output node.
Now we have a better circuit implementation as there are less drain capacitances at the output node.
Please also note that even a better circuit can be obtained if we place the transistors according to the signal arrival, with the latest arriving signal nearer to the output. This will be covered later.
Page 8 of 17

Ratioed Logic (Pseudo NMOS)
The circuit uses N+1 transistors to implement a function, where n is the number of the inputs. The pull-up is a single pmos with the rest of the pull down consists of nmos transistors, thus saving in area greatly.

2-input NAND Pseudo NMOS

2-input NOR Pseudo NMOS
Page 9 of 17

Complex Gates Design
F

A

B

( D

C )
The same design methodology applies here. Select an optimum pseudo NMOS inverter and optimize your gate accordingly.
Design technique
Remember that this is a ratioed logic, therefore the pull-down transistor/pull-up resistance has to be calculated to give Vol<Vtn, where the value of Vol could be Vtn/2.
R pd
R pd

R pu
* V dd

V tn
2
Advantages of using Pseudo NMOS are: Saving in area, faster depending on design.
Disadvantages: Static power dissipation, short circuit current, reduced noise margin.
Page 10 of 17

Cascode Logic Family
Block diagram of a DCVS circuit (Differential Cascode Voltage Swing)
Page 11 of 17

Example of Cascode Logic
A signal from one gate to the next is always transferred with its complement.
During switching a current spike takes place. This current is usually larger than that of a complementary logic.
This logic is fully compatible with complementary logic because the output makes a full swing between V dd
and V ss
.
Both output and its complement are present.
The circuit uses mainly nmos transistors.
Slower than conventional complementary gate because during switching the pull-ups have to “fight” the n pull-down trees.
Page 12 of 17

F
A static Cascode (CVSL) complex logic gate

( A

B )

C

( D

E )
The load for a static DCVS
Page 13 of 17

The DCVS trees for a full adder Sum and Carry Pull-Down Networks
S’(A,B,C) = A’BC’ + A’B’C + ABC + AB’C’
S (A,B,C) = A’B’C’ + A’BC + ABC’ + AB’C
C(A,B,C) = AB + BC + AC
Comparison with CMOS Gates
Let us compare the parameters involved between CMOS and Coscode such as
Number of transistors, (Area)
Propagation dealy
Power dissipation,
Noise,
Input capacitance
COSCODE has less input capacitance and good logic density. It has dual output with high reliability and high noise immunity. Device count is more but it is nMOS rather than pMOS. , Power dissipation and speeds of the two technologies are similar. However
CASCODE logic is superior for near threshold voltage application. Wiring is a problem as there is a need for dual rail
The pass gate logic uses the pass gate or transmission gate to build a logic circuit.
Reviewing these two devices:
Page 14 of 17

nmos pass gate
C=1
C=0
OUT=A
OUT=NO OUTPUT (OPEN CIRCUIT)
NMOS passes good logic ‘0’
CMOS
TRANSMISSION GATE (TG)
PMOS passes good logic ‘1’
Together they cover the whole range of inputs.
The logic is built around series and parallel pass gates followed by an inverter.
Examples
AND, NAND
A B F
0 0 0
0 1 0
1 0 0
1 1 1
A B F
0 0 0
0 1 1
Page 15 of 17

XOR
OR, NOR
A multiplexer
C
0
0
0
0
A
0
0
1
1
B
0
1
0
1
1
1
F
0
1
0
1
0
1
1
1
C
1
1
1
1
A
0
0
1
1
B
0
1
0
1
F
0
0
1
1
A
0
0
1
1
B
0
1
0
1
F
0
1
1
0
The ideal number of series pass gates is 4. More than this the delay will be impractical.
This is as a result of added series resistance and capacitance, rendering the circuit useless for long chains. There is also charge distribution problems associated to such circuits.
Page 16 of 17

Four to one multiplexer using pass gates
Design Guidelines
The driver for the inputs signals should be strong enough to force the signal.
At Y’ fan in can be a problem.
Be careful a short between Vdd and Ground can exist even for a short period as shown in red in the figure below
END OF LECTURE
Page 17 of 17