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Combinational Logic - Outline
 Conventional Static CMOS basic principles
 Complementary static CMOS
COMBINATIONAL LOGIC
Complex Logic Gates
VTC, Delay and Sizing
 Ratioed logic
 Pass transistor logic
 Dynamic CMOS gates
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Combinational vs. Sequential Logic
Complementary static CMOS
In
Logic
In
Logic
Out
Circuit
 Complex Logic Gates
Out
Circuit
 VTC, Delay and Sizing
State
(flipflops)
(a) Combinational
§ 6.2
(b) Sequential
Output = f (In, History)
Output = f (In)
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Complementary Static CMOS
generic
In1
In2
In3
example
B
B
In1
In2
In3
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2-input Nand/Nor
Pull-Up
Network
PMOS Only
PUN
Pull-Down
Network
A
A
VDD
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NMOS Only
PDN
B
B
A
F =G
B
A
Y = A AND B
A
A
Y = A OR B
B
VSS
§ 6.2.1
 Conduction of PDN and PUN must be mutually
exclusive (Why?)
 Pull-up network (PUN) and pull-down network (PDN)
are dual
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1
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Mutual Exclusive PDN and PUN
C
B
A
P P
D U
N N Out
0
0
0
?
1
1
0
0
1
?
1
1
1
Out = (AB + C)’
VDD
C
A
B
Out
B
C
A
VSS
0
1
0
?
1
0
1
1
0
?
0
1
0
0
0
?
0
1
0
1
0
?
0
1
1
0
0
?
0
1
1
1
0
?
0
Complementary Static CMOS (2)
 Conduction of PUN and PDN must be mutually
exclusive
 PUN is dual (complement) network of PDN
series  parallel
nmos  pmos
 Complementary gate is inverting
 No static power dissipation
 Very robust
 Wide noise margin
 Need 2N transistors for N-input gate
PDN Off
PUN On
PUN Off
PDN On
For all Complementary Static CMOS Gates, either
the PUN or the PDN is conducting, but never both.
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NMOS vs. PMOS, pull-down vs. pull-up
Out = VDD
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Bad Idea
Out = V?
DD – VTn
OUT
IN
pull-up
Out = |V
? Tp|
Out = 0
Exercise: Determine logic function
pull-down
Determine Vout
for Vin = VDD and Vin = VSS
 PMOS is better pull-up
Why is this a bad circuit?
 NMOS is better pull-down
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Assume full-swing inputs (high = VDD, low = VSS)
 Highest output voltage of NMOS is
VGS - VTn = VDD - VTn
 An 1 on NMOS gate can produce a strong 0 at the drain, but not a
strong 1
 Lowest output voltage of PMOS is
VDD + VGS - VTp = |VTp|
(with VGS, VTp < 0 for PMOS)
 An 0 on PMOS gate can produce a strong 1 at the drain, but not a
strong 0
 Need NMOS for pull-down, PMOS for pull-up
A 1 at input can pull-down, 0 at input can pull-up
For a non-inverting Complementary CMOS
Gate, you can only use 2 inverting gates
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Implementation of
Combinational Logic
CMOS Gate is Inverting
Inverting behavior
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 How van we construct an arbitrary combinational
logic network in general, using NMOS and PMOS
transistors (using Complementary static CMOS)?
 Example:
E
l
Y = (A + BC)D
 Remember: only inverting gates available
Ex. 6.2
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2
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Implementation of
Combinational Logic
Improved Gate Level Implementation
 Example:
Y = (A + BC)D
 Remember: only inverting gates available
 Logic depth: number of gates in longest path  DELAY
 Using DeMorgan
B
&
C
B
C
&
A
>1
&
B
A
>1
&
&
C
A.BC
&
?
# transistors 14
D
&
A
logic depth 5?
# transistors 16
?
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Logic depth 3?
 {TPS}: Can this be further improved?
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Complex CMOS Logic Gates
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How to Synthesize Complex Gates
 Restriction to basic NAND, NOR etc.
not necessary
 Easy to synthesize complex gates
B
Y
F
D
 {TPS}: Can this be improved? If so, how?
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Y = (A + BC)D
Y
BC
D
Y
A + BC = A.BC
Y F= (A A+BC)D
BC D
 Using tree representation of
Boolean function
Y
F
C
 Operator with branches for
operands
AND
D
OR
A
 As
A a series-parallel
i
ll l network
t
k
D
Y = (A + BC)D
AND
A
D
# transistors: 8
Logic depth: 1
B
A
PDN
AND
OR
C
B
C
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PUN
Series
Parallel
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Complex Gate Synthesis Example
Parallel
Series
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And-Or-Invert Gate
Y
Y == (A
(A ++ BC)D
(BC))D
B
Y
C
A1
A2
A3
D
AND
OR
A
B1
B2
D
D
AND
A
B
C
B
A
C
AND
OR
PDN
Series
Parallel
PUN
Parallel
Series
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Recipe
 Write Y = f(inputs)
 Decompose f in
tree form
 Realize tree
branches
according to table
at bottom-left
 Use inverted inputs
if necessary
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C1
C2
C3
VDD
&
Dual PMOS
pull-up network
&
>
1
&
Vout
A1
C1
B1
A2
C2
B2
A3
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And-Or-Invert Example
And-Or-Invert Improvement
 From a Truth-Table: take 0-outputs
A
B
C
Y
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
A
B
A
A
B
C
A
B
A
B
C
A
B
C
B
Y
Y
ABC
C
C
B
B
A
A
A, B to be created with extra
inverters (or by restructuring
previous circuits)
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C
C
B
B
B
B
A
A
A
A
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Y = ABC + ABC
Y = (AB + AB)C
12 transistors
10 transistors
2-level logic minimization: boolean algebra technique
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CMOS Complex Gate Sizing
C
D
A
Y = (A + BC)D
D
B
A
C
Y
ABC
Y = ABC + ABC
B
C
C
3 trans. in
series
C
2 trans. in
series
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 Assume all transistors will have mininum length L
 Determine Wn for PDN transistor of inverter that
would give the desired ‘drive strength’
 For each transistor in PDN of complex gate do the
following:
 Determine the length l of the longest PDN chain in
which it participates
 Set W = l Wn
 Repeat this procedure for PUN, using Wp for PUN
transistor of inverter.
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Gate Sizing
A
2
B
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CMOS Complex Gate Sizing
 Function of gate
independent of
transistor sizes: ratioless
 But current-drive
capability (timing)
depends on transistor
sizes
 Worst-case currentdrive depends on
number of transistors
in series
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Gate Sizing
Y = A (B+C)+D
2
2
B
1
B
B
6
C
6
3
A
A
A
4
2
4
2
6
D
 W/L ratios
 what are the W/L of 2-input NAND for the
same drive strength?
A
1
B
1
2
A
D
1
B
2
C
2
0-th order calculation
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Exercise
A1
A2
A3
&
C1
C2
C3
&
N
Dual PMOS
pull-up network
&
B1
B2
Avoid Large Fan-In
VDD
C linear in N
Vout
>
1
A1
C1
R linear in N
C2
Delay  RC quadratic in N
B1
A2
(a)
B2
A3
C
C3
(b)
Exercise:
N
 Perform gate sizing of (a) for nominal drive strength equal to
that of min size inverter, assume PU/PD = 3
 Determine PUN of (b)
 Perform gate sizing of (b) for same drive strength (same
PU/PD)
 Compare sum of gate areas in (a) and (b). Note: area  width
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Empirical
Delay = a1FI + a2FI2 + a3FO
25
Data-Dependent Timing
tPHL = 0.69RNCL
CL t
PLH = 0.69RPCL
You should be able to
identify the transistor paths
that charge or discharge CL,
and calculate resulting RC
delay model, including
effects of wires and fan-out
tPLH = 0.69RpCL
One input goes low
tPLH = 0.69(Rp/2)CL
Two inputs go low,
parallel connection
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2nd Order Effects
tPHL = 0.69(RN  2)CL Series connection
CL
R
-Transistor
T
i t Sizing
Si i
-Progressive Transistor Sizing
-Input Re-Ordering
-Logic Restructuring
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Data-dependent VTC: 2nd order effects
 Much more to say about performance of static
gates
 Simulator can give accurate answer
 Understanding needed to make design decisions
 Data-dependent VTC
 Data-dependent Timing
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Data-dependent Timing
Case I
Cases II
 Charge at ‘int’
 Body effect in M2
A=1, B=: need to charge int
A=, B=1: int does not need to be charged
A=, B=: twice the pull-up strength
{TPS}:
Explain VTC difference between I and II
 Short-circuit currents
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{TPS}:
Explain differences in tpLH
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Combinational Path Sizing for Timing
Given: CL, S1
Determine S2, S3, S4 to minimize delay
We know how to optimally size string of inverters:
make equal stage delays
{TPS}: What is different in comparison to string of inverters?
LOGICAL EFFORT
Answer:
- Delay of unloaded gate differs from delay of unloaded inverter
- For same transistor sizes, amount of output current differs
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Recap: Inverter Delay
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Recap: Inverter Delay
delay
Vs
2S
Cext
-
+
CgS
Cextt
CgS
with t po  R0Cg


R0
f

 Cg S  Cext  t po  1  
S
 
d  1 f 
R0
Cg
C0 =Cg
S
f

tp0
d
C
f  ext
Cin
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Si: relative sizes of inverters
C
with t po   R0Cg , f  ext
Cin
+
S2
S1
S3
S4
Vs
In units of tp0
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delay
Cload
Path delay is minimized if all stage delays are equal
Equivalent output resistance of min size inverter
Input cap of min size inverter
Drain (and Miller) cap of min size inverter
Size of inverter (relative to min inverter)
electrical effort – ratio between Cload and Cin
ratio of drain cap to gate cap
intrinsic delay - delay of unloaded inverter
tp0  20 ps for a 250 nm process, tp0  5 ps for a 45 nm process
normalized delay = tp/tpo
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with Cin  SCg
tp0: Delay of unloaded inverter, independent of sizing
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Inverter Delay Summary
tp 
Cext

f

 t po  1  
 
Cext
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
R0
Cg S  Cext
S


C
 C

 R0Cg  1  ext   t po  1  ext 
 SCg 
 Cin 


tp 
R0, Cg, Cg : output res, input cap and output cap of min size inverter
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CgS
R0, Cg, Cg : output res, input cap and output cap of min size inverter
-
R0/S
CgS
S
Vs
S: relative size of inverter
Vs
R0/S
Vs
S
+
For string of inverters:
when ratio of load cap over input cap is identical for each stage
If Cg = input cap of inverter with size 1 (minimum size):
S2Cg
Cin
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
S2Cg
S1Cg
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S
C
S
S
 2  3  4  load
S1 S2 S3 S4Cinv
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Logical Effort Methodology
Inverter delay:
d inv  1  f 
Gate delay:
d gate  p  gf   p  h 
Intrinsic, Parasitic Delay
VDD
VDD
p parasitic delay - ratio of
intrinsic delay
compared to inverter
p is ratio of output
capacitances if gate is
sized for identical drive
strength
pnand
is (2+2+2)/(2+1) = 2
In units of tp0
A
A
2
B
2
2
F
Logical Effort Methodology Definitions:
p
parasitic delay
– ratio of intrinsic delay compared to inverter
– ratio of output cap for same drive strength
g
logical effort
– how much more load the gate creates
– ratio of input cap for same drive strength
h
gate effort, h = gf
A
F
A
2
B
2
1
Inverter
2-input NAND
p=1
p=2
d gate  p  gf 
[Logical Effort – Designing Fast CMOS Circuits, Sutherland, Sproul, Harris]
Beware: compared to most texts, incl. Sutherland,
Rabaey swaps definition of f and h
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Logical Effort
VDD
A
VDD
A
2
2
B
F
A
A
2
1
B
Inverter
2
2-input NAND
g=1
g=4/3
d gate  p  gf 
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Normalized delay (d)
VDD
VDD
A
A
2
2
B
F
2
F
A
A
VDD
B
4
A
4
2
F
1
A
B
Inverter
1
2
2-input NAND
p=1, g=1
B
1
p=2, g=4/3
2-input NOR
p=2,
p=?, g=5/3
g=?
p ratio of intrinsic delay compared to inverter
g logical effort – ratio of inp. cap for same strength
p, g independent of sizing, only topology of gate
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Delay vs Fan-Out
g = 4/3
p=2
d = 2+(4/3)f/
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Logical Effort
g logical effort: how
much load a gate
provides relative to
inverter for same drive
strength
g ratio of input cap (per
pin) if gate is sized for
identical drive strength
gnand
is (2+2)/(2+1) = 4/3
2
F
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Multistage Networks
2-nand
N
Delay    pi  g i  f i 
inverter
i 1
g=1
p=1
d = 1+f/
&
Stage effort:
effort delay
Normalized w.r.t. unit delay,
assume  = 1
hi = gifi
Path electrical effort: F = f1f2…fN = Cout/Cin
1
2
3
4
5
Fan-out (f)
d gate  p  gf 
6
7
&
f
&
&
Path logical effort:
G = g1g2…gN
Path effort:
H = GF
Path delay
D = di = pi + hi
dnand
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Optimum Effort per Stage
Combinational Path Sizing for Timing
S1 = 1, CL = 36.45
When each stage bears the same effort, optimal effort h*:
hN  H
h  N H
Stage efforts: g1f1 = g2f2 = … = gNfN = h
43
S1 = 1, CL = 36.45
NAND
NOR
INV
1
3x3/2 = 4.5
3x6.75/5 = 4.05
3x12.15/3=12.15
Width of P:
2
3x3/2 = 4.5
3x4x6.75/5 = 16.2
3x2x12.15/3 = 24.3
Nrmlzd Cin
1
9/3=3
20.25 / 3 = 6.75
36.45 / 3 = 12.15
f1 = 3
f2 = 3/g2
f3 = 3/g3
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Logical Effort - Summary
Numerical logical effort characterizes gates
Inverters and NAND2 best for driving large caps
NANDs are faster than NORs in CMOS
Extension needed (see book) for branching
Simplistic delay model
 Neglects input rise time effects
 Interconnect
 Iteration required in designs with wire
 Maximum speed only
 Not minimum area/power for constrained delay





f3g3 = 3 S4 = 12.15
INV
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h  N H  4 81  3
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Combinational Path Sizing for Timing
Width of N:
G = gi = 20/9
F = fi = 36.45
36 45
f3g3 = 3  S4 = 12.15
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f2g2 = 3 S3 = 27/4 = 6.75
g4=1
f4=36.45/S
=36 45/S4
f2g2 = 3  S3 = 27/4 = 6.75
Dˆ    g i f i  pi   NH 1/ N  P
f1g1=3 S2=3
g3=5/3
f3=S4/S3
f1g1=3  S2 = 3
larger fanout for simpler stages
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g2=4/3
f2=S3/S2
H = FG = 81
Effective fanout of each stage: fi  h g i
Minimum path delay
g1=1
f1= S2
CL=
36.45 Cin
f4 = 3
45
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Dynamic Power Dissipation
Power = Energy/transition • Transition rate
= CLVDD2 • f01
= CLVDD2 • f • p01
= CswitchedVDD2 • f
DYNAMIC POWER
DISSIPATION
-Transistor Sizing
- Physical capacitance
-Input and output rise/fall times
- Short-circuit power
p
-Threshold and temperature
- Leakage power
-Switching activity
 Power dissipation is data dependent –
depends on the switching probability p01
 Switched capacitance Cswitched = p01CL=  CL
( is called the switching activity)
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Transition Probability
Impact of Logic Function
Example: Static 2-input NAND gate
pA=1 = pA: given probability of value of signal A being 1 in any clock cycle
pA=0 = pA’: given probability of value of signal A being 0 in any clock cycle
Note the ’ prime (for inversion of signal)
Transition probability:
Probability of 1 to 0 or 0 to 1 transition at clock edge:  = pA(1-pA) = pApA’
A
B
Out
0
0
1
0
1
1
1
0
1
1
1
0
Assume signal probabilities
pA=1 = 1/2
pB=1 = 1/2
Then transition probability
 = p01 = pOut=0 x pOut=1
= 1/4 x 3/4 = 3/16
If inputs switch every cycle
NAND = 3/16
NOR gate yields similar result
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Example: Static 2-input XOR Gate
B
Out
0
0
0
1
0
1
1
0
1
1
1
0
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Signal and Transition Probabilities
OR Gate
Impact of Logic Function
A
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pA: Probability of A being 1
pB: Probability of B being 1
Assume signal probabilities
pA=1 = 1/2
pB=1 = 1/2
A
0
B 0
A OR B 0
1
1
1
0
1
1
1
Then transition
Th
t
iti
probability
b bilit
p01 = pOut=0 x pOut=1
If inputs switch in every cycle
Probability of Output being 0: (1-pA)(1-pB)
= 1/2 x 1/2 = 1/4
Probability of Output being 1: (1-(1-pA)(1-pB))
P01 = 1/4
Transition probability: =(1-pA)(1-pB)(1-(1-pA)(1-pB))
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Signal and Transition Probabilities
AND Gate
Transition Probabilities for Basic
Gates
pA: Probability of A being 1
pB: Probability of B being 1
As a function of the input probabilities
A
0
B 0
A AND B 0
1
1
0
0
0
= p01
1
1
AND
Probability of Output being 0: (1-pA)(1-pB)
Probability of Output being 1: pApB
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(1 - pApB)pApB
OR
(1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB))
XOR
(1 - (pA +pB – 2pApB))(pA + pB – 2pApB)
Activity for static CMOS gates:  = p0p1
Because of symmetry: AND  NAND, OR NOR
Transition probability: = (1-pA)(1-pB)pApB)
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9
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Reconvergent Fanout (Spatial
Correlation)
Evaluating Power Dissipation of Complex
Logic
Inputs to gate can be interdependent (correlated)
Simple idea: start from inputs and propagate
signal probabilities to outputs
y
0.1
0.5
0.9
pin1
0.1
pZ = 1-(1-pA)pA ?
NO!
pZ = 1
pZ = 1-pxpB =1-(1-pA)pB
=0.0099
0.5
reconvergent
no reconvergence
0.989
0.99
0.1
reconvergence
py = 0.9 x 0.5 x 0.1= 0.045
=0.045x(1-0.045) = 0.043
0.045
0.25
0.5
Must use conditional probabilities
pZ = 1- pA . p(X|A) = 1
But:
Reconvergent fanout
Feedback and temporal/spatial correlations
probability that X=1 given that A=1
Becomes complex and intractable real fast
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Glitching in Static CMOS
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Example: Chain of NAND Gates
Analysis so far did not include timing effects
Out2
Out1
1
Out3
Out4
Out5
3.0
101
Out6
000
Out2
X
Voltage (V)
ABC
Glitch
Z
Gate Delay
The result is correct,
but extra power is dissipated
2.0
Out6
Out8
Out7
1.0
Out1
Also known as dynamic hazards:
“A single input change causing
multiple changes in the output”
Out3
0.0
0
Out5
200
400
600
Time (ps)
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A
X
 Logic levels not dependent upon the relative device
sizes; ratioless
D
A,B
A,B
C,D
C,D
X
X
Y
Y
Z
 Always a path to Vdd or Gnd in steady state; low
output impedance
 Extremely high input resistance; nearly zero steadystate input current
 No direct path steady state between power and
ground; no static power dissipation
Z
Uneven arrival times of input signals of gate due to
unbalanced delay paths
Solution: balancing delay paths!
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 Full rail-to-rail swing; high noise margins
Z
Y
C
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Complimentary CMOS Gates - Summary
What Causes Glitches?
B
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 Need 2N transistors for N-input gate
59
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10
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Pseudo NMOS Ratioed Logic
 Reduced area
 Reduced capacitances
 Increased VOL
 Reduced noise margins
 Static dissipation
PDN
RATIOED LOGIC
§ 6.2.2
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Ratioed Logic VOL Computation
IDn (linear) = IDp (saturation)
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Pseudo NMOS Ratioed Logic
Exercise: verify these
assumptions/steps


V2 
V2
k n  VDD  VTn VOL  OL   k p   VDD  VTp VDSAT  DSAT
2 
2


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



Ignore quadratic terms (they are relatively small)
k n VDD  VTn VOL  k p  VDD  VTp VDSAT
Performance of a pseudo-NMOS inverter
Size
VOL [V]
Power [μW]
tpLH [ps]
4
0.693
564
14
2
0.273
298
56
1
0.133
160
123
0.5
0.064
80
268
0.25
0.031
41
569
Ignore, because approximately equal
VOL 
kp
kn
VDSAT 
 pW p
V
 nW n DSAT
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Pseudo NMOS Ratioed Logic
Differential Cascode Voltage Switch Logic (DCVSL)
 Rail-to-rail swing
M2
M1
 No static dissipation
 Rationed
Out
Out
A
B
 Cross-over currents
 Wiring
A
PDN
PDN1
PASS TRANSISTOR LOGIC
PASS GATE LOGIC
PDN
PDN2
B
VSS
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VSS
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11
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Pass Transistor Logic
Pass Transistor Logic
B
 Save area, capacitances
 Need complementary inputs
(extra inverters)
A
B
 Need complementary inputs
(might mean extra inverters)
F  AB
0

V

OH  VDD  VTno
T
NMOS vs. PMOS, pull-down vs. pull-up
 NMOS is better pull-down
5 combinational 12
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 Level restoring circuit
Out
x
VDD
Voltage [V]
In
A
x
VSS
Level restoring
circuit
C
 Rail-to-rail swing
0
0.5
1
68
B
Out
Out
1.0
0.0
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 Discuss what happens when you connect the output
of a single pass-transistor (not a pass-gate) to the
input of another pass-transistor stage (i.e. the gate
of another pass-transistor). Why should you never
use such a circuit?
In
2.0

Exercise
In
3.0
2f  VOH   2f
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Pass Transistor Logic
x

{TPS}: Why is there static dissipation in
next conventional gate?
 PMOS is better pull-up
VDD
F  AB
 Disadvantages (and advantages) may be reduced by
complementary pass gates (NMOS + PMOS parallel)
pull-down
09-May-06
B
 Static dissipation in subsequent static
inverter/buffer
pull-up
TUD/EE ET1205 EC/GS 0506 - © NvdM
A
 Reduced VOH, noise margins 0
But remember:
§ 6.2.3
B
 Save area, capacitances
1.5
2
Time [ns]
 No static dissipation
 Rationed – use with care
 Increased capacitance
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Pass Gates (Transmission Gates)
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Pass Transistor Logic
 use an N-MOS and a P-MOS in parallel
B
B
A
A
B'
F=AB
0
F=AB
B'
0
 Pass gates eliminate some of the disadvantages of simple
pass-transistors
 Eliminates reduced noise margins & static power consumption
 Disadvantages of pass gate:
 Requires both NMOS and PMOS in different wells, both true and
complemented polarities of the control signal needed, increases
node capacitance
 Design remains a trade-off!
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n
t p (Vn )  0.69 kCReq  0.69CReq
k 0
n(n  1)
2
 Propagation delay is proportional to n2!
 Insert buffers
mopt  1.7
t pbuf
CReq
 In current technologies, mopt is typically 3 or 4
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12
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Pass Transistor Logic
 Most typical use: for multiplexing, or path selecting
 Assume in circuit below it is required to either connect A or
B to Y, under control by S
 Y = AS + BS’ (S’ is easier notation for S-bar = S-inverse = S)
 Y = ((AS)’ (BS)’)’ allows realization with 3 NAND-2 and 1 INV:
14 transistors
 Pass gate needs only 6 (or 8) transistors
A
Dynamic CMOS gates
A
&
&
B
&
Y
Y
B
S
S
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Static
CLK
 At every point in time (except during the switching
transients) each gate output is connected to either VDD or Vss
via a low-resistive path.
 The outputs of the gates assume at all times the value of the
Boolean function, implemented by the circuit (except during
switching periods)
 Require 2N transistors for N inputs (fan-in of N)
In1
In2
In3
Mp
Out
CL
PDN
In3
CLK
CLK
1
on
Mp
off
CL
ME
F(In1, In2, In3)
A
C
B
Evaluate
Transistor Me
off
Me
on
Two phase operation
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Precharge (CLK = 0)
§ 6.3
75
ME
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Evaluate
(CLK = 1)
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 Only look at output after
evaluation phase
 On rhythm of global clock
 Example: use edge-triggered FF
with trigger on 1→0 transition of
clock to sample logical value
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Properties of Dynamic Gates (1)
 Only one output transition per
clock cycle, after CLK 0→1. It
cannot be charged again until
the next precharge operation
 Inputs to the gate can make at
most one transition during
evaluation
 Output can be in the high
impedance state during and
after evaluation (PDN off), state
is stored on CL
13/03/14
1
Out
(A&B)|C
CLK
Conditions on Output
In2
Precharge
Transistor Mp
PDN
CLK
 Output not permanently connected to Vdd or Vss
 Output value partly relies on storage of signal values on the
capacitance of high impedance circuit nodes.
 Input only active when clock is active
 Requires N+2 transistors for N inputs
In1
Mp
Out
Dynamic
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Dynamic Gate
Static vs. Dynamic CMOS Circuits
CLK
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CLK
Mp
Out
In1
In2
CL
PDN
In3
CLK
 Logic function is implemented
by the PDN only
 Number of transistors is N + 2
(versus 2N for static
complementary CMOS)
g outputs
p
((VOL = VSS
 Full swing
and VOH = VDD)
 Nonratioed – sizing of the
devices is not important for
proper functioning
ME
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13
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Properties of Dynamic Gates (2)
CLK
Mp
Out
In1
In2
CL
PDN
In3
CLK
Properties of Dynamic Gates (3)
 Faster switching speeds
 reduced capacitive load to
predecessor (only PDN)
 reduced internal capacitance
(drain cap. of only one pullp)
up)
 Low noise margin (NML)
 PDN starts to work as soon
as the input signals exceed
vTN  VM and VIL equal to VTN
CLK
Mp
Out
In1
In2
CL
PDN
In3
CLK
ME
ME
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Issues in Dynamic Design (1)
Out
A
CL
p
t
u
ME
VT
<
Target is to keep
drive a static gate
Cb
CLK
Vo
Δ
Same approach as
level restorer for
pass-transistor logic
L
CL
D
M1

C
a
C +a
C
A=0
Ca
M2
t
u
B=0
Out
VD
=
 Static bleeders
MP
ME
Vo
CLK
CLK
then Vout and Vx reach the same
n
If
value
X
t
u
M1
VT
>
CL
M1
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
MP
Vo
Δ
A=0
CLK
Precharge
Out
80
 Charge redistribution
diffusion diodes and subthreshold leakage
Evaluate
VOut
MP
13/03/14
Issues in Dynamic Design (2)
 Charge leakage – via reversed-biased
CLK
 Needs a precharge clock
 {TPS} compare power of dynamic vs
static CMOS: higher or lower
 Overall power dissipation usually
significantly higher than static CMOS
 Reduced capacitance
 no static current path ever exists
between VDD and GND (including Psc)
 no glitching
 higher transition probabilities
 extra load on CLK
since output may
CLK
ME
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Issues in Dynamic Design (2)
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Issues in Dynamic Design (3)
 Backgate Coupling
CLK
MP
CLK
 Solution to charge redistribution
Out
A
M1
MkP
M1
Clk
 Pre-charge internal nodes using a
clock-driven PMOS transistor (at the
cost of increased area and power)
Mp
A=0
CL1
B=0
B
M2
Clk
CLK
ME
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Out1 =1
Me
This node drops
below VDD,
potentially leading
to partial turn-on of
M1
Dynamic NAND
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Out2: 1→0
In
CL2
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Static NAND
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14
13/03/15
Issues in Dynamic Design (3)
Issues in Dynamic Design (4)
 Clock Feedthrough
 Backgate Coupling
 Coupling between VOut and Clkin of the
pre-charge device due to the CGD
 May forward bias the junction and inject
electrons into substrate
 VOut can rise above VDD
 The fast rising (and falling edges) of the
clock couple to Out
3
Clk
Mp
2
A
Out1
1
Clk
Out
CL
B
2,5
0
Out2
In
Clk
Me
1,5
-1
0
2
4
Time, ns
Clock feedthrough
In &
Clk
0,5
6
Out
-0,5
0
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0,5
Time, ns
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Issues in Dynamic Design (5)
1
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Delayed Clocks
Clk
 Cascading Dynamic Gates
V
Clk
Mp
Clk
Out1
Mp
Clk
11
10
Clk
Out2
In2
In
Clk
Me
Out1
Me
Clk
V
Out2
Only 0  1 transitions allowed at inputs!
Out2
00
01
In4
PDN
PDN
PDN
PDN
In5
In3
VTn
Mkp
Out1
In1
In
Clk
Mp
Mp
Me
Me
t
Evaluation starts when Out1 is stable
Problem when input of 2nd gate not being 0 during precharge
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Domino Logic
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NP Logic, aka NORA Logic
Ensures all inputs to the Domino gate is set to 0 during precharge period
Clk
Clk
Mp
11
10
PDN
PDN
Clk
Me
Mp1
Out2
In4
Clk’
In2
In4
PDN
PDN
Clk
Out2
Me1
 Input capacitance reduced
 No static dissipation
PDN
PUN
In5
In3
Me

ClkVery high-speed
Me2
Out1
In1
PDN
PDN
In5
In3
Clk
Mkp
00
01
In1
In2
Mp
Out1
To other
N blocks
N block
Clk’
Mp2
P block
To other
P blocks
 High dynamic dissipation
 Only non-inverting logic
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Differential (Dual Rail) Domino Logic
 Conventional Static CMOS basic principles
off
1
on
Mp Mkp
Clk
Out = AB
Mkp
0
Clk
Mp
1
A
Summary
!A
 Complementary static CMOS
Out = AB
Complex Logic Gates
0
VTC, Delay and Sizing
!B
B
Clk
 Ratioed logic
Me
 Pass transistor logic
 Dynamic CMOS gates
Solves the problem of non-inverting logic
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16