Wien Bridge Oscillator
Wien Bridge Oscillator
fo  10.28kHz
R
U1
Vo
if
R
4
1
R
1
Will oscillate at frequency
3
1
fo =
2π RC
C
j 
R
R3
R4
=3
Pick
C  1nF
R 
1
2 π C fo
R  15kΩ
Pick
which is a standard value
R3  20kΩ
Pick
C
 15.482kΩ

R4  10kΩ
Page 170 of Lab Manual
R1 = R2 = R
Transfer Function for Circuit shown in Fig 9.2.b
Vo 
R3 
sRC
T( s ) =
= 1 
 2 2 2
Vi
R4

 s R C  3sRC  1

R3

R4
T( f )   1 
C1 = C2 = C
Second Order BPF
j  2 π f  R C

 ( j  2 π f  R C) 2  3 ( j  2 π f  R C)  1
100
0
50
20 log T ( f )
180
 10
0
π
 arg( T ( f ) )
 50
 20
3
1 10
4
1 10
 100
5
1 10
f
RA  RB = 30kΩ
Vγ = 0.7V
the peak value of the output sine wave. Solution with Eqn 9.8 yields
For the diode limiter network pick
Vo = 5V
RA = 3.95kΩ
RB = 26.05kΩ
0
1
2
3
4
D1
5
6
7
8
R10
A
A
26.05kΩ
R9
VCC
3.95kΩ
15V
R5
RF
22kΩ
22kΩ
VEE
B
B
-15V
VEE
-15V
out
U1
C
U2
R3
10kΩ
out_3
C
R6
10kΩ
VCC
15V
C1
VCC
15V
C3
D
15kΩ
1nF
R7
15kΩ
E
1nF
R4
R8
3.95kΩ
C4
1nF
R2
15kΩ
VEE
R1
15kΩ
D
C2
1nF
-15V
R11
E
26.05kΩ
D2
Title: Wien
F
Set ICs to Zero and use small time steps compared to a period.
Size:
A
Use Virtual Op Amp 5 Terminals
F
Document N:
Revision:
0001
Date:
1.0
2012-06-20
Sheet
1
of
1
This is Multisim
G
0
1
G
2
3
4
5
6
7
8
Wien
Printing Time:Wednesday, June 20, 2012, 8:39:16 PM
Transient Analysis
20
No Diode Limiter All Initial Conditions set to zero
(1.0198m, 9.1726)
It Clips at the dc power supply voltages. Highly undesirable.
10
Frequency of Oscillation
(925.0564µ, 4.8770)
Voltage (V)
10.5548026kHz
0
-10
-20
0.00
250.00µ
500.00µ
750.00µ
Time (s)
V(out)
1.00m
1.25m
1.50m
Wien
Printing Time:Wednesday, June 20, 2012, 8:43:31 PM
Transient Analysis
7.5
(1.0167m, 5.0859)
5.0
Diode Limiter Peak Output
5.0859 V
Voltage (V)
2.5
0.0
-2.5
-5.0
-7.5
0.00
250.00µ
500.00µ
750.00µ
Time (s)
V(out_3)
1.00m
1.25m
1.50m
Wien
Printing Time:Wednesday, June 20, 2012, 8:49:20 PM
1 Fourier analysis for V(out_3):
2 DC component:
-0.031584
3 No. Harmonics:
9
4 THD:
6.76763 %
5 Grid size:
256
6 Interpolation Degree:
1
7
8 Harmonic
Frequency
Magnitude
Phase
Norm. Mag
Norm. Phase
9 1
10554.8
5.44243
112.088
1
0
10 2
21109.6
0.0346508
125.259
0.00636679
13.1715
11 3
31664.4
0.351388
-55.842
0.0645646
-167.93
12 4
42219.2
0.00535184
-155.24
0.000983356
-267.33
13 5
52774
0.0974462
31.9446
0.0179049
-80.143
14 6
63328.8
0.00318635
68.2141
0.000585465
-43.874
15 7
73883.6
0.0258589
-154.2
0.00475135
-266.29
16 8
84438.4
0.0034441
153.858
0.000632825
41.7704
17 9
94993.2
0.0277988
-48.781
0.0051078
-160.87
18
Fourier Analysis
10
4
With Diode Limiter Circuit
Voltage (V)
1
400m
70m
40m
7m
4m
1m
0
25k
50k
75k
Frequency (Hz)
V(out_3)
100k
125k
V(6)
15V
12V
9V
6V
3V
0V
-3V
-6V
-9V
-12V
-15V
0.0ms
0.2ms
0.4ms
0.6ms
0.8ms
1.0ms
1.2ms
1.4ms
1.6ms
--- Z:\Z_Red_Ruby\brewdoc\ece3043hwk\hwk07_fbosc\wien_741.cir ---
1.8ms
2.0ms
LTspice netlist
Wien Bridge Oscillator
*No Diode Amplitude Limiter
Cp 3 0 1n IC=0
Rp 3 0 15k
Cs 3 36 1n IC=0
Rs 36 6 15k
R1 2 0 10k
R2 2 6 22k
X0A 3 2 7 4 6 TL071
VCC 7 0 DC 15
VEE 4 0 DC -15
* TL071 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A)
SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
*
| INVERTING INPUT
*
| | POSITIVE POWER SUPPLY
*
| | | NEGATIVE POWER SUPPLY
*
| | | | OUTPUT
*
|||||
.SUBCKT TL071 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL071
.TRAN 0 2m UIC
.PROBE
.END
Page 1
V(6)
15V
12V
9V
6V
3V
0V
-3V
-6V
-9V
-12V
-15V
0.0ms
0.2ms
0.4ms
0.6ms
0.8ms
1.0ms
1.2ms
1.4ms
1.6ms
--- Z:\Z_Red_Ruby\brewdoc\ece3043hwk\hwk07_fbosc\wien_tl071.cir ---
1.8ms
2.0ms
LTspice netlist
Wien Bridge Oscillator
*With Diode Amplitude Limiter
Cp 3 0 1n IC=0
Rp 3 0 15k
Cs 3 36 1n IC=0
Rs 36 6 15k
R1 2 0 10k
R2 2 6 22k
X0A 3 2 7 4 6 TL071
VCC 7 0 DC 15
VEE 4 0 DC -15
D1 2 8 d1n4148
D2 9 2 d1n4148
Ra 6 8 3.95k
Rb 8 7 26.05k
Ra1 6 9 3.95k
Rb1 9 4 26.05k
.model d1n4148 D(is=1n bv=100 n=1.8)
* TL071 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A)
SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
*
| INVERTING INPUT
*
| | POSITIVE POWER SUPPLY
*
| | | NEGATIVE POWER SUPPLY
*
| | | | OUTPUT
*
|||||
.SUBCKT TL071 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL071
.TRAN 0 2m UIC
.PROBE
Page 1
LTspice netlist
.END
Page 2
V(6)
5V
4V
3V
2V
1V
0V
-1V
-2V
-3V
-4V
-5V
0.0ms
0.2ms
0.4ms
0.6ms
0.8ms
1.0ms
1.2ms
1.4ms
1.6ms
1.8ms
--- Z:\Z_Red_Ruby\brewdoc\ece3043hwk\hwk07_fbosc\wien_tl071_diode_limit.cir ---
2.0ms
0
1
2
3
4
5
6
7
8
A
A
R4
190kΩ
VEE
B
B
-15V
C3
C2
C1
1nF
1nF
1nF
R3
C
6.32kΩ
R2
R1
6.32kΩ
5
C
6.32kΩ
VCC
15V
R8
D
D
190kΩ
D2
VEE
-15V
R11
E
C6
C5
1nF
C4
1nF
1nF
E
R9
15kΩ
R5
5.1kΩ
6.32kΩ
7
5.1kΩ
F
R7
6.32kΩ
R6
R12
6.32kΩ
F
R10
15kΩ
G
15V
0
1
2
3
4
5
VCC
D1
G
6
7
8
Phase_Shift
Transient Analysis
Printing Time:Monday, June 25, 2012, 7:54:07 PM
20
They are the same until the diodel limiter network kicks in
Voltage (V)
10
0
-10
-20
0
5m
10m
Time (s)
V(7)
V(5)
15m
20m
Phase_Shift
Printing Time:Monday, June 25, 2012, 7:56:35 PM
Transient Analysis
18
They are the same until the diodel limiter network kicks i
No Limiter
Voltage (V)
9
1
Limiter
-7
-16
17.52m
17.60m
17.67m
17.75m
17.82m
Time (s)
V(7)
V(7):
V(5):
V(5)
x1
17.6883m
17.6883m
y1
5.8314
-6.1310
x2
17.5909m
17.5909m
y2
5.8308
-5.0948
dx
-97.4169µ
-97.4169µ
dy
-615.3424µ
1.0362
dy/dx
6.3166
-10.6366k
1/dx
-10.2652k
-10.2652k
17.90m
17.97m
18.04m
18.12m
0
1
2
3
4
5
6
7
8
A
A
C1
R2
1nF
1kΩ
VEE
VEE
-15V
B
2
-15V
R5
B
R1
15.481kΩ
1kΩ
5
C
C
VCC
VCC
15V
15V
R3
R4
30.96kΩ
D
30kΩ
C2
1nF
D
E
E
F
F
G
G
0
1
2
3
4
5
6
7
8
Quadrature
Transient Analysis
Printing Time:Tuesday, June 26, 2012, 5:29:17 PM
20
Quad No Diode Limiter
Voltage (V)
10
0
-10
-20
0
5m
10m
Time (s)
V(2)
V(5)
15m
20m
Quadrature
Transient Analysis
Printing Time:Tuesday, June 26, 2012, 5:30:54 PM
16
Quad No Diode Limiter
Voltage (V)
8
-53m
-8
-16
16.3m
16.5m
16.6m
Time (s)
V(2)
V(2):
V(5):
V(5)
x1
16.7871m
16.7871m
y1
-5.1974
14.7697
x2
16.8860m
16.8860m
y2
-4.3953
15.0293
dx
98.9405µ
98.9405µ
dy
802.0629m
259.6381m
dy/dx
8.1065k
2.6242k
1/dx
10.1071k
10.1071k
16.8m
16.9m
0
1
2
3
4
5
6
7
8
C1
A
A
R2
1nF
D2
1kΩ
VEE
VEE
B
2
-15V
-15V
B
R1
1kΩ
R7
15kΩ
C
C
VCC
R6
R5
15V
5.1kΩ
5
15.481kΩ
D
R8
5.1kΩ
R9
15kΩ
R3
R4
30.96kΩ
C2
30kΩ
1nF
D
E
E
VCC
15V
D1
F
F
G
G
0
1
2
3
4
5
6
7
8
Quadrature_Diode
Printing Time:Tuesday, June 26, 2012, 5:58:46 PM
Transient Analysis
7.5
5.0
Voltage (V)
2.5
0.0
-2.5
-5.0
-7.5
0.0
2.5m
5.0m
7.5m
Time (s)
V(2)
V(5)
10.0m
12.5m
15.0m
Quadrature_Diode
Printing Time:Tuesday, June 26, 2012, 6:00:12 PM
Transient Analysis
6.9
4.7
Voltage (V)
2.4
141.5m
-2.1
-4.4
-6.7
13.96m
14.03m
14.09m
14.16m
Time (s)
V(2)
V(2):
V(5):
V(5)
x1
14.0782m
14.0782m
y1
6.0018
-292.1749m
x2
14.1757m
14.1757m
y2
5.9989
-364.8312m
dx
97.5181µ
97.5181µ
dy
-2.8724m
-72.6563m
dy/dx
-29.4549
-745.0549
1/dx
10.2545k
10.2545k
14.22m
14.29m
14.35m
Georgia Institute of Technology School of Electrical and Computer Engineering ECE 3043 Electrical and Electronic Circuits Laboratory Verification Sheet NAME:________________________________________ SECTION:___________________________ AD LOGIN:___________________________________ Experiment 9: Linear Op‐Amp Oscillators Procedure Time Completed Date Completed 3. Wein Bridge Verification (Must demonstrate circuit) 4. Phase Shift 5. Quadrature Points Points Possible Received
25 25 25 Enter your critical frequency below: fcrit To be permitted to complete the experiment during the open lab hours, you must complete at least three procedures during your scheduled lab period or spend your entire scheduled lab session attempting to do so. A signature below by your lab instructor, Dr. Brewer, or Dr. Robinson permits you to attend the open lab hours to complete the experiment and receive full credit on the report. Without this signature, you may use the open lab to perform the experiment at a 50% penalty. SIGNATURE:____________________________________ DATE:____________________________________ ECE 3043 Check‐off Requirements for Experiment 9 Make sure you have made all required measurements before requesting a check‐off. For all check‐offs, you must demonstrate the circuit or measurement to a lab instructor. All screen captures must have a time/date stamp. Wein bridge and phase shift oscillators  Scope capture showing open loop input and output waveforms in phase. Display Vpp and frequency measurements.  Scope capture showing closed loop output waveform. Display Vpp and frequency measurements.  Scope capture showing closed loop output waveform with limiter. Display Vpp and frequency measurements.  Comparison of the measured frequency of oscillation to the design value. Adjust the circuit component values if the measured value is not within 10% of the design value. Quadrature oscillator  Scope capture showing both output waveforms. Display Vpp, frequency, and phase measurements.  Scope capture of XY plot.  Comparison of the measured frequency of oscillation to the design value. Adjust the circuit component values if the measured value is not within 10% of the design value.