PETsys Electronics
Medical PET Detectors,
S. A.
Taguspark,
Lisbon Science and Technology Park
Ed. Tecnologia I, nº 26
2740-257 Oeiras, Portugal
T: + 351 96 600 2882
www.petsyselectronics.eu
PETsys TOF Front End Board /D
PETsys
Electronics
The PETsys TOF Front End Board type D (FEB/D_V1) is a carrier of FEB/A readout
boards for Time Of Flight applications (Fig. 3). Up to eight FEB/A boards (Fig. 2) can be connected to the FEB/D, using either direct board-to-board connectors or flexible kapton cables.
The FEB/D is optimised for being used together with arrays of LYSO scintillating crystals associated to SiPMs and eight FEB/A boards as a building block for high resolution PET
scanners using the Time Of Flight information. Each FEB/D board measures 118.0x118.0 mm
and is four-side buttable such as to form a continuously sensitive area with almost no dead
space.
Figure 1
FEB/A 0808 board (top and
bottom).
The FEB/D boards can be integrated with the PETsys DAQ board forming a complete
scalable data acquisition system with several ten thousand channels. Each FEB/D board
collects the data of 1024 channels and transmits assembled data frames through an electrical
serial link (3.2 Gb/s) or two high-speed optical links (8 Gb/s). The data links of several FEB/D
boards can be daisy-chained and interfaced to a single DAQ board to create a compact data
acquisition system. Using the HDMI links the maximum event rate is 65 M events/s; using the
optical links, the maximum output event rate per FEB/D is 162M event/s.
The FEB/D board is supplied with 24 V. On board DC-DC converters and regulators
provide the required low voltages as well as 64 configurable SiPM bias voltage lines.
The TOF ASIC [1] (Fig. 2) used in PETsys front-end system is optimized for timing
and has 25 ps time resolution (r.m.s.). It uses a low threshold for timing and a high threshold
for accepting the event. Both thresholds are separately configurable for each channel. Every
time one of the 64 channels exceeds the high threshold a record is created giving the channel
number, the time and the amplitude of the event. Activity in one channel does not cause any
dead-time on one of the other channels.
Figure 2
The 128-channel assembly
of two TOF ASICs
Figure 3
FEB/D_V1 board.
The board dimensions are
118.0x118.0 mm.
[1]
M. D. Rolo et al., 2013,
JINST 8, C02050
Main features:
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Motherboard serving one detector module of 1024 independent channels
Compatible with FEB/A and DAQ boards
Data readout of 16 TOF ASICs
Output data HDMI serial links (3.2 Gbps)
Two high-speed optical links (8G bit/s)
Gigabit Ethernet interface
Daisy chaining of data and configuration links
External clock and synchronization
Max output event rate (optical links): 162 M events/s
Operation frequency 80-160 MHz
External supply voltage: 24 V
On board DC-DC converters
On board SiPM bias voltage regulation (64 lines)
Temperature monitoring
Equipped with Kintex 7 FPGA
I/O connectors
Each of the eight FEB/A connectors has two rows of pins, separated by ground, one row assigned to the bias voltages and the low voltages, and the other row assigned to the digital
signals. The connector is of type SAMTEC_QTH-030-0H-L-D-A on the FEB/D side matching a
connector of type SAMTEC_QSH-030-01-L-D-A on the FEB/A side.
The lines in the FEB/A connector include:
• CLK_IN: Nominal operation mode uses a 160 MHz clock
• SPI interface: 10 MHz configuration interface writes and reads the configuration
• SYNC RST: dual purpose reset (full and partial reset)
• BIAS V: 8 bias voltages lines
• TX_OUT (0-3): 4 LVDS data links
• TEMP: temperature sensor
• Supply voltages: 1.5 V (analog), 1.2 V (digital), 2.5 V (I/O).
The FEB/D board has a mini HDMI connector carrying the output data link, the input configuration link, as well as the clock and synchronisation lines. All signals are LVDS. Two optical links
connectors and one Gigabit Ethernet connector are also available.
Data frames.
The ASICs transmits data in frames (Fig.4), each frame consisting of the events captured in a
1024 clock period (6.4 μs frames). The FEB/D FPGA receives 16 ASIC point-to-point data links,
builds data frames with all events and outputs the data through a high-speed LVDS serial link.
The output link is 8B/10B encoded and a CRC is
Figure 4
Data frame format (full event data).
Each event includes time counters
and channel ID (6-bit tag of the channel that generates the data). A 2-bit
TAC ID records the index of the TAC
used for a particular event.
For
more information contact sales@vub.ac.be
PETsys
Electronics
PETsys Electronics
Medical PET Detectors,
S. A.
Taguspark,
Lisbon Science and Technology Park
Ed. Tecnologia I, nº 26
2740-257 Oeiras, Portugal
July 2015
T: + 351 96 600 2882
www.petsyselectronics.eu