CMOS and TTL Technologies
Z. Jerry Shi
Department of Computer Science and Engineering
University of Connecticut
CSE2300W:Digital Logic Design
Physical states representing bits
Technology
State Representing Bit
0
1
Relay logic
Circuit open
Circuit closed
CMOS logic
0-1.5V
3.5-5V
Transistor-transistor logic
0-0.8V
2-5V
Light off
Light on
Capacitor discharged
Capacitor charged
Electrons trapped
Electrons released
Fuse blown
Fuse intact
Flux direction N
Flux direction S
No pit
Pit
Dye in crystalline state
Dye in noncrystalline
state
Fiber optics
Dynamic memory
Nonvolatile, erasable memory
Bipolar read
read-only
only memory
Magnetic tape or disk
Read-only compact disc
Writeable compact disc (CD-R)
CMOS logic levels
•
•
•
Undefined region is inherent
Switching threshold varies with voltage,
voltage temp,
temp process,
process phase of the moon
– Need “noise margin”
– The average weekly count of failure in Q in Los Alamos Lab is 47.1
The more you push the technology, the more “analog” it becomes
– Logic voltage levels decreasing with process
– 5 Æ 3.3 Æ 2.5 Æ 1.8 V
Noise margins
Low voltage CMOS logic
Metal-Oxide-Semiconductor (MOS) Transistors
Voltage-controlled resistance
PMOS
NMOS
CMOS Inverter
Inverter
Inverter behavior
CMOS NAND gate
CMOS NOR gate
Example of LS-TTL gates: 2-input NAND
TTL Logic Levels and Noise Margins
• Asymmetric, unlike CMOS
• CMOS can be made compatible with TTL
– “T”
T CMOS logic families
CMOS vs. TTL Levels
TTL Levels
CMOS with TTL Levels -- HCT, FCT, VHCT, etc.
TTL features
•
•
•
TTL families7400 series
– 74 (standard), 74H(high speed), 74L(low-power), 74S(Schottky),
74LS(low-power Schottky), 74AS(Advanced Schottky), 74ALS
(Advanced low-power Schottky), 74F(Fast)
Unused gate inputs can be left unconnected, but should be connected to be
safe
– An output of other gates
– 1 or 0 through
g ppull-up
p or ppull-down resistors
Output
– Totem pole
– Tri-state
Tri state
– Open-collector
CMOS features
• CMOS families:
– 4000 series
– 7400 series:
•
•
•
•
•
•
74HC (high-speed CMOS),
74HCT(High-speed
4 C ( i h
dC
CMOS,
OS TTL compatible)
ibl )
74AC(Avanced CMOS)
74ACT(Advanced CMOS, TTL compatible)
74FCT(Fast CMOS, TTL compatible)
74FCTT(Fast CMOS, TTL compatible with TTL VOH)
• Do not leave unused gate inputs unconnected
• Output
– Regular,
g
, Tri-state,, Open-drain
p
Chip density for various scales of integration
Timing specifications
•
Maximum: the longest delay a circuit may have
– The delay of the path is never longer than the maximum
– What does never mean?
• Depends on manufacturers and logic families
• 74LS: VDD = 5V, T = 25ºC, no capacitive load
• 74ACT: full
f ll operating
i voltage
l
andd temperature range andd a load
l d off 50pF
•
Typical: what you see from a device that was manufactured on a good day and
i operating
is
ti under
d near-ideal
id l conditions
diti
•
Minimum: The smallest delay that a path will ever exhibit
– Most
M t well-designed
ll d i d circuits
i it workk even if the
th minimum
i i
delay
d l is
i 0
– Needs to be considered in some circuits
• Help designers to meet the hold-time requirements
Propagation delay of selected 5-V CMOS and TTL SSI parts
In nanoseconds
MSI parts
In nanoseconds
Fan-in and Fan-out
• A logic family’s fan-in is the number of inputs that a gate can
have
– More inputs Æ more resistors in series Æ long delay
– Faster to cascading multiple gates
• Fan-out refers to the number and type of device inputs and other
loads that are connected to a given output
– Large fan
fan-out
out Æ more load Æ long delay
– Large load Æ inadequate noise margins