CMOS Logic Circuit Design
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Link（リンク）: センター教官講義ノート の下 CMOS論理回路設計
Arithmetic Modules (Part 1)
• Digital Processing Systems
• Base-2 Numbers (Binaries)
• Circuits for Addition and Subtraction
– Adders for Single-Bit Binaries
– Combinational Adders/Subtractors for Multi-Bit Binaries
– Sequential Adders/Subtractors for Multi-Bit Binaries
• Circuits for Data Shifting
Mattausch, CMOS Design, H20/6/6
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Digital Processing Systems
-
Basic Structure
Construction of the Datapath
(Arithmetic Part)
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Basic Digital-Processing-System Structure
Memory:
Interconnect
Unit
Memory
SRAM, ROM, DRAM
Control:
Finite-State Machine,
Micro-Program
Input/Output:
Input/
Output
Control
Buffer, A/D-, D/A-Converter,
Protection Circuits
Interconnect Unit:
Busses, Switches, Arbiters
Datapath
Datapath:
Adder, Multiplier, Shifter,
Logic Unit, etc.
The datapath in a digital processing system is the system
unit, which carries out the actual data-processing functions.
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Construction of the Datapath (Arithmetic Part)
Bit 31
Bit 30
Data-Out
Multiplexer
Multiplier
Boolean Unit
Shifter
Adder
Register
Data-In
Control
Bit 3
Bit 2
Bit 1
Bit 0
Today’s
Lecture
A datapath consists of registers, arithmetic units and a
multiplexer for current-operation selection.
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Base-2 Numbers (Binaries)
-
Signed Binary Numbers with N Bits
Transforming a Signed Binary into its
Negative
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Signed Binary N-Bit Numbers (2’s Complement)
Possible digits d in a binary number
d = {0,1}
Construction of signed (2’s complement form) binary number
(s = 0 means positive, s=1 means negative)
Dbase 2 = sd N− 2 d N −3 o o od 3 d2 d 1d 0
Conversion into the equivalent decimal number
Example of 4-bit binaries
Dbase10 = − s⋅2
N −1
N− 2
+ ∑di⋅ 2
i
7ten = 0111two
6ten = 0110two
-1ten = 1111two
-2ten = 1110two
0ten = 0000two
-8ten = 1000two
i −0
Efficient arithmetic CMOS circuits can be constructed, if
binary numbers are represented in the 2’s complement form.
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Negative of a 2’s Complement Binary
For every D following equation must be valid
(The result of adding the inverted bits and non-inverted bits of any binary consists
of only 1s at all its digits. Thus this result is the representation of -1)
D+ D = −1
Consequently, the negative of any 2’s complement binary can
be calculated by inverting all bits and adding a 1 afterwards.
− D = D +1
Above method of calculating the negative of a binary is often
exploited for simplifying arithmetic hardware.
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Circuits for Addition and
Subtraction
-
Adders for Single-Bit Binaries
Combinational Adders/Subtractors for
Multi-Bit Binaries
Sequential Adders/Subtractors for
Multi-Bit Binaries
Mattausch, CMOS Design, H20/6/6
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Binary-Adder Principle, 1-Bit-Adder Truth-Table
Process of adding two binaries
leads to a 1-bit adder unit with
3 inputs and 2 output
(Carry Bits) (0)
A:
0
+B:
C:
0
1-bit full-adder truth-table
A B
Cin
Full
Adder
Cout
S
(0)
0
(1)
0
(1)
1
(0)
1
1
A
B
Cin
S
Cout
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
(0) 0 (0) 0 (0) 1 (1) 1 (1) 0 (0) 1
Basic Adder Unit
(Full Adder)
Carry
Status
delete
delete
propagate
propagate
propagate
propagate
generate
generate
The basic circuit for realizing the adder arithmetic is the full
adder, a combinational circuit with 3 inputs and 2 outputs.
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Adder/Subtractor as Combinational Circuits
Combinational Adder (“Ripple Adder”) Circuit for S=A+B
A0 B0
Ci,0=0
A1 B1
A2 B2
Co,0
Co,1
Co,2
Full
Full
Full
Adder =Ci,1 Adder =Ci,2 Adder =Ci,3
S0
S1
AN-1BN-1
Co,N-2
=Ci,N-1
S2
Full
Adder
Co,N-1
SN-1
Combinational Subtractor (“Ripple Subtractor”) for S=A-B
A0 B0
Ci,0=1
A1 B1
A2 B2
Co,0
Co,1
Co,2
Full
Full
Full
Adder =Ci,1 Adder =Ci,2 Adder =Ci,3
S0
S1
S2
AN-1BN-1
Co,N-2
=Ci,N-1
Full
Adder
Co,N-1
SN-1
A 1-Bit full-adder circuit is sufficient to construct N-bit adder
or subtractor as a simple combinational (ripple) circuit.
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Delay Time of N-Bit Ripple Adder/Subtractor
delay from carry-in
to carry-out
A B
TFCin,Cout
Cin
Full
Adder
TFCin,S S
delay from carry-in
to sum
Cout
Delay time for the carry-out
signal of the kth full adder circuit
TR Cout,k = k⋅ TFCin,Cout
Delay time for the sum signal
of the kth full adder circuit
TR S,k = (k− 1)⋅ TFCin,Cout + TFCin,S
The ripple adder/subtractor delay is proportional to
the bit-number N of the binaries used in the arithmetic.
The most important task in the design of a ripple adder/
subtractor is to minimize the delay from carry-in to carry-out.
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Implementation of the Full-Adder in Static CMOS
Straight forward Boolean equations
C out = A• B+ B• C in + A• Cin
S = A• B• Cin + A • B• C in + A • B• Cin + A• B• C in
Usage of inverting properties
for pull-up network
C out = A • B + B • Cin + A • Cin
S = A • B• Cin + C out • (A + B + Cin )
= A• B• Cin + C out • (A + B+ Cin )
Corresponding circuit
Improved corresponding circuit
(Problem: long p-MOS chains)
(Removal of 4 p-MOS transistors)
An efficient symmetric full-adder results, if different Boolean
equations for pull-up and pull-down network are used.
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Revised Boolean Equations: More Improvement
Definition of 2 Functions
depending only on A and B
Generate:
G = A• B
Propagate:
P = A+ B
Rewriting the relation between
Cout and Cin in terms of G and P
Cout = A• B+ (B+ A) • Cin
= G + P• Cin
Manchester carry chain for fast ripple-adder construction
VDD
VDD
P0
Cout,0
P1
Cout,1
P2
Pk
Cout,2
Cout,k
Cout,k
Cin,0
G0
VSS
VSS
G1
VSS
G2
VSS
Gk
VSS
VSS
Propagate and generate signals for each bit allow to
construct a fast carry-ripple chain (Manchester carry chain).
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Carry-Select-Adder Principle
Setup (Pi and Gi Calculation)
Idea
“0”
“0” Carry Propagation
“1”
“1” Carry Propagation
Cout,k
Multiplexer
Carry Vector
- Subdivide the N-bit adder into
N/i blocks
- Calculate the carry-propagation
result in each part for “0” and
“1” carry-in in parallel
- Select the correct output carry
of the block, when the correct
input-carry to the block arrives
Cout,k+i
Sum Calculation
Application of the carry-select principle results in extremely
fast combinational adders.
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Critical Delay Path of the Carry-Select Adder
Example of a 16-bit carry-select adder with 4-bit
blocks. The critical path is shown in red.
Setup
Setup
Setup
Setup
“0” “0” Carry
“0” “0” Carry
“0” “0” Carry
“0” “0” Carry
“1” “1” Carry
“1” “1” Carry
“1” “1” Carry
“1” “1” Carry
Cin,0
Mux
Sum
Cout,3
Mux
Sum
Cout,7
Mux
Cout,11
Sum
Mux
Cout,15
Sum
Delay in the general case of an N bit adder with M-bit blocks
N
τ carry−select = τ setup + M⋅ τ carry + ⋅ τ mux + τ sum
M
The block length M and the multiplexer-delay time τmux
determine the calculation speed of the carry-select adder.
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Carry-Look-Ahead Principle
Direct resolution of the recursive formula for Cout,k
k
k
C out,k = C in, 0 ∑ Pi + ∑ G j⋅
C o,k = Gk + Pk ⋅C o, k−1
i =1
j =0
k
∑P
i = j+1
i
Example of a 16-bit carry-look-ahead adder with 4-bit
blocks. The critical path is again shown in red.
Setup
Look-Ahead
Cin,0
Ripple
Setup
Cout,3
Look-Ahead
Ripple
Setup
Cout,7
Look-Ahead
Setup
Cout,11
Ripple
Ripple
Cout,15
Block length M and look-ahead-delay time τahead determine
the calculation speed of the carry-look-ahead adder.
Mattausch, CMOS Design, H20/6/6
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Circuits for Addition and
Subtraction
-
Adders for Single-Bit Binaries
Combinational Adders/Subtractors for
Multi-Bit Binaries
Sequential Adders/Subtractors for
Multi-Bit Binaries
Mattausch, CMOS Design, H20/6/6
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Bit-Serial Adder
Block diagram of a bit-serial adder
Timing of a
bit-serial adder
augend
augend
The bit-serial adder is the most area efficient adder
implementation, but latency and throughput are proportional
to the bit number n of the addend and augend binaries.
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High Throughput Carry-Ripple Sequential Adder
Ci,0=0
Clock
A0 B0
A1 B1
AN-1BN-1
Full
Adder
Full
Adder
Full
Adder
S0
S1
Co,N-1
SN-1
Throughput of sequential carry-ripple adders is independent
of bit number N, but latency increases proportional to N.
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Dynamic Sequential Carry-Ripple Adder
Carry-path and sum-calculation in
NP-domino logic
Corresponding circuit
(Problem: long p-MOS chains)
Carry Part
For further speed improvements
sum and carry calculation can be
carried out sequentially in addition
Full-Adder
Sum Part
NP-domino logic allows a high speed implementation of the
sequential carry-ripple adder.
Mattausch, CMOS Design, H20/6/6
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Circuits for Data Shifting
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Application and Principle of Shifters
programmable left-right shifter
(shift depth is one bit)
• Shifters can move all bits of a
binary by a programmable
number of k positions. kmax is
called the shift depth.
• Shifters are mainly used in
floating-point units of
processors for:
- number scaling,
- alignments
- replacement of multiplication
operations by 2k.
The implementation circuits of shifters belong to the class of
programmable path-selector circuits.
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Logarithmic Shifters
programmable logarithmic shifter
(shift depth is 0-7 bit)
Logarithmic shifters use
stages which can shift by
powers of 2.
Therefore, the bits of the
binary which determines the
shift-length can be directly
used as the control signals
of the logarithmic shifter.
Logarithmic shifting leads to very effective shifter circuits.
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