Frequency Response of Hysteretic
Comparators in Switching Converters
Dongwon Kwon and Gabriel A. Rincón-Mora
Georgia Tech Analog, Power, and Energy IC Research
March 18, 2010
Abstract
Hysteretic switching dc-dc converters are popular because they
are (i) relatively simple (i.e., self-oscillating and selfcompensating), (ii) fast (i.e., able to respond within one
switching cycle: f0dB = fSW), and (iii) robust (i.e., reliably stable).
Although the time-domain operation of a hysteretic comparator
can at times be intuitive, its ac transfer response in a switching
converter (i.e., gain and phase) is not because linearizing what is
already an inherently nonlinear circuit is difficult. This
presentation illustrates how to derive a describing (rather than
transfer) function that conveys more ac insight and shows how
the oscillator circuit ensures there is just enough phase shift
across the feedback loop to sustain oscillations (i.e., reach 180O
of phase shift at f0dB = fSW).
Page 1
Summary
Hysteretic switching converter ≡ Oscillator (i.e., fSW = f0dB = f180o);
AC Response ≡ Large Signal (i.e., loop processes fSW signal);
LC eliminates higher-than-fSW frequencies
∴ Only comparator's fSW component is relevant.
4
 4
 VDD  VDD
∆v OUT (f SW )  π 
π
Gain ≡
=
≤ 
∆v IN (f SW )
∆v IN(PP)
VHYST
Square Wave's
Fundamental
Component
Input Ripple's
Amplitude
If comparator's TDLY << TSW ∴ No in-band comparator pole;
Comparator waits for vIN to reach trip point
∴ 90O if ΔvIN = VHYST
AND
< 90O if ΔvIN > VHYST;
–FB adjusts ΔvIN (gain and phase) until oscillations are sustained.
Introduction: Problem Statement
“Hysteretic buck converters are always stable.”
[1] K. -C. Lee et al., ISSCC 2010.
[2] C. -H. Tso et al., IEEE Power Electronics Letters, Sept. 2003.
[3] J. H. Park et al., IEEE COMPEL Workshop, 2006.
• Hysteretic DC-DC Converters:
- Simple system and intuitive operation, but always stable?
- Output voltage ripple often exceeds hysteretic window, why?
- Output can ring rail-to-rail when the output impedance
lacks resistive components (e.g., RESR is low in CO) , why?
How can we explain the stability and dynamics of
hysteretic comparators in switching dc-dc converters?
Page 2
PWM Switching Converters
A PWM switching converter can be averaged
and linearized across a switching cycle.
Hysteretic Switching Converters
• No error amp, Digital output, Circuit processes frequencies near fSW:
Hysteretic comparator is difficult to linearize
(i.e., extract ac transfer function).
• It is well known that the circuit sustains oscillations at fSW, but how?
Page 3
Linearizing a Hysteretic Comparator
Observations:
1) Nonlinear block
2) TCP_IN= TCP_OUT fCP_IN(fund) = fCP_OUT(fund)
3) Gain and phase-shift relationships can be defined.
* Reference: Chestnut and Mayer, “Servomechanisms and Regulating
System Design,” New York: John Wiley & Sons, 1955.
Describing Function: Gain and Phase Shift
Gain =
Output Amplitude
Input Amplitude
4 VDD
2V
= π 2 = DD
VC
π VC
Phase − Shift = ωC t D
VH
2
 V 
ω C t D = sin−1 H 
 2 VC 
VC sin(ω C t D ) =
Page 4
Frequency Response
Bode Diagram
45
44
VC=18.5mV
43
VC=20mV
VC=22mV
Magnitude (dB)
42
VC=30mV
41
VC=40mV
40
• VH=2 × 18.5 mV
39
• Gain and phase-shift
38
37
are constant over
36
frequency, but they
35
0
change with the input
ripple (i.e., with VC).
Phase (deg)
-45
• Max Gain and phase
shift with min. input
-90
ripple: VC = VH/2.
-135
• Gain and phase shift
-180
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
decreases as input
10
ripple (VC) increases.
Frequency (Hz)
Loop-Gain Transfer Function
G(VC ) =
 V 
2 VDD
∠ sin −1 H 
π VC
 2 VC 
H(s) =
1 + sRESR CO
1 + sRESRCO + s 2L OCO
Loop-Gain = G(VC) × H(s)
Page 5
Frequency Response of the Loop-Gain
Bode Diagram
80
H(s)
60
G(18.5mV)H(s)
G(20mV)H(s)
G(22mV)H(s)
Magnitude (dB)
40
20
G(30mV)H(s)
G(40mV)H(s)
0
-20
-40
-60
-80
0
Phase (deg)
-45
-90
-135
-180
-225
-270
3
10
10
4
10
5
10
6
10
7
Frequency (Hz)
Frequency Response of the Loop-Gain (zoom in)
B ode Diagram
H(s)
G(18.5mV )H(s)
15
G(20mV)H(s)
G(22mV)H(s)
G(30mV)H(s)
Magnitude (dB)
10
5
1
0
2
-5
1
2
G(40mV)H(s)
3
-10
3
-15
-20
-90
-180
The loop changes the
amplitude and frequency of the
input ripple to ensure f0dB = f180⁰;
-225
Loop sustains oscillation;
Phase (deg)
-135
fSW = f0dB = f180⁰
-270
10
5
Frequency (Hz)
Page 6
Theory vs. Simulation
Parameters
Theoretical Estimation
Simulated Result
fSW
230 KHz
262 KHz
vOUT(Rppl)
22 mV
20 mV
* Source of Error: vOUT is not a sinusoidal waveform.
Conclusions
Hysteretic DC-DC Switching Converters:
- Sustained oscillation of vOUT about VREF f0dB = f180⁰⁰;
- Respond within 1 switching cycle f0dB = fSW;
∴ Faster than PWM counterparts.
- Hysteretic comparator is nonlinear.
Describing Function of Hysteretic Comparators:
- Linearize by analyzing fundamental frequency;
- Supply VDD fixes ΔvOUT's amplitude to a constant;
- Hysteresis delays (phase-shifts) response;
Gain and phase change with input ripple's amplitude.
Page 7