Tomasz BISKUP1, Carsten BÜHRER2, Bogusław GRZESIK1, Josien KRIJGSMAN3, Jarosław MICHALAK1,
Szymon PASKO1, Marcin ZYGMANOWSKI1
Politechnika Śląska, Zakład Napędu Elektrycznego i Energoelektroniki (1), Trithor GmbH, Reinbach, Germany (2), KEMA b.v., Arnhem,
The Netherlands (3)
Multilevel Converter for Power Conditioning System with SMES
Abstract. Multilevel converters have emerged recently as power electronic converters for high voltage and power applications. The analysis of
converter topologies and control strategies for multilevel converters enabling two-quadrant operation in power conditioning system PCS with
superconducting magnetic energy storage SMES is given in the paper. Diode-clamped, capacitor-clamped and cascaded converters are explored
and compared. Three-level diode-clamped converter with space vector pulse width modulation has been selected.
Streszczenie. Falowniki wielopoziomowe pojawiły się stosunkowo niedawno jako przekształtniki do zastosowań przy średnich napięciach oraz
wysokiej mocy. Artykuł zawiera analizę kilku topologii przekształtnika wielopoziomowego jak i sposobu jego sterowania. Analiza jest prowadzona ze
względu na przydatność przekształtnika wielopoziomowego w kondycjonerze mocy z magazynowaniem energii w cewce z nadprzewodnika. Artykuł
zawiera porównanie przekształtników wielopoziomowych: z diodami poziomującymi, z kondensatorami poziomującymi oraz falownika kaskadowego.
Keywords: multilevel converters, voltage balancing, multilevel vector PWM, power converters
Słowa kluczowe: przekształtniki wielopoziomowe, stabilizacja napięć w obwodzie pośredniczącym, wielopoziomowa metoda modulacji
szerokości impulsów, przekształtniki energoelektroniczne.
Introduction
Multilevel converters (power electronic converters) in
application to Power Conditioning Systems (PCS) are the
subject of the paper.
The selection of the best multilevel converter topology
(together with control strategy) that could operate in the
PCS is the aim of the work.
Multilevel converters can be roughly described using
Fig. 1 where the schematic diagram and a selected
waveform of the output voltage are given.
UDC
UP1
UP2
UN1
0
UN2
Converter
C
UP(n-1)/2
A
UN(n-1)/2
uA0
load
(a)
uA0
UP1
UP2
UP(n-1)/2
UN(n-1)/2+1
0
UN2
UN1
supplied by n-1 voltage sources UP1, UP2, …, UP(n-1)/2, UN1,
UN2, …, UN(n-1/)2, that are different from each other.
Equality of positive and negative voltages UP1 = UN1, …,
UP(n-1)/2 = UN(n-1)/2 is one of two conditions that should be
fulfilled in order to get symmetrical output voltage
waveform. The second condition is symmetry in the
switching times.
Power Conditioning System (PCS) is depicted in Fig. 2.
Assuming the symmetry and the lack of DC component
in the output voltage uA0 the converter C has to be supplied
by n - 1 voltage sources. The sources are different from
each other. PCS consists of two converters (AC-DC and
DC-DC) and energy storage (in this case superconducting
magnetic energy storage (SMES)). In normal state of mains
the energy is delivered from mains to (protected) load (e.g.
paper machines) while SMES (in other words inductor
LSMES) stores certain amount of energy. In case of the faults
in the mains the circuit breaker is off and the energy is
immediately drawn out from the SMES being delivered to
the load for the certain time.
PCS with SMES is highly dynamic system that starts the
transfer energy from the SMES to the protected load in time
of about 5 ms. The stored energy is enough till the
conventional source of energy is turn on (fuel cells, diesel
generator). The energy flow between mains and SMES and
between SMES and the load is maintained by converters.
It is necessary to add that the faults means voltage
sags, swells, and power interruptions. Instead of SMES
super capacitor could be used.
Multilevel
Multilevel
AC-DC Converter DC-DC Converter
(b)
Fig.1. Multilevel converter. (a) Schematic diagram of one phase
leg. (b) Output voltage waveform of n-level converter
Number of voltage levels n is the attribute of multilevel
converter. It is defined as the number of levels in output
voltage uA0 measured between output terminal A and the
neutral point 0 or negative terminal of DC link [3]. It is
explained in Fig. 7 given for n = 5.
Assuming that there is no DC component in output
voltage uA0 and uA0 is symmetric the converter C has to be
Circuit
Breaker
Filter
LAC
Cn-1
Cn-2
LSMES
Mains
(Protected)
Load
C1
Superconducting
Magnetic
Energy Storage
Fig.2. Power conditioning system PCS with multilevel converters
Apart from delivering energy to the load PCS can
operate like reactive power compensator and active filter of
higher harmonic content in currents taken from mains.
Contemporary PCSs need to be built for high rated
power and high rated energy. High power can be achieved
at high rated voltage.
The relevant rated voltage can be obtained by
application of two-level converters with transistors / GTOs
connected in series or/and by applications of transformers.
Instead of two-level converters it is possible to use
multilevel converters. Beside high rated voltage the
advantage of it is much better shape of its AC current in
comparison with AC current in two-level converters. The
AC-DC converter in this case is voltage source converter.
Having such precisely described topic one can state that
the thorough examination of (power electronic) multilevel
converters is needed. The control of the whole PCS is
outside the scope of the paper.
maximum number of levels is (4n-3). In this paper
essentially only five-level converters for PCS (Fig. 2) are
taken into consideration, with 9 levels in line-to-line voltage
and 17 levels in phase voltage. Number of voltage levels in
phase voltage is a function of modulation index.
There are three basic types of converters (topologies)
existing in the class of multilevel converters. They are:
diode-clamped converters – DCC (derived from neutralpoint clamped NPC inverter [5]), capacitor-clamped
converter- CCC (flying capacitors or multicell converter) [3],
[4], [11], and cascaded multicell converter – CMC (Hbridge) [3], [4] and [7]. All the topologies are compared in
this paper in terms of usefulness in PCS with SMES. Each
topology can operate as rectifier or inverter resulting in
different energy flow direction. All of them have the same
number of switches but use different number of capacitors
and diodes and can be controlled under different control
strategies. The control strategies are described in the
second part of this paper.
It is necessary to stress that study of literature of the
subject revealed the lack of papers reporting the results of
such research works as is presented in this paper.
The following assumptions have been made for the
analysis of AC-DC converter:
1) Multilevel converter should operate as: i) reactive
power compensator, ii) active power filter and iii) high
dynamics UPS (with SMES), iv) should be immune
against voltage sags, swells, and power interruptions.
2) Converter should maintain balanced voltages across
DC link capacitors, it means every voltage level should
be stabilized at needed level.
3) The power part of the converter should be
transformerless.
Da
Sb1
Db
Sa2
UDC
Sb2
A
Sc1
Dc
Sc2
B
D'a
C1
S 'a1
D'b
S 'b1
D'c
S 'a2
S 'b2
load
C
S 'c1
S 'c2
Fig.3. Three-phase three-level diode-clamped converter (DCC);
n=3
S1
C4
S2
D1
The work is a theoretical one basing on analysis that is
carried out using Matlab-Simulink.
The structure of the paper is as follows. It encompasses:
i) classification of multilevel converter topologies, ii) diodeclamped converter, iii) capacitor-clamped converter,
iv) cascaded multicell converter, v) comments on power
part of multilevel converters vi) classification of control
strategies, vii) selective harmonic elimination, viii) space
vector control, ix) sinusoidal pulse width modulation, x)
comments on modulation strategies and xi) conclusions.
Classification of multilevel converter topologies
The multilevel concept comes from ideas of step
approximation of sinusoid that was patented by the MIT
researcher [1], [2]. As was mentioned above multilevel
AC-DC converters have to be used when high rated voltage
is needed as well as good shape of AC current of the
converter is demanded. In multilevel converter single device
has to withstand only small part of the DC link voltage UDC.
Voltage across the switch depends on number of output
voltage levels n and is equal to UDC/(n-1), cf. Fig. 8 where
n = 5. Although it is possible to have any number of levels it
is usually limited to n = 10 [3], [4], because of the complexity
of its control.
Apart from operation at high voltage level multilevel
converters assure small dv/dt and low voltage THD. It
results in smoother AC currents. Smaller dv/dt results in low
EMI problems.
For three-phase converters number of levels in line-toline voltage and in phase voltage differs from number of
levels of output voltage. For three-phase symmetrical
converter the number of levels in line-to-line voltage is
(2n-1) but phase voltage has more levels where the
Sa1
C2
UDC
2
UDC
S3
D2
C3
0
S4
D '1
S '1 A
D3
C2
iA
load
D '2 S '
2
UDC
2
uA0
S '3
D '3
C1
S '4
Fig.4. One phase leg of five-level diode-clamped converter (DCC);
n=5
Sa1
C4
Da1
UDC
C2
C1
Sa3
Sb3
D 'a2
D 'a3
Db3
D 'b2
S 'a4
D 'b3
Sc3
Sc4
D 'c1
C
S 'c1
Dc3
D 'c2
S 'b2
S 'b3
Sc2
Dc2
S 'b1B
S 'a2
S 'a3
Dc1
Sb4
D 'b1
S 'a1A
Da3
Sc1
Sb2
Db2
Sa4
D 'a1
0
Db1
Sa2
Da2
C3
Sb1
D 'c3
S 'b4
S 'c2
S 'c3
S 'c4
Three phase load
Fig.5. Three-phase five-level diode-clamped converter (DCC)
Diode-clamped converter (DCC)
The first mention of diode-clamped converter DCC can
be found in paper [5] where authors proposed neutral point
clamped (NPC) inverter that produces three-level output
voltage Fig. 3. Multilevel diode-clamped converters based
on NPC structure instead of two pairs of switches in every
phase leg of three-level converter have n - 1 pairs of
switches cf. Fig. 4 and Fig. 5. Switches S1-S’1, S2-S’2, ... are
complementary.
Turned on transistor caused that the voltage from
related capacitor is connected to the output. Diodes have to
block capacitors when greater voltage is at output terminal.
This means that voltage across every diode is equal to
UDC/(n-1).
Because there are n-1 complementary switch pairs in
every phase leg they can be switched on/off in (n-1)2
manners. Only n switching states allow generating output
voltage by connecting AC load to DC link capacitors. For
n = 5 these states are depicted in Fig. 6 with indication of
corresponding current paths in one phase leg for both
current direction flows.
uA0 =UDC/2
1
Switch
states
6
uA0 =UDC/4
2
1111
uA0 = 0
3
0111
7
uA0 =-UDC/4
4
0011
8
uA0 =-UDC/2
5
0001
9
0000
10
Fig.6. Equivalent circuits for five states of upper switches of one
phase leg of diode-clamped converter; n = 5
Fig.7. Capacitor voltages for three-phase diode-clamped converter
with AC resistive-inductive load under PWM control; n = 5
(simulation for: R = 10 Ω, L = 100 mH, C = 1 mF, fm = 50 Hz,
UDC = 200 V)
The converter directly connected to the DC link, with AC
resistive-inductive load, draws currents from certain
capacitors that cause capacitor voltage unbalance. In other
words the capacitor voltages are not balanced when AC
load draws from converter real power. It can be observed in
Fig. 7 where waveforms of capacitor voltages are given.
The behavior of voltage unbalancing can be explained
using Fig. 6 where current paths are presented.
Assuming that the AC load is pure resistive capacitor
voltages change their value in states 2 and 9, that is when
output voltage is equal to ¼ UDC or -¼ UDC. For state 2
(uA0=¼ UDC) current flowing through capacitor C4 is greater
than current of C3, C2 and C1 because serial connection of
three capacitor give smaller capacitance. All four capacitors
are connected to the DC link voltage UDC, thus any increase
in voltage at one capacitor is connected with the decrease
in voltage across the other capacitors. If current of C4 is
greater it means that voltage across that capacitor is
increasing more than across other capacitors, C3, C2 C1. In
states 3 or 8 (uA0 = 0) currents of C4, C3 are equal to the
currents of C2, C1 and their values are zero. For state 9
(uA0 = -¼ UDC), symmetrical in relation to state 2, current
changes its direction and flows to the converter leg and
then it spreads out through capacitors. In this case the
greater current flows through C1 increasing its voltage. That
is why voltages across C1 and C4 increase and voltages
across C2, C3 decrease at every cycle. One can observe
that sum of that capacitor voltages is equal to UDC.
In Fig. 8 waveforms of output voltage are given for
unbalanced capacitor voltages (the same conditions like in
Fig. 7). One can observe a decrease in medium level
voltages.
The same mechanism of unbalancing capacitor voltages
is in three-phase converter. It can be observed and
analyzed assuming that the voltage of common point of
three-phase load (wye connection) has approximately the
same potential as neutral point 0.
Different situation takes place for pure reactive power
drawn from inverter AC output (reactive power
compensator). Here the current is always shifted with
respect to output voltage by ± π/2. Output voltage of every
converter topology with any controller is even-symmetrical
with regard to π/2 and odd-symmetrical in relation to 0 and
π. In this case reactive current flows from/to converter
causing that average (over the period) current of each
capacitor is equal to 0 - Fig. 9 (where iA is averaged or
fundamental component). For example in state 2 that lasts
the same time as state 7 current is positive and capacitor C4
is charged but in state 7 current has the same value but is
negative and capacitor C4 is discharged – average value of
capacitor current is 0.
Fig.8. Unbalanced output voltage of five-level diode-clamped
converter; n = 5, the same conditions like in Fig. 7 (simulation)
uA0
UDC
2
π iA
2
0
ωt
π
8
7
6
1
2
3
4
5
10
9
8
Fig.9. One phase leg of diode-clamped converter: output voltage
and pure output reactive current with switching states (Fig.6); n = 5
In case the converter operates as rectifier converting AC
real power into DC power the unbalance of capacitor
voltages is different in comparison with that given in Fig. 7.
uC1, uC4 are decreasing while uC2, uC3 are increasing.
Therefore it is obvious that five-level diode-clamped
converter itself cannot cope with real power conversion
because unbalancing of capacitor voltages occurs. The
three-level DCC is the only converter, which allows
balancing capacitor voltages for AC real power. It can be
obtained by application the control strategy basing on
redundant converter vectors [13].
There is no control strategy that can maintain balancing
capacitor voltages for AC real power when the number of
voltage levels is higher than three. It means there is no
control strategy that meet assumed demands.
Beside the three-level balanced solution there are two
other solutions applicable to the converters of higher
number of levels allowing to keep capacitor voltages
balanced.
First solution is based on the back-to-back connection of
two multilevel converters (necessarily with the same
number of levels). Back-to-back connection allows keeping
the voltage at each capacitor close to UDC/(n-1) by using
one converter to generate output voltage and second
converter to balance capacitor voltages [14].
Although PCS is composed of two converters and it seems
that the solution [14] can be applied in this case the details
of PCS reveals difficulty. They come from specific features
of SMES coil that has to be kept short-circuited after being
loaded till the time its energy is needed by the load. Actually
it is impossible to use SMES energy for balancing capacitor
voltages. It means that back-to-back connection is not the
candidate for PCS application when n > 3.
Balancing of capacitor voltages can also be achieved by
application of multiple winding transformers with rectifiers,
each of which supplies its own capacitor. But this solution is
bulky in comparison with transformerless one. Therefore
this solution is also not the one that can be applied in PCS.
C
S1
3UDC 3
S1
4
UDC
UDC C2
2
2
UDC
4
0
UDC
iC1
S3
C1
S4
A
iC2
2
iC3
UDC
0
iA
S '1
UDC
S2
S3
S4
C2
UDC
UDC
2
3UDC
C1
4
S2
load
S '2
C3
4
iC3
iC2
S '4
S '3
A
iC1
S '2
S '1
paths for different switching states are presented in
Fig. 12a. In Fig. 12b one can observe the switching states
and capacitor currents of one phase leg of CCC. A given
voltage level can be obtained in many different states, e.g.,
uA0 = UDC/4 can be generated by four states, 2-5.
Unlike diode-clamped converter this structure can
produce output voltage in every switching state of 2n-1
possible states. As is stated in Fig. 12b the clamping
capacitor voltages can be charged or discharged depending
on switching state, output current value and its direction.
Because there are few redundant switching states that can
produce the same output voltage level these redundant
switching states can be utilized to balance voltages of
clamping capacitors.
Sa1
Sb1
Sa2
Ca3
Ca3
UDC
Sb2
Cb3
Sa3
Ca2
Ca1
Ca2
Ca3
Sc1
Sb3
Cb2
Sa4
Cb3
S 'a2
Cc3
S 'c1
Cc3
S 'b2
Sc4
Cc1
Cc2
S 'b1
Cb3
Sc3
Cc2
Sb4
Cb1
Cb2
S 'a1
Sc2
Cc3
S 'c2
S 'a3
S 'b3
S 'c3
S 'a4
S 'b4
S 'c4
Three-phase load
Fig.11. Three-phase five-level capacitor-clamped converter (CCC)
Capacitor-clamped converter has to utilize different
control strategy compared to DCC because there exist
more switching states than in DCC counterpart. The most
suitable control strategy that can balance all clamping
capacitors [12] is phase-shifted carrier PWM within limits of
load angles -π/2 > φ > π/2. It is presented later in this paper.
Clamping capacitor voltages are self-balanced, what means
that any disturbance that can occur to these voltages will be
lessened with time. The number of levels does not influence
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
iA
uA0
load
uA0
S '3
S '4
Fig.10. Different arrangements (and names) of one phase leg of
five level capacitor-clamped converter (CCC); (a) Flying capacitor
converter. (b) Multicell converter [11]
Capacitor-clamped converter (CCC)
Second multilevel topology is capacitor-clamped
converter, CCC also known as flying capacitor or multicell
converter [11]. Its structure is presented in Fig. 10 – one
phase leg and Fig. 11 – three-phase converter. Voltage
across every clamping capacitor has the same value equal
to UDC/(n-1). In case of series connection of clamping
capacitors voltage across clamping capacitor branch is a
multiple of UDC/(n-1) (e.g. voltage across C3 is equal to
3UDC/4). In contrast to DCC the complementary switch pairs
in CCC are S1-S’4, S2-S’3, ..., S4-S’1. Turning switches on
allows connecting relevant clamping capacitors in series,
what can generate the multilevel output voltage. Current
(a)
uA0
UDC/2
No. of switch state
1
1
1
1
1
0
0
0
Sa1 i S'a1
Sa2 i S'a2
Sa3 i S'a3
Sa4 i S'a4
iCa1
iCa2
iCa3
0
UDC/4
2
0
1
1
1
0
0
3
1
0
1
1
0
4
1
1
0
1
5
1
1
1
0
6
0
0
1
1
0
0
0 0 0
7
0
1
0
1
8
0
1
1
0
-UDC/4
9
1
0
0
1
10 11 12 13 14 15
1 1 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
0 0 1 0 0 0
0
0 0
0 0
0
0
0 0 0
-UDC/2
16
0
0
0
0
0
0
0
(b)
Fig.12. Switching states and capacitor currents directions for output
current drawn from converter; for switch state: ‘0’ – switch is off, ‘1’
– switch is on, for currents: +/- – current increases/decreases
capacitor voltage; ‘0’ means capacitor voltage is not changed
on balancing capacitor voltages. As is stated in [12], the
time constant describing voltage regain depends on
capacitance of clamping capacitors, modulation index, load
impedance and load angle. The most important fact is that,
the greater load angle the longer time is needed to regain
capacitor voltages. For load angles equal ±π/2, this time
constant is infinity. In other words it could be stated that
CCC cannot operate with output current angles shifted by
±π/2 with regard to output voltage what means that
operation of CCC as reactive power compensator is not
allowed. This is the main drawback of the CCC. The steady
state behavior of the converter with load angle of 1.26,
under phase-shifted carrier PWM is depicted in Fig. 13.
Fig.13. Balanced output voltage uA0 of five-level capacitor-clamped
converter (Fig. 9) with phase-shifted carrier method. (simulation
carried out with R = 10 Ω, L = 100 mH, C = 1 mF, fm = 50 Hz,
UDC = 200 V)
Ua1
Ua2
Ub1
Uc1
uA
uB
Ub2
Uc2
uC
Second control strategy that could be applied to threephase CCC is the method based on space vector
modulation that utilizes lookup tables. Selecting switching
states has to take into account balancing clamping
capacitor voltages. To perform this condition measuring of
clamping capacitor voltages and output currents are
demanded. The main drawback of this method is large
number of switchings and complexity of controls.
The clamped-capacitor multilevel converter is not the
one that can be applied in PCS that has to operate like
reactive power compensator.
Cascaded converter with separate DC sources (CMC)
The third type of multilevel converter is cascaded one
with separate DC sources. The topology is given in Fig. 14
where DC sources can be connected to each other in series
through two-level converters.
The n-level converter needs to use (n-1)/2 separate DC
sources. Five-level converter with two separate sources and
its output voltage waveform and current paths is presented
in Fig. 15. Each voltage level numbered from 1 to 6
corresponds to exact state of all converter switches. Current
paths give information about conducting switches for both
current directions.
The CMC needs to use separate DC sources what
means that for PCS application it is demanded to use
multiple winding transformer that can produce separate
voltages. It results in stable voltage of each level. The
topology is also bulky like DCC with capacitor stabilized
voltages since transformer has to be used.
The topology is the most promising for automotive
applications and in energy systems that use alternative
energy sources such as photovoltaic batteries or fuel cells
is cascaded multicell converter [3], [7] or even SMES.
Cascaded inverters with capacitors can operate only for
reactive loads (or for active power filtering where no real
power is demanded).
Concluding, the topology also does not meet demands
assumed for PCS, because transformers are needed.
0
b
Three-phase load
Fig.14. Three-phase five-level cascaded converter with separate
DC sources
U1+U2
U1
U2
1
A
vref
0
2
a
3
iA
uA0
U2
0
-U1
4
0
-U1-U2
5
6
(a)
Fig.16. Space vector pulse width modulation (SVPWM) for fivelevel converter, vector distribution and rotating reference vector vref
(b)
uA0
π
2
0
8
2
π
1
2
3 4
ωt
5
6
5
c
4
(c)
Fig.15. One phase leg of five-level cascaded multicell converter
(CMC). (a) Structure. (b) current paths. (c) Output voltage
waveform
Control strategies
The control strategies are discussed briefly since there
is only one that is suitable for PCS.
There are four main control strategies applied to
multilevel converters [3] divided into two groups:
i) fundamental switching frequency, FSFM [6], [7],
• selective harmonic elimination, SHE,
• space vector control, SVC [10].
ii) higher switching frequency, HSF-PWM [8], [9].
• sinusoidal pulse width modulation, SPWM,
• space vector pulse width modulation, SVPWM.
Analysis of control strategies results in conclusion that
SVC and SVPWM are the best solutions for PCS
application. SVC is applicable for higher number of levels
but SVPWM is more suitable for small number of levels.
Space vector pulse width modulation (SVPWM)
The method can be described using Fig. 16. This
modulation method is similar to SVPWM of two-level
inverter but the number of values of space vector depends
on the number of output voltage levels and is much higher
than in two-level one. The needed vector is synthesized by
averaging adjacent three vectors. Its value is taken from a
certain triangle, such as depicted in Fig. 16. All possible
vectors are indicated in this figure. It is necessary to add
that the given vector can be produced in several switching
states.
This control strategy has following advantages [3]:
allows balancing of capacitor voltages, results in low current
ripple, permits for relatively easy hardware implementation
by a digital signal processor.
Comments on power part of multilevel converters
Summing up all mentioned features can be seen that
first mentioned topology DCC has following advantages and
following disadvantages:
Advantages of this topology are i) only n-1 bulky capacitors
are used, ii) reactive power can be controlled.
Disadvantages are i) keeping capacitor voltages at certain
level for converter with n>3 is difficult, ii) many diodes are
used.
The second topology CCC presents more interesting
features and it has following advantages: i) there is no
problem of unbalanced capacitor voltages, ii) reactive and
real power flow can be controlled, iii) many capacitor has
additional energy that can be used for occurred faults
(outages) in the mins. Disadvantages are i) great number of
bulky and costly capacitors, ii) complex control needed
when measuring of capacitor voltages exists.
Third topology CMC uses separate DC sources what is
the major drawback in PCS application because it needs to
use heavy multiple winding transformer. Although CMC is
very promising topology for other applications and it needs
the smallest number of parts it was not taken into
consideration for choosing the multilevel converter for
power conditioning system.
The first topology, although has unbalanced voltage
problem, can operate in PCS application by using back-toback connection. In that case AC-DC converter is
composed of three phase-legs and DC-DC converter
consists two phase-legs.
Authors deem CCC as the most fitted converter
topology to PCS. This choice was dictated by self-balancing
property and greater freedom of selecting proper switching
state.
Conclusions
1. Selecting the best multilevel topology is difficult because
all three topology has different advantages and drawbacks
when are used in PCS. These features are observed only at
particular operation modes what shows that there is no one
that is the best solution for PCS.
2. Nevertheless the three-level diode-clamped converter
with space vector pulse width modulation (SVPWM) is the
best candidate for AC-DC converter for PCS with SMES.
The PCS system has to operate as UPS of high dynamics,
reactive power compensator and as active power filter.
3. The DC-DC converter has to be two-level one because
the shape of the DC voltage of SMES is to be ±UDC.
4. The possibility of application of capacitor-clamped
converter (especially with n > 3) has to be thoroughly
examined from the point of view of application in PCS.
Remark
This paper is a result of the research work carried out in the framework
of EU project - HIPOLITY (5th FP).
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Autorzy: mgr inż. Marcin Zygmanowski, Politechnika Śląska,
Zakład
Energoelektroniki
i
Napędu
Elektrycznego,
ul.
Krzywoustego 2, 44-100 Gliwice, e-mail: mzyg@polsl.gliwice.pl; dr
hab. inż. Bogusław Grzesik, Zakład Energoelektroniki i Napędu
Elektrycznego, ul. Krzywoustego 2, 44-100 Gliwice, e-mail:
grzesik@polsl.gliwice.pl