Hardware-Software Implementation With Model-Based
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® ® Sudhir Sharma Product Manager, HDL Code Generation And Verification The MathWorks © 2007 The MathWorks, Inc. Hardware-Software Implementation With Model-Based Design ® ® Agenda What is the System Design Challenge Solutions for Embedded Software Development Automatic Code Generation Verification Solutions for Hardware Development Automatic Code Generation Verification 2 ® ® System design to implementation gap Algorithm Algorithm and and System System Design Design HDL C MCU DSP FPGA ASIC 3 ® ® Integrated Design Flow for Embedded Software and Hardware Verify the software implementation against the system model Verify the hardware implementation against the system model Simulink Simulink HDL HDL Coder Coder Co-simulation links Co Co-simulation links Generate Automatically generate production software for embedded processors Real-Time Workshop Real Real-Time Workshop Embedded Embedded Coder, Coder, Targets, Links Targets, Links Generate MATLAB MATLAB®® and and Simulink Simulink®® Algorithm Algorithm and and System System Design Design HDL C MCU Verify Design, simulate, and validate system models and algorithms in MATLAB and Simulink Verify DSP FPGA ASIC 4 ® ® Case Study: Sobel Edge Detection Algorithm 5 ® ® Floating-Point System Specification Start by developing a golden specification 6 ® ® Fixed-Point Modeling Floating-point model Fixed-point model 7 ® ® Fixed-Point Modeling Floating-point model Fixed-point model 8 ® ® Implementation on DSP, GPP, or an FPGA? Fixed-point model 9 ® ® Agenda What is the System Design Challenge Solutions for Embedded Software Development Automatic Code Generation Verification Solutions for Hardware Development Automatic Code Generation Verification 10 ® ® Implementation on DSP and GPP Fixed-point model Code generation options and preferences Select target or flavor of generated code 11 ® ® Code Execution on Target and Profiling Build and execute Auto-generate ‘C’ and ASM Integrate RTOS and scheduler Create full CCS project Invoke compiler, linker, and download code Run on target Profile code performance System System profiling profiling includes entire DSP application code Subsystem profiling 12 ® ® Design Verification and Visualization: Simulink as verification test bench Processor Processor and and hardware-in-thehardware-in-theloop loop testing, testing, simulation, simulation, visualization, visualization, and and verification verification of of embedded embedded software software with with Simulink Simulink Simulink test bench Device or design under test (DUT) Simulink system design embedded on DSP 13 ® ® Review: Code Generation for Embedded Software Code Generation Real Time Workshop – ANSI/ISO C code for rapid prototyping, acceleration Real Time Workshop Embedded Coder – Embedded deployment Links Link for Altium TASKING ! Link for Analog Devices VisualDSP++ New Link for TI Code Composer Studio Targets Target for TI C6000 DSP Target for TI C2000 DSP Target for Infineon C166 Microcontrollers Target for Freescale MPC5xx Microcontrollers 14 ® ® Agenda What is the System Design Challenge Solutions for Embedded Software Development Automatic Code Generation Verification Solutions for Hardware Development Automatic Code Generation Verification 15 ® ® Code Generation for Hardware Simulink HDL Coder Correct-by-construction VHDL and Verilog code Generated Verilog code Simulink data path Stateflow control logic 16 ® ® Fixed-Point Implementation on an FPGA Floating-point model Fixed-point model Hardware specific model 17 ® ® Design Space Exploration Speed How fast can this design run? Area Can I use a smaller chip? Power Can I target a mobile device? Implementation Alternatives Sum & Product: Linear, Cascade, and Tree Gain: Multiplier, CSD, Factored-CSD Minimum/Maximum: Tree and Cascade Lookup Table: Inline or hierarchical 18 ® ® Code Generation Options Select subsystem, target language, directory Select output options Check model for errors Generate HDL Code 19 ® ® More Code Generation Options Select reset and clock options Set language-specific options: input/output datatypes, timescale directives, … 20 ® ® Generate HDL Test Bench Self-checking HDL test bench compares Simulink results to HDL results 21 ® ® Automatic HDL Code Generation ‘Correct-by-construction’ Matches Fixed-Point System Model Faster design implementation Reduces verification burden Benefits Include: 1 Rapid FPGA implementation Automatic Automatic HDL HDL 2 Reference code for HDL engineers Automatic Automatic HDL HDL Hand Hand Customized Customized HDL HDL Co-Simulate Co-Simulate 22 ® ® Verification with system specification Link for ModelSim 23 ® ® Making full use of the system model Promotes parallelism in design and verification tasks Improves focus on critical areas Verify Verify Interfaces Interfaces System System metrics metrics 24 ® ® Making full use of the system model Promotes parallelism in design and verification tasks Improves focus on critical areas Accelerates verification at all levels 25 ® ® Making full use of the system model Promotes parallelism in design and verification tasks Improves focus on critical areas Accelerates verification at all levels Supports re-use and “what-if” scenarios 26 ® ® Implementation on an FPGA 27 ® ® Review: Code Generation for Hardware Code Generation w! Simulink® HDL Coder – FPGA and ASIC deployment using VHDL Ne and Verilog Filter Design HDL Coder – Filter implementation from MATLAB Links Link for Mentor ModelSim ! Link for Cadence® Incisive® New 28 ® ® Summary Simulink SimulinkHDL HDLCoder Coder Link for ModelSim® ® ModelSim Link for ModelSim® ®®Incisive®® Link for Cadence Link for Cadence Incisive Generate HDL C MCU Verify Real-Time Workshop Real Real-Time Workshop Embedded EmbeddedCoder, Coder, Targets, Targets,Links Links Generate Accelerate product development using Model-Based Design MATLAB MATLAB®® and and Simulink Simulink®® Algorithm Algorithm and and System System Design Design Verify Design and verify software and hardware from MATLAB and Simulink DSP FPGA ASIC 29
