PRELIMINARY TECHNICAL DATA
a
1
µmIsolation™
HIGH-SPEED DIGITAL ISOLATOR
ADuM1100AR/ADuM1100BR
DESCRIPTION
PRELIMINARY TECHNICAL DATA
FEATURES
• High Data Rate: DC – 100 Mbps (NRZ)
• Compatible with 3.3/3.3V or 5.0/5.0V Operation
• Low Power Operation
5V Operation: 0.9 mA max. @1 Mbps,
4.2 mA max. @25 Mbps,
16.8 mA max. @100 Mbps
3.3V Operation: 0.4 mA max. @1 Mbps,
3.2 mA max. @25 Mbps,
12.4 mA max. @100 Mbps
• Small Footprint: Standard 8 Lead SO package
• High Common Mode Transient Immunity:
>25kV/µS
• No Long Term Wearout
• Safety and Regulatory Approvals (Pending)
UL Recognized
2500 Vrms for 1 min. per UL 1577
CSA Component Acceptance Notice #5
VDE 0884
VIORM = 560 Vpeak
The ADuM1100AR and ADuM1100BR are digital
isolators based on Analog Devices’ µmIsolation
(micromachined isolation) technology. Combining
high-speed CMOS and monolithic air core transformer
technology, these isolation components provide
outstanding performance characteristics superior to
alternatives such as optocoupler devices.
Configured as pin-compatible replacements for
existing high-speed optocouplers, the ADuM1100AR
and ADuM1100BR support data rates as high as 25
Mbps and 100 Mbps, respectively.
Both the ADuM1100AR and ADuM1100BR operate at
either 3.3V or 5V supply voltages, boast propagation
delay of <18ns and edge asymmetry of <2 ns (at 5V
operation). They operate at very low power, less than
0.9 mA of quiescent current (sum of both sides) and a
dynamic current of less then 170 µA per Mbps of data
rate. Unlike common transformer implementations,
the ADuM1100 provides DC correctness with a
patented refresh feature that continuously updates the
output signal.
APPLICATIONS
•
•
•
•
•
Digital Fieldbus Isolation
Opto-Isolator Replacement
Computer-Peripheral Interface
Microprocessor System Interface
General Instrumentation and Data Acquisition
Applications
FUNCTIONAL BLOCK DIAGRAM
VDD1
1
VI
(Data In)
2
VDD1
3
E
N
C
O
D
E
UPDATE
GND1
D
E
C
O
D
E
8
VDD2
7
GND2
6
VO
(Data Out)
5
GND2
WATCHDOG
4
For principles of operation, see application note “Method of Operation, DC Correctness, and Magnetic Field Immunity.”
VI,
Input
H
L
X
X
VDD1
State
Powered
Powered
Unpowered
Powered
TRUTH TABLE (POSITIVE LOGIC)
VDD2
VO,
Note
State
Output
Powered
H
Powered
L
Powered
H
VO returns to VI state within 1 µsec of power restoration
Unpowered
X
VO returns to VI state within 1 µsec of power restoration
Protected by U.S. patent 5,952,849. Additional patents are pending.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
2
ADuM1100AR/ADuM1100BR
Ordering Information
Model
Temperature
Range
-40°C to +100°C
-40°C to +100°C
ADuM1100AR-REEL
ADuM1100BR-REEL
Max. Data
Rate (Mbps)
25
100
Min. Pulse
Width (nsec)
40
10
Package
Description
13” Reel 8-Lead SOIC
13” Reel 8-Lead SOIC
Package
Option
R-8
R-8
Pin Configuration (SOIC)
VDD1*
1
VDD1*
GND1
8 VDD2
ADuM 1100
7 GND2**
TOP VIEW
3
6 VO
(Not to Scale)
VI 2
4
5 GND2**
* Pin 1 and Pin 3 are internally connected. Either or both may be used for VDD1.
** Pin 5 and Pin 7 are internally connected. Either of both may be used for GND2.
Solder Reflow Thermal Profile
(JEDEC Standard No. 22a)
275
250
235° C min.
240° C max.
360 sec. max.
Temperature
225
3° C/sec. max.
6° C/sec. max.
200
183° C
175
150
125
10 sec. min.
20 sec. max.
60 sec. min.
120 sec. max.
100
75
50
25
Time
Regulatory Information
The ADuM1100AR/BR will be approved by the following organizations upon product release:
UL
To be recognized under 1577
component recognition program
CSA
To be approved under CSA
Component Acceptance Notice #5
VDE
To be approved according to VDE
0884
Insulation and Safety Related Specifications
Parameter
Minimum External Air Gap
(Clearance)
Minimum External
Tracking (Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
Symbol
L(I01)
L(I02)
CTI
Value
4.90
min.
4.01
min.
0.016
min.
> 175
Units
Conditions
mm Measured from input terminals to output
terminals, shortest distance through air.
mm Measured from input terminals to output
terminals, shortest distance path along body.
mm Insulation distance through insulation.
Volts DIN IEC 112/VDE 0303 Part 1
IIIa
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Material Group (DIN VDE 0110,1/89,Table 1)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
3
ADuM1100AR/ADuM1100BR
VDE 0884 Insulation Characteristics
Description
Installation classification per DIN VDE 0110
for rated mains voltage <= 150Vrms
for rated mains voltage <= 300Vrms
for rated mains voltage <= 400Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b
Symbol
Characteristic
Units
VIORM
VPR
I- IV
I- III
I- II
40/100/21
2
560
1050
Vpeak
Vpeak
VPR
840
Vpeak
VTR
4000
Vpeak
TS
IS, INPUT
IS,OUTPUT
Rs
150
160
170
>109
°C
mA
mA
Ω
VIORM x 1.875 = VPR, 100% Production Test,
tm = 1sec, Partial Discharge < 5pC
Input to Output Test Voltage, Method a
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5pC
Highest Allowable Over-Voltage
(Transient Over-voltage, tTR =10 sec)
Safety-limiting values (Maximum value allowed in the event
of a failure, also see Thermal Derating Curve, Figure 5)
Case Temperature
Input Current
Output Current
Insulation Resistance at Ts, VIO = 500V
This isolator is suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety date shall be ensured by means of protective circuits.
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltages
Input Voltage
Output Voltage
Average Output Current
ESD (Human Body Model)
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
VDD1,2
VI
VO
IO
Min.
-55
-40
-0.5
-0.5
-0.5
-2.0
Max.
125
100
6.5
VDD1+ 0.5
VDD2+ 0.5
25
2.0
Units
°C
°C
V
V
V
mA
KV
Note
1
See Solder Reflow Temperature Profile Section
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation
of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination.
Ambient temperature = 25 °C unless otherwise noted.
Recommended Operating Conditions
Parameter
Operating Temperature
Supply Voltages
Logic High Input Voltages, 5V operation
Logic Low Input Voltages, 5V operation
Logic High Input Voltages, 3.3V operation
Logic Low Input Voltage, 3.3V operation
Input Signal Rise and Fall Times
Symbol
TA
VDD1,2
VIH
VIL
VIH
VIL
Min.
-40
3.0
2.0
0.0
1.5
0.0
Max.
100
5.5
VDD1
0.8
VDD1
0.5
1.0
Units
°C
V
V
V
V
V
ms
Fig.
Note
3,4
1, 2
1, 3
See application note “Method of Operation, DC Correctness, and Magnetic Field Immunity” and Figure 12 for information on immunity to external magnetic fields.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
4
ADuM1100AR/ADuM1100BR
Electrical Specifications, 5V Operation
4.5V ≤ VDD1 ≤ 5.5V, 4.5V ≤ VDD2 ≤ 5.5V. All Min/Max specifications apply over the entire recommended operation range unless
otherwise noted. All typical specifications are at TA = 25 °C, VDD1 = VDD2 = +5V.
Parameter
DC Specifications
Symbol
Input Supply Current
Output Supply Current
Input Supply Current
(25 Mbps)
Output Supply Current
(25 Mbps)
Input Supply Current
(100 Mbps)
Output Supply Current
(100 Mbps)
Input Current
Logic High Output
Voltage
Logic Low Output
Voltage
Typ.
Max.
Units
Test Conditions
I DD1(Q)
I DD2(Q)
I DD1(25)
0.5
0.02
2.7
0.8
0.06
3.5
mA
mA
mA
VI = 0V or VDD1
VI = 0V or VDD1
12.5 MHz logic signal freq.
1
I DD2(25)
0.5
0.7
mA
12.5 MHz logic signal freq.
2
I DD1(100)
10.5
14
mA
1
I DD2(100)
2.0
2.8
mA
0.01
5.0
4.6
0.0
0.04
0.4
10
µA
V
0.1
0.1
0.8
V
V
V
50 MHz logic signal freq.,
ADuM1100B only
50 MHz logic signal freq.,
ADuM1100B only
0 ≤ VIN ≤ VDD1
IO = -20 µA, VI = VIH
IO = -4 mA, VI = VIH
IO = 20 µA, VI = VIL
IO = 400 µA, VI = VIL
IO = 4 mA, VI = VIL
40
ns
Mbps
CL= 15pF,
CMOS signal levels
5
6
II
VOH
Min.
-10
VDD2 - 0.1
VDD2 – 0.8
VOL
Fig. Note
2
4
4
Switching Specifications
For ADuM1100A:
Minimum Pulse Width
PW
Maximum Data Rate
For ADuM1100B:
Minimum Pulse Width
PW
Maximum Data Rate
For ADuM1100A and ADuM1100B:
Propagation Delay Time
tPHL
to Logic Low Output
Propagation Delay Time
tPLH
to Logic High Output
Pulse Width Distortion,
PWD
|tPLH-tPHL|
Propagation Delay Skew
tPSK1
25
6.7
150
10
100
ns
Mbps
CL= 15pF,
CMOS signal levels
5
6
8
12
18
ns
CL= 15pF,
CMOS signal levels
7, 9
8
12
18
ns
0.5
2
ns
7
ns
6
ns
8, 9
(constant temperature)
Propagation Delay Skew
tPSK2
(constant temperature,
supplies)
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Common Mode Transient
Immunity at Logic High
Output
Common Mode Transient
Immunity at Logic Low
Output
Input Dynamic Power
Dissipation Capacitance
Output Dynamic Power
Dissipation Capacitance
tR
tF
|CMH|
25
3
3
35
ns
ns
kV/µS
|CML|
25
35
kV/µS
CPD1
40
pF
CPD2
8
pF
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
VI = VDD1, VO > 0.8VDD1,
VCM = 1000V, transient
magnitude = 800V
VI = 0, VO < 0.8V,
VCM = 1000V, transient
magnitude = 800V
10
11
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
5
ADuM1100AR/ADuM1100BR
Electrical Specifications, 3.3V Operation
3.0V ≤ VDD1 ≤ 3.6V, 3.0V ≤ VDD2 ≤ 3.6V. All Min/Max specifications specifications apply over the entire recommended operation
range unless otherwise noted. All typical specifications are at TA = 25 °C, VDD1 = VDD2 = +3.3V.
Parameter
DC Specifications
Symbol
Input Supply Current
Output Supply Current
Input Supply Current
(25 Mbps)
Output Supply Current
(25 Mbps)
Input Supply Current
(100 Mbps)
Output Supply Current
(100 Mbps)
Input Current
Logic High Output
Voltage
Logic Low Output
Voltage
Typ.
Max.
Units
Test Conditions
I DD1(Q)
I DD2(Q)
I DD1(25)
0.2
0.02
2.1
0.3
0.06
2.8
mA
mA
mA
VI = 0V or VDD1
VI = 0V or VDD1
12.5 MHz logic signal freq.
1
I DD2(25)
0.3
0.4
mA
12.5 MHz logic signal freq.
2
I DD1(100)
8.5
10.8
mA
1
I DD2(100)
1.2
1.6
mA
0.01
3.3
3.0
0.0
0.04
0.3
10
µA
V
0.1
0.1
0.4
V
V
V
50 MHz logic signal freq.,
ADuM1100B only
50 MHz logic signal freq.,
ADuM1100B only
0 ≤ VIN ≤ VDD1
IO = -20 µA, VI = VIH
IO = -2.5 mA, VI = VIH
IO = 20 µA, VI = VIL
IO = 400 µA, VI = VIL
IO = 2.5 mA, VI = VIL
40
ns
Mbps
CL= 15pF,
CMOS signal levels
5
6
II
VOH
Min.
-10
VDD2 - 0.1
VDD2 - 0.4
VOL
Fig. Note
2
4
4
Switching Specifications
For ADuM1100A:
Minimum Pulse Width
PW
Maximum Data Rate
For ADuM1100B:
Minimum Pulse Width
PW
Maximum Data Rate
For ADuM1100A and ADuM1100B:
Propagation Delay Time
tPHL
to Logic Low Output
Propagation Delay Time
tPLH
to Logic High Output
Pulse Width Distortion,
PWD
|tPLH-tPHL|
Propagation Delay Skew
tPSK1
25
6.7
150
10
100
ns
Mbps
CL= 15pF,
CMOS signal levels
5
6
10
18
28
ns
CL= 15pF,
CMOS signal levels
7, 9
10
18
28
ns
1
4
ns
14
ns
12
ns
8, 9
(constant temperature)
Propagation Delay Skew
tPSK2
(constant temperature,
supplies)
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Common Mode Transient
Immunity at Logic High
Output
Common Mode Transient
Immunity at Logic Low
Output
Input Dynamic Power
Dissipation Capacitance
Output Dynamic Power
Dissipation Capacitance
tR
tF
|CMH|
15
4
2
20
ns
ns
KV/µS
|CML|
15
20
KV/µS
CPD1
33
pF
CPD2
5
pF
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
VI = VDD1, VO > 0.8VDD1,
VCM = 1000V, transient
magnitude = 800V
VI = 0, VO < 0.8V,
VCM = 1000V, transient
magnitude = 800V
10
11
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
6
ADuM1100AR/ADuM1100BR
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage
Resistance (Input-Output)
Capacitance (Input-Output)
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
Symbol
Min.
VISO
2500
Typ. Max. Units
VRMS
RI-O
CI-O
CI
θjci
1012
1
4.0
46
Ω
pF
pF
°C/W
θjco
41
°C/W
PPD
240
Test Conditions
Note
RH < 50%, t = 1 min.,
TA = 25°C
12, 13
12
f = 1 MHz
14
Thermocouple located
at center underside of
package
mW
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
All voltages are relative to their respective ground.
VDD1 and VDD2 must be kept within 1V of each other (|[VDD1 – GND1] – [VDD2 – GND2]| < 1V).
Input switching thresholds have 300 mV of hysteresis.
Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an
output load is present is given by: IDD2(L)=IDD2+VDD2*f*CL, where IDD2 is the unloaded output supply current, f is the input signal
frequency, and CL is the output load capacitance.
The minimum pulse width is the shortest pulsewidth at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
tPHL propagation delay is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge
of the VO signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VI signal to the 50% level of
the rising edge of the VO signal.
tPSK is the magnitude of the worst case difference in tPHL and/or tPLH that will be measured between units at the same operating
temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst case difference
in tPHL and/or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions
Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typcial input signals, the measured
propagation delay and pulsewidth distortion may be affected by slow input rise/fall times. See application note “Propagation
Delay-Related Parameters” and Figures 7 - 11 for information on the impact that given input rise/fall times have on these
parameters.
CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the
maximum common mode voltage slew rate than can be sustained while maintaining VO < 0.8V. The common mode voltage
slew rates apply to both rising and falling common mode voltage edges. The transient magnitude is the range over which the
common mode is slewed.
The Dynamic Power Dissipation Capacitance is given by:
CPDi = (IDDi(100)-IDDi(Q))/(VDDi * f), where i = 1 or 2 and f is the input signal frequency.
The supply current consumptions at a given frequency are calculated as follows:
IDD1 = CPD1 * VDD1 * f + IDD1(Q)
IDD2(L) = (CPD2 + CL) * VDD2 * f + I DD2(Q), where CL is the output load capacitance.
Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
In accordance with UL1577, each ADuM1100 is proof testing by applying an insulation test voltage > 3000 Vrms for 1 second
(leakage detection current limit, II-O < 5 µA).
Input capacitance is measured at pin 2 (VI).
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
7
ADuM1100AR/ADuM1100BR
5
4
15
Current (mA)
Current (mA)
20
5V
10
3.3V
5
3
5V
2
1
0
3.3V
0
0
25
50
75
100
125
150
0
25
Data Rate (Mbps)
75
100
125
150
Data Rate (Mbps)
Figure 1. Typical Input Supply Current vs. Logic
Signal Frequency for 5V and 3.3V Operation.
Figure 2. Typical Output Supply Current vs. Logic Signal
Frequency for 5V and 3.3V Operation.
1.70
1.40
-40 C
+25 C
+100 C
1.60
Input Threshold, V ITH (V )
Input Threshold, V ITH (V )
50
1.50
1.40
1.30
1.20
1.10
-40 C
+25 C
+100 C
1.30
1.20
1.10
1.00
0.90
0.80
3
3.5
4
4.5
5
5.5
3
Input Supply Voltage, V D D 1 (V )
3.5
4
4.5
5
5.5
Input Supply Voltage, V D D 1 (V )
Figure 3. Typical Input Voltage Switching Threshold,
Low-to-High Transition.
Figure 4. Typical Input Voltage Switching Threshold,
High-to-Low Transition
Safety-Limiting Current (mA)
180
160
Input Current
140
Output Current
120
100
80
60
40
20
0
0
50
100
150
200
Case Temperature (Deg. C)
Figure 5. Thermal Derating Curve, Dependence of Safety
Limiting Values with Case Temperature per VDE 0884.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
8
ADuM1100AR/ADuM1100BR
Package Outline Drawing:
8-Lead Small Outline
(R-8)
Dimensions are in inches and (mm)
0.1968 (5.00)
0.1890 (4.80)
8
5
1
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
PIN 1
0.0098 (0.25)
0.2284 (5.80)
0.0688 (1.75)
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0532 (1.35)
0.0040 (0.10)
0.0500 0.0192 (0.49)
SEA TIN G
0.0098 (0.25)
(1.27)
PLAN E BSC 0.0138 (0.35) 0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
Application Information
PC Board Layout
The ADuM1100 digital isolator requires no external interface circuitry for the logic interfaces. Given that normal
guidelines are followed for the maintenance of the supply distribution impedances, no bypassing is required at the
output supply pin. A bypass capacitor is recommend at the input supply pin and may be most conveniently connected
between Pin 3 and Pin 4 (Figure 3). Alternatively, the bypass capacitor may be located at Pin 1 and Pin 4. The
capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
VDD2
ADuM1100
VDD1
VI (Data
In)
(optional)
VO (Data Out)
GND2
GND1
Figure 6. Recommended Printed Circuit Board Layout.
Propagation Delay-Related Parameters
Propagation Delay Time is a parameter that describes the length of time it takes for a logic signal to propagate through
a component. Propagation Delay Time to Logic Low Output and Propagation Delay Time to Logic High Output refer
to the duration between an input signal transition and the respective output signal transition (Figure 7).
Pulse Width Distortion is the maximum difference between tPLH and tPHL and provides an indication of how accurately
the input signal’s timing is preserved in the component’s output signal. Propagation Delay Skew is the difference
between the minimum and maximum propagation delay values among multiple ADuM1100 components operated at
the same operating temperature and having the same output load.
Input (VI)
50%
tPLH
Output (VO)
tPHL
50%
Figure 7. Propagation Delay Parameters.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
9
ADuM1100AR/ADuM1100BR
Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary
from the true propagation delay of the component (as measured from its input switching threshold). This is due to the
fact that the input threshold, as is the case with commonly-used optocouplers, is at a different voltage level than the
50% point of typical input signals. This propagation delay difference is given by:
∆LH = t'PLH – tPLH = (tr/0.8V1)(0.5V1 – VITH(L-H))
∆HL = t'PHL – tPHL = -(tf/0.8V1)(0.5V1 – VITH(H-L))
where: tPLH, tPHL = propagation delays as measured from the input 50% level
t'PLH, t'PHL = propagation delays as measured from the input switching thresholds
tr, tf = input 10-90% rise/fall time
VI = amplitude of input signal (0 to VI levels assumed)
VITH(L-H), VITH(H-L) = input switching thresholds
∆LH
∆HL
VI
VITH(L-H)
0V
50%
VITH(H-L)
tPLH
Input (VI)
tPHL
t'PLH
t'PHL
50%
Output (VO)
Figure 8. Impact of Input Rise/Fall Time on Propagation Delay.
0
4
(ns)
HL
3.3V Input Signal
3
Prop. Delay Change,
Prop. Delay Change,
LH
(ns)
5V Input Signal
2
1
0
-1
-2
-3
5V Input Signal
3.3V Input Signal
-4
1
2
3
4
5
6
7
8
9
10
1
Input Rise Time (10-90%, ns)
Figure 9. Typical Propagation Delay Change Due to
Input Rise Time Variation (for VDD1 = 3.3, 5V).
2
3
4
5
6
7
8
9
10
Input Fall Time (10-90% , ns)
Figure 10. Typical Propagation Delay Change Due to
Input Fall Time Variation (for VDD1 = 3.3, 5V).
The impact of slower input edge rates can also affect the measured pulse width distortion as based on the input 50%
level. This impact may either increase or decrease the apparent pulse width distortion depending on the relative
magnitudes of tPHL, tPLH, and PWD. The case of interest here is the condition that leads to the largest increase in pulse
width distortion. The change in this case is given by:
∆PWD = PWD' - PWD = ∆LH - ∆HL = (t/0.8V1)(V - VITH(L-H) - VITH(H-L)) , (for t = tr = tf)
where: PWD = |tPLH - tPHL|
PWD' = |t'PLH - t'PHL|
This adjustment in pulse width distortion is plotted as a function of input rise/fall time in Figure 11 below.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
Pulse Width Distortion Adjustment,
PWD (ns)
a
6
10
ADuM1100AR/ADuM1100BR
5V Input Signal
5
3.3V Input Signal
4
3
2
1
0
1
2
3
4
5
6
7
8
9 10
Input Rise/Fall Time (10-90%, ns)
Figure 11. Typical Pulse Width Distortion Adjustment Due to Input Rise/Fall Time Variation (at VDD1 = 3.3, 5V).
Method of Operation, DC Correctness, and Magnetic Field Immunity
Referring to the functional block diagram on page 1, the two coils act as a pulse transformer. Positive and negative
logic transitions at the isolator input cause narrow (2ns) pulses to be sent via the transformer to the Decoder. The
Decoder is bistable and is therefore either Set or Reset by the pulses indicating input logic transitions. In the absence
of logic transitions at the input for more than 2 µs, a periodic "update" pulse of the appropriate polarity is sent to
ensure "DC correctness" at the output. If the Decoder receives no pulses for more than about 5 µs, then the input side
is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the
Watchdog timer circuit.
The limitation on the ADuM1100’s magnetic field immunity is set by the condition in which induced voltage in the
transformer’s “receiving” coil is sufficiently large to either falsely set or reset the Decoder. The analysis below defines
the conditions under which this may occur. The ADuM1100’s 3.3V operating condition is examined as it represents
the most susceptible mode of operation:
Allowable Magnetic Field Amplitude
(KGauss)
The pulses at the transformer output are greater than 1.0V in amplitude. The Decoder has sensing thresholds at
about 0.5V therefore establishing a 0.5V margin in which induced voltages can be tolerated. The induced voltage
induced across the “receiving” coil is given by:
V = (-dβ/dt)ΣΠrn2; n = 1,2,…,N
where: β = magnetic flux density (Gauss)
N = number of turns in receiving coil
rn = radius of nth turn in receiving coil (cm)
Given the geometry of the receiving coil in the ADuM1100 and an imposed requirement that the induced voltage
be at most 50% of the 0.5V margin at the Decoder, a maximum allowable magnetic field is calculated as shown in
Figure 5. A 50% margin is maintained to accommodate the possibility of input voltage transients occurring in
conjunction with the external magnetic field disturbance.
100
10
1
0.1
0.01
0.001
0.1
1
10
100
1000
10000 100000
Magnetic Field Frequency (KHz)
Figure 12. Maximum allowable external magnetic field.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
a
11
ADuM1100AR/ADuM1100BR
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 KGauss induces a
voltage of 0.25V at the receiving coil. This is about 50% of the sensing threshold and will not cause a faulty output
transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst case polarity) it
would reduce the received pulse from > 1.0V to 0.75V – still well above the 0.5V sensing threshold of the Decoder.
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board
traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be
taken in the layout of such traces to avoid this possibility.
µmIsolation in Field Bus Networks
The emergence of field bus communication networks such as PROFIBUS or DeviceNet has enabled higher levels of
control in industrial automation systems than previously possible. These networks, interconnecting sensors, actuators,
controllers, and various other devices, typically recommend the use of galvanic isolation at each interface location
(Figure 5). The use of galvanic isolation in the network increases data integrity and provides protection from power
faults and ground loop effects.
The ADuM1100, using µmIsolation technology, provides a superior isolation solution for field bus networks than
alternatives such as optocouplers. The ADuM1100AR provides superior propagation delay and pulse width distortion
performance, a higher level of common mode transient immunity, and a substantial reduction in power consumption
relative to optocoupler devices. The ADuM1100BR offers all of the same advantages and supports a four-fold increase
in data rate to 100 Mbps.
Controller
Field Bus
Field Bus
Device #1
Device #2
Transceiver
Device #3
Device #4
Isolation
Field Bus
Interface
Sensor/
Actuator/
etc.
Figure 13. Representative Field Bus Configuration.
µmIsolation is a trademark of Analog Devices, Inc.
Rev. PrG November 6, 2000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2000