designfeature By Brian Rush, Texas Instruments
TODAY’S MOST ADVANCED LOW-VOLTAGE MICROPROCESSORS, DSPs, AND PLDs USE TWO POWER
SUPPLIES OF DIFFERENT VOLTAGES TO SIGNIFICANTLY
REDUCE POWER REQUIREMENTS. PROPER SEQUENCING
CAN MEAN THE DIFFERENCE BETWEEN DUAL SUPPLIES
AND DUELING SUPPLIES, WITH SYSTEM RELIABILITY
HANGING IN THE BALANCE.
Power-supply sequencing
for low-voltage processors
he use of a dual-voltage architecture often
requires coordinated management of both supplies to avoid potential problems with device
and system reliability. Designers must consider the
relative voltage and timing of core- and I/O-voltage
supplies during power-up and -down operations to
comply with manufacturers’ requirements. Intelligent, dual-output-supply control ICs are useful for
sequencing power supply rails in low-voltage
systems.
T
WHY SEQUENCING MATTERS
ates with a single powered rail. It is unlikely for a
single or even several poorly controlled power-up
and -down cycles to harm the processor. But in a
system that is power-cycled many times a day, day
after day, the dual-voltage device’s operation may
ultimately suffer from a compromised long-term
reliability.
By contrast, improper supply sequencing can
cause immediate and catastrophic damage to the
bi-directional I/O ports. With most ICs fabricated
in CMOS technology, the potential for latch-up exists when a processor’s I/O port and the I/O port
of a supporting peripheral, such as memory, an
FPGA, or a data converter, do not share the same
supply.
Latch-up occurs when current forced through the
substrate of a CMOS device triggers a self-sustained
conduction path in back-to-back parasitic bipolar
Sequencing refers not only to the order in which
voltage rails power-up and -down but also to their
timing and voltage-differential relationships. Designing a system without proper sequencing risks
two kinds of potential danger. The first type represents a threat to the long-term reliability of the dualvoltage device. The second can cause either immediate or latent faults and possibly damage I/O
Figure 1
ports in the processor or supporting system
devices, such as memory, logic, or data-converter
3
ICs.
I/O SUPPLY (3.3V)
The threat to long-term reliability of the dualvoltage device comes from the possibility of breakVOLTAGE (V) 2
CORE SUPPLY (1.5V)
down in the ESD protection and well-isolation
VOK
structures that internally separate the two power1
supply rails. If one rail is active while the other is inDV
active, damage may occur if the condition persists
Dt
for extended periods. It is important to realize “ex5
10
15
20
25
tended periods” mean months for most devices, a
TIME (mSEC)
time scale that does not apply to ordinary design
considerations for these systems. However, device Sequential power-up imposes a fixed delay between supply
manufacturers count the cumulative lifetime expo- ramps or ramps the second supply after the first reaches
sure to conditions under which a processor oper- regulation.
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September 1, 2000 | edn 115
designfeature Supply sequencing
transistors (as in an SCR). Curmethod the power-subsystem
rent continues to flow
designer should use; they simply
Figure 2
until the device fails or
specify restrictions on time or
until the supply powers down.
voltage differences during pow3
I/O SUPPLY (3.3V)
The trigger current may occur
er-up. Some processors allow
if a supply powers one device,
out-of-tolerance voltage condiDV
VOLTAGE (V) 2
enabling it to source or sink
tions to persist for just 50 msec,
current into or out of the secand their data sheets recommend
Dt
ond device before the second
diodes between the core and the
1
CORE SUPPLY (1.5V)
device fully powers up. A sysI/O rails to prevent the out-oftem can also trigger a latch-up
tolerance conditions in the abif it drives an input pin above or
sence of coordinated power-up
5
10
15
20
25
below the power-supply rails
of the core and I/O rails. Data
TIME (mSEC)
after both devices have powered
sheets for other processors do
up. A latch-up condition may Ratiometric power-up start and complete their ramps and reach
not define the restrictions as well.
cause damage that is immedi- regulation together.
Although they may not specify a
ately noticeable, or it may affect
specific order for powering the
reliability over a long
voltage rails, system designers
Figure 3
period of time. To hanshould consider bus-contention
I/O SUPPLY (3.3V)
dle latch-up problems, you
issues. Good design practice may
must power any logic periphercall for powering up both rails at
3
al connected to the processorthe same time or powering up
I/O bus from the same supply
one rail before the other to preVOLTAGE (V) 2
rail that powers the processor’s
vent unknown output states on
DV=0
CORE SUPPLY (1.5V)
I/O section.
the I/O bus. At least two device
Bus contention occurs when
manufacturers, Intel and TI, cau1
the processor and another detion against leaving only one
Dt=0
vice simultaneously attempt to
supply powered for long periods.
control a bidirectional bus durAlthough vendors do not often
5
10
15
20
25
ing power-up, which can affect
specify a maximum period, a
TIME (mSEC)
I/O reliability. Designers should
useful rule of thumb is to comcheck the specifics for bus con- Simultaneous power-up forces the two supplies to track to within
plete powering up or down both
tention for individual devices. some small DV departing only when the core supply reaches regurails within 1 sec. This time peTo eliminate the risk of these lation.
riod is chosen for convenience; it
dangers to the processor and
is significantly longer than the
system ICs, good design practice pro- ration and amount that one supply ex- time needed to accomplish the task but
vides careful power-up and -down se- ceeds the other. With the second method, much shorter than the time that would
the ratiometric method, the two rails be- damage the device from having only one
quencing.
gin to power up and reach regulation at rail active, even if the damage is cumuAPPROACHES TO POWER-UP SEQUENCING
the same time (Figure 2). This method lative.
To avoid potential threats to the requires a higher slew rate for the rail
processor and system ICs, designers fol- with the higher final voltage and results PRACTICAL SEQUENCING
low three general methods for power-up in the maximum voltage differential
Although the restrictions on simultasequencing. Taken together, these design when the supplies reach regulation. neous power-up are greater than on othapproaches are referred to as power-up However, some processors may not tol- er power-up methods, all of the methods
sequencing methods, a term that should erate the instantaneous voltage differ- require coordinated control of the two
not be confused with sequential power- ences that occur while the supplies are power supplies. Until recently, designs
up.
slewing. The third approach eliminates have accomplished this coordination
Sequential power-up, as its name im- instantaneous voltage differences. A through the use of diodes connecting the
plies, energizes the two rails one after the common way of implementing the third two power-supply outputs. With this
other (Figure 1). Typically, the second method is simultaneous power-up, in technique, if one rail rises ahead of the
rail begins to ramp up once the first rail which the voltage rails rise together and other, it pulls the second rail along
reaches regulation. Alternatively, the sec- at the same rate, with the higher or I/O with it.
ond rail may begin its ramp after a set de- voltage rail continuing after the lower or
As long as the voltage rails are close tolay from the start of the first rail. Both core voltage rail has reached its final val- gether (for example, 3.3 and 2.5V),
methods must comply with manufac- ue (Figure 3).
diodes can control the separate voltage
turers’ restrictions on the minimum or
In general, microprocessor manufac- ramps. However, core voltages of 1.8 and
the maximum lag time or with the du- turers do not specify which sequencing 1.5V are frequently used today, with
116 edn | September 1, 2000
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designfeature Supply sequencing
even lower voltages coming
uations in which the loading
soon, whereas the I/O
on either rail changes during
Figure 4
voltage is likely to stay
power-down and is different
at 3.3V for some time. With
from one power-down event
DSP
VOUT1
large voltage differentials beto another. A technique for
LOW-DROPOUT
VIN1
I/O
REGULATOR 1
tween core and I/O, the diode
making the power-down rates
3.3V
EN1
ENA
technique is less effective beoccur more reliably involves
SENSE 1
SEQUENCE
RESET
cause diode ratings are too indischarging the power-supply
LOGIC
SEQ
SENSE 2
accurate to produce a preoutputs with a known load
EN2
dictable voltage drop from one
each time. The TPS563xx,
VIN2
LOW-DROPOUT
CORE
REGULATOR 2
1.5V
rail to another. Thus, it beTPS701xx, TPS703xx, and
VOUT2
comes necessary to use a differTPS707xx low-dropout reguent technique for power-up selator families integrate circuitDual low-dropout regulators include sequencing logic to coordinate
quencing.
ry that provides an internal
A straightforward design for the two supplies during transitions.
discharge path on each output.
sequential power-up would use
The circuitry activates autoa comparator, voltage dematically when the input suptector, or SVS (supplyply falls below an undervoltFigure 5
voltage supervisor) to
age-lockout threshold or upon
monitor the first supply in the
the receipt of a logic-shutsequence and delay the powerdown signal.
up of the second. If the supply
GOOD POWER-SUPPLY DESIGN
input equals the I/O supply, the
voltage-monitor circuit could
As the use of dual-voltage
control a MOSFET switch or a
microprocessors, DSPs, and
low-dropout regulator operatPLDs increases, the gap being in dropout mode. If the intween core- and I/O-voltage
put supply is greater than the
levels is widening. Soon, cores
I/O supply, a regulator is rewill be running at 1V or less,
quired. Dual low-dropout regwhereas I/O voltages are likeulators with built-in monitorly to remain at 3.3V for some
ing circuitry can supply both Simultaneous power-up: TPS56300 controls both core and I/O suptime. In this dual-voltage enthe I/O and the core (Figure 4). plies.
vironment, good power-supThe SEQ pin selects the order
ply-design techniques, such as
of the output power-up. When both out- ratiometric power-up. A dual-controller proper sequencing, will be more imporputs reach regulation, the RESET func- IC also allows the circuit designer to use tant than ever. Sequencing helps ensure
tion delays processor execution for 120 capacitors of different sizes to predictably the long-term reliability of the processor
msec. The TPS701xx, TPS703xx, and retard one of the output ramps.
and at the same time helps protect sysTPS707xx low-dropout regulator famiAlthough you can use most power tem-I/O cells. The processor in question
lies, which can supply 150 mA to 2A to supplies with soft-start inputs for ratio- may require strict timing and voltage difthe core or I/O rails, integrate these func- metric power-up, simultaneous power- ferentials; nevertheless, it is desirable to
tions.
up requires a device with dual-level out- design the power-supply rails to rise and
A simple implementation of ratiomet- puts that track to keep the timing fall predictably. Today’s intelligent, dualric power-up sequencing consists of con- matched within user-selected limits. As output supplies help simplify designing
necting the soft-start inputs of two an example, the TPS56300, with a low- power for the low-voltage processors
switching-controller circuits to the same- dropout regulator for I/O and a switch- that are fundamental to many types of
sized capacitor. To make the rise times ing regulator for the core, integrates a systems.k
nearly identical, you may be able to con- single capacitor for both outputs and regnect both soft-start inputs to one capac- ulates them using the same reference Author’s bio graphy
Brian Rush is a systems
itor. This situation is especially true if a voltage to provide tight matching
engineer at Texas Instrusingle chip integrates both controller cir- (Figure 5).
ments in Dallas, where he
cuits. In this case, the characteristics of
The system designer should also acdevelops power-managethe soft-start inputs closely match, mak- count for power-down sequencing. The
ment products for DSPs.
ing it more likely that the outputs ramp node capacitance and resistive load deHe holds a BSEE from
up within a tight timing window. A dual- termine the voltage profile of each rail
the University of Texas
output switching controller, such as the during power-down. But in typical digiTPS5102, with its PWM outputs, allows tal systems, power-down can occur as a (Arlington, TX). You can reach him at
the use of a single external capacitor for result of several scenarios, including sit- brian_rush@ti.com.
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