9. Memory Elements and Dynamic Logic
Institute of
Microelectronic
Systems
RS Flipflop
The RS-flipflop is a bistable element
with two inputs:
• Reset (R), resets the output Q to 0
• Set (S), sets the output Q to 1
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
2
RS-Flipflops
There are two ways to implement a RS-flipflop:
• based on NOR-gates: positive logic
• based on NAND-gates: negative logic
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
3
Clocked RS-Latch
To achieve a synchronous
operation, we can add a clock
signal
• Clock= 0: R and S have no
influence upon the state of the
circuit
• Clock= 1: R and S can change
the state of the circuit
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
4
D-Latch
For storing data it is more
convenient to have a data
input. This is realized by
using the data input as set
signal and the inverted data
input as reset signal.
• Clock= 0: Q unchanged
• Clock= 1: Q= D
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
5
Transmission Gate D-Latch
An alternative way to build a D-latch is to use transmission gates
thus reducing the complexity (transistor count) of the circuit.
• Load= 0: Latch stores data
• Load= 1: Latch is transparent (output= input)
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
6
Clocked JK-Latch
An other extension of a simple RSflipflop is a JK-Latch
• J: enables/disables the low to
high transition of the latch
• K: enables/disables the high to
low transition of the latch
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
7
Edge Triggered Logic
If the previous presented D-latch would
be used in a synchronous circuit, i.e.
a counter, it would produce a
malfunction:
While clock is low the latches have the
state Q(n) and the feedback network
would apply the state Q(n+1) at the
inputs of the latches. When clock
goes high the latches change to the
new state Q(n+1). The feedback logic
calculates now the state Q(n+2). But
clock is still high so the latches
change falsely to the state Q(n+2).
So what we need is a latch which
changes only once per clock cycle,
this is edge triggered logic.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
8
Edge Triggered JK-Flipflop
A straight forward way to implement an edge-triggered JK-flipflop is
to use a master-slave flipflop.
• Clock= 1: The master (left latch) is changeable, the slave (right
latch) is locked and holds the output at the current state
• Clock= 0: The master is locked and the slave is changes its state
if necessary
Æ The output value is the state of the master at the falling edge of
the clock signal
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
9
Edge Triggered TG D-Flipflop
Circuitry of an edge-triggered flipflop
• Clk= 0: First stage is loaded, second stage is locked and stores data
• Clk= 1: First stage is locked, second stage is loaded
Æ With the rising edge (low to high transition) the new value is
available a the output
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
10
Transmission Gate JK- Flipflop
It is also possible to
build a JK-flipflop with
transmission gates as
a edge-triggered
flipflop.
This achieves that the
output state can only
change at the rising
edge of the clock
signal
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
11
Dynamic D-Flipflop
Dynamic logic utilizes the parasitic capacitances of transistors and
interconnect to store the current state. This reduces the transistor
count but forbids a static operation. An application of dynamic
circuits is the dynamic D-flipflop.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
12
Dynamic Shift Register
An other application is the dynamic shift register. It has also less
transistor count but requires a non-overlapping two-phase clock
which is expensive to generate.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
13
Dynamic Chain Latch
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
14
Dynamic RAM
A special kind of memory is dynamic RAM. The major advantage is
the low transistor count, DRAM requires only one transistor and
one (small) capacitor per bit.
The first disadvantage is the destructive read. After reading a cell
the red value must be written back to keep the data in the RAM.
The second disadvantage is the limited duration of storage. After
some milliseconds the cell must be refreshed (read and written
back).
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
15
Dynamic RAM
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
16
Clocking
Clock Signal:
• used to synchronize data flow though
a digital network
⇒ clocked static or dynamic circuits
• problems: clock skew(delay caused by
clock distribution wires)
Condition for nonoverlapping clock
signals φ1( t ) and φ 2 ( t ):
φ1( t )φ 2 ( t ) = 0 ∀t
9: Memory Elements &
Dynamic Logic
Ideal nonoverlapping 2-phase clocks
Institute of
Microelectronic
Systems
17
Basic 2-phase clocking
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
18
Single and Multiple Clock Signals
Single clock 2-phase timing
⇒ For nonoverlapping clock phases φ and φ fine tuned and well designed
delay lines (realized as Transmission gates) have to be inserted in order to
avoid overlapping of φ and φ.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
19
Generation of inverted clock phase
TG delay circuit
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
20
Pseudo 2-φ clocking
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
21
Clocked Static Logic
⇒ Synchronized data transfer
Shift register
1) Upper Frequency Limitation: Charging and Discharging Times
Clocked shift register circuit
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
22
Time constant for charging and discharging:
τTG = RTGCL
where
CL = CTG + Cin + Cline
VA=VDD:
(Vin(0)=0)
Vin( t ) ≅ VDD ⎡1 − e −t / τTG ⎤
⎢⎣
⎥⎦
Inverter is switched, when Vin=VIH which occurs after
VIH ⎤
⎡
ϕt 1 ≅ − τTG ln ⎢1 −
⎣ VDD ⎥⎦
Cin = Cox [(WL )n + (WL )p ]
VA=0:
(Vin(0)= VDD)
Vin( t ) ≅ VDD ⋅ e −t / τTG
The time until Vin reaches VIL is given by
⎡VDD ⎤
t 0 ≅ − τTG ln ⎢
⎣ VIL ⎥⎦
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
23
2) Lower Frequency Limitation: Charge Leakage
Leakage patch in a CMOS TG
The load capacitance, seen by the transmission gate (TG) is
CL = CTG + Cline + Cin
The depletion capacitance contributions to CL are due to the reversed pn
junctions in the MOS transistors. As shown in fig. above a leakage current flow
exists across the reverse biased pn junctions. The influence of this leakage
current on the charge stored in CL depends on the values of ILp and ILn.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
24
Charge leakage problem in CMOS TG
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
25
With
IL = ILn − ILp
the leakage current influence on Vin is given by
CL
dVin
= − IL
dt
If ILp>ILn the capacitance is charged by IL otherwise it is discharged or remains
constant when the ideal condition ILp=ILn is true.
dQstore
dt
Cstore
= ILp − ILn
=
dQstore
dV
Assuming that the leakage currents ILp and ILn are constant and that the node
charge voltage relation is linear of the form
Qstore = CstoreV
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
26
follows (because Cstore is const.)
Cstor
dV
= ILp − ILn
dt
The solution of this equation is
V(t ) =
( ILp − ILn )
t +V(0 )
Cstor
If ∆V is the maximum allowed voltage change:
Cstor∆V
t max =
IL
Charge leakage circuit
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
27
With Tmax=2tmax (the longest allowed clock period) follows for the minimum
frequency
IL
1
f min ≅
≅
2 t max 2Cstore∆V
The transmission gate capacitance is
Transmission gate capacitance
CT ≅ CG + Cline + Cols + Cold + CSBp( V ) + CDBn( V )
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
28
So the storage capacitance can be estimated by voltage averaging of this
expression:
Cstor ≅ C G + Cline + Cols + Cold + K ( 0 ,VDD )[CSBp + CDBn ]
For a realistic analysis of the charge leakage problems the dependence of the
leakage currents from the reverse voltage bias has to be taken into consideration.
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
29
Charge Sharing
Basic charge sharing circuit
t<0: (TG switched off)
t>0: (TG switched on)
V 1( t < 0 ) = VDD
V 2( t < 0 ) = 0
QT = C1VDD
QT = ( C1 + C 2 )Vf
Vf = V 1( t > 0 ) = V 2 ( t > 0 )
C1
1
=
VDD =
VDD
C1 + C 2
1 + ( C 2 / C1 )
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
30
If we design a circuit with C1=C2, then Vf=(VDD/2), indicating drop in voltage. A
reliable forward transfer of a logic 1 state from C1 to C2 requires that C1>>C2 to
insure that Vf≈VDD.
Let us specify arbitrary initial conditions V1(0)and V2(0) on the capacitors
giving the system a total charge of
Qt = C1V 1( 0 ) + C 2V 2 ( 0 )
Applying basic circuit analysis gives the time-dependent voltage as
V 1(t ) = V 1(0) +
[V (0) − V
(0)]
C 1 + C 2 e −t / τ
(C 1 + C 2)
1
2
[
]
[
⎛ C1 ⎞
−t / τ
V 2(t ) = V 2(0) + [V 1(0) − V 2(0)]⎜
⎟ 1− e
⎝ C1 + C 2 ⎠
]
where the time constant is given by
τ = RTGCeq
with
Ceq =
C1C 2
C1 + C 2
In the limit t→∝, V1=V2=Vf:
Vf =
9: Memory Elements &
Dynamic Logic
C1
C1
V 1( 0 ) +
V 2( 0 )
C1 + C 2
C1 + C 2
Institute of
Microelectronic
Systems
31
This agrees with the result from simple charge conservation by noting that the
final charge distributes according to
QT = ( C1 + C 2 )Vf
Transient voltage behavior for initial conditions of V1(0)=VDD and V2(0)=0
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
32
Charge sharing among N TG-connected capacitors
Initial charge:
N
QT = ∑ CiVi ( 0 )
i =1
After connecting nodes:
Final voltage:
9: Memory Elements &
Dynamic Logic
N
QT = ⎛⎜ ∑ Ci ⎞⎟Vf
⎝ i =1 ⎠
Vf =
∑Ni =1 CiVi ( 0 )
∑Ni =1 Ci
Institute of
Microelectronic
Systems
33
Dynamic Logic
• Pull-up (pull-down) network of static CMOS is replaced by a single precharge
(discharge) transistor.
The remaining network then conditionally discharges (changes up) the output
in a second operation pulse
• One logic level is held by dynamic charge storage
• Transistor count is reduced from 2n (static CMOS) to n+2 for dynamic
precharged CMOS (but now: 2 phases of operation)
Dynamic nMOS Inverter (Single clock, 2 phases)
Basic dynamic nMOS inverter
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
34
Precharge Phase
If Vin=0 then
τch =
Cout
= RpCout
β p( VDD − VTp )
WORST case (Vin=VDD):
τch , max = Rp( Cout + Cn )
tch , max =
⎡
=
τch , max ⎢⎢
2 VTp
⎢ ( VDD
⎣
− VTp )
⎛ 2 ( VDD
+ln ⎜⎜
⎜
⎝
− VTp )
V0
⎞⎤
− 1 ⎟⎟ ⎥⎥
⎟⎥
⎠⎦
Dynamic nMOS inverter:
precharge and evaluate
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
35
Evaluation Phase
For the case that M1 is switched on and identically designed channel width for M1
and Mn the discharge time constant is given by
τdis =
( L1 + Ln )Cout
k ′nW ( VDD − VTn )
Precharge network for worst case
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
36
Evaluation discharge network
⎡
⎤
2VTn + ln ⎛⎜ 2 ( VDD − VTn ) − 1 ⎞⎟ ⎥
⎟⎥
⎜
⎟⎥
⎜
V0
⎠⎦
⎝
⎣⎢ ( VDD − VTn )
tdis = τdis ⎢⎢
Maximum clock frequency
tM = max( tch , max, tdis )
f
max
≅
1
2 tM
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
37
Dynamic pMOS Inverter
φ=1 Precharge
φ=0 Evaluate
Basic dynamic pMOS inverter
Dynamic CMOS Properties and Conditions
• single phase clock
• input should change during precharge only
• input must be stable at the end of the precharge phase
• in the evaluation phase the output remains HIGH (LOW) or is optionally
discharged (charged)
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
38
Complex Logic
Complex dynamic logic
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
39
Dynamic Cascades
pMOS blocks and nMOS blocks have to be installed alternated in order to avoid
glitches
Cascaded nMOS-nMOS glitch problem
Dynamic cascades
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
40
Domino CMOS Logic
Basic domino logic circuit
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
41
• Domino Logic: design method for glitch-free cascading of nMOS logic blocks
• Each stage is driven by φ
- Precharge during φ = 0
- Evaluation when φ = 1
• Domino logic blocks consists of a precharge/ evaluation block and an output
inverter
Precharge Phase: The gate output is precharged to logic 1 and the inverter output
is going to logic 0. Logic transmission errors are avoided by providing a
logic 0 at the inverter output (avoiding discharge of the next logic state).
Evaluation Phase: The inverter output stays according to the actual input values
at logic 0 or is set to logic 1. The correct result signal is provided at the
end of the domino cascade after stabilization of all stages.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
42
Domino AND gate
Cascaded domino logic
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
43
Visualization of domino effect
Domino timing
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
44
Cascaded domino circuit with fanout = 2
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
45
Domino Logic Properties
Cascaded domino logic
• Domino logic consists of either n-type or p-type blocks
• small load capacity to by driven by logic (one inverter only) ⇒ low dimensions of
transistors
• only one clock signal required
• only positive logic realizations possible because of the input inverters ⇒ domino
logic is noninverting
Functions as
cannot be directly realized in a domino chain
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
46
Analysis
Domino AND4 gate
CX=C0+CT. C0 represents the capacitance due to M0, while CT is the total of all
other contributions.
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
47
Precharge (φ=0: Mp1 in conduction, Mn1 in cutoff)
Mp1 conducting →
Minimum precharge time
Cx → Vx > VIH ( = log ic 1 )
⎤
⎡
VTp
⎛ 2 ( VDD − VTp )
⎞
tch ≅ τch ⎢
− 1⎟
⎥ + ln⎜
⎝ VDD − VIH
⎠
⎣ ( VDD − VTp ) ⎦
VX(0)=0
⎤
⎡
CX
τch = ⎢
⎥
⎣ β p( VDD − VTp ) ⎦
CX = C 0 + CT
≅ ( CGDn1 + CBDn1 ) + ( CGDp1 + CBDp1 ) + CG + Cline
Evaluate
If all inputs Ai are set to logic 1, the worst case delay time can be estimated by
tD ≅ RnCn + ( Rn + R 3 )C 3 + ( Rn + R 3 + R 2 )C 2 +
+ ( Rn + R 3 + R 2 + R1 )C1 + ( Rn + R 3 + R 2 + R1 + R 0 )CX
with
Rj +
9: Memory Elements &
Dynamic Logic
1
k ′n( W / L ) j ( VDD − VTn )
Institute of
Microelectronic
Systems
48
Charge Leakage and
Charge Sharing
Domino stage with pull-up MOSFET
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
49
Cout,1>>Cx1+Cx2
Charge sharing in a domino chain
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
50
Use of feedback to control a pull-up MOSFET for charge sharing problem
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
51
NORA Logic
(NORA = NO RAce)
NORA Properties
• NORA is very insensitive to clock delay
• one clock signal and the inverted clock signal with short slopes rise times are
sufficient
• no inverter is needed between the logic stages, because of alternate use of
n-type and p-type blocks
• the last stage is a clocked inverter, a C2MOS latch
• ideal to clock pipelined logic systems
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
52
The Signal Race Problem
Signal race problem
The signal race problem can be seen: a signal race can arise, when both
transmission gates conduct at the same time. If the new input from TG1 reaches
the input of TG2 while TG2 is still transmitting the output, the output information
will be lost. Imperfect TG synchronization occurs because of normal transmission
intervals or clock skew.
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
53
tp>>tr,tf → no problems
Tskew=tp → race result
critical
Clock skew
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
54
φ=0 Precharge
φ=1 Evaluate
Accept data when φ=0,
hold data when φ=1
Dynamic latch operation
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
55
NORA Structuring
clk2
NORA structuring
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
56
NORA φ and φ sec tions
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
57
φ=1 Precharge
φ=0 Evaluate
C2MOS latch
NORA pipelined logic
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
58
φ = 0:
φ = 1:
P
E
P
E
locked
transp.
E
P
E
P
transp.
locked
φ
φ
NORA φ and φ sec tions
Institute of
Microelectronic
Systems
9: Memory Elements &
Dynamic Logic
59
?
0V
?
φ = 0:
φ = 1:
P
E
P
E
locked
transp.
E
P
E
P
transp.
locked
φ
φ
NORA φ and φ sec tions
?
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
60
0V
φ = 0:
φ = 1:
P
E
P
E
locked
transp.
E
P
E
P
transp.
locked
C²MOS Latch
locked during
clock skew
period!
φ
φ
NORA φ and φ sec tions
9: Memory Elements &
Dynamic Logic
Institute of
Microelectronic
Systems
?
61
Duration of initial Value of Evalutation Phase (VDD) will be enhanced
?
Precharged
to 0V
?
φ = 0:
φ = 1:
P
E
P
E
locked
transp.
E
P
E
P
And the other
way round:
transp.
locked
Duration of provision of logical
output value to next stage will
eventually be enhanced
φ
φ
NORA φ and φ sec tions
9: Memory Elements &
Dynamic Logic
?
Institute of
Microelectronic
Systems
62