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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
Design Strategies for Source Coupled Logic Gates
Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE
Abstract—In this paper, a strategy for the design of source-coupled logic (SCL) gates both with and without an output buffer is
proposed. Closed-form design equations to size bias currents and
transistor aspect ratios to meet assigned specifications are derived
from a simple SCL gate analytical delay model, shown to be sufficiently accurate by extensive simulations. The design criteria proposed are simple and provide the designer with a more profound
understanding of the tradeoff between delay and power consumption. More specifically, design criteria are derived to consciously
manage this tradeoff in practical design cases, i.e., when either
high performance or an optimum balance with power dissipation
is needed. Therefore, the strategy proposed is useful right from the
early design phases, and avoids tedious simulation iterations.
Index Terms—Analytical delay model, source coupled logic
(SCL) gates.
I. INTRODUCTION
T
HE diffusion of applications requiring digital signal processing, including digital audio and video applications, has
increased market interest in high-speed high-resolution mixedsignal ICs, such as sigma-delta A/D and D/A converters [1]–[5].
The performance of these circuits, that consist of both analog
and digital circuits sharing the same substrate, is strongly affected by the noise induced onto the former circuits by the latter.
Indeed, due to the supply current spikes during switching, logic
gates generate the power-supply switching noise [5]–[10], that
couples with the analog circuits through supply lines and substrate coupling, thus degrading circuit resolution. In particular,
the traditional CMOS static logic generates a high amount of
noise, and is thus not suitable for high-resolution applications.
For instance, in [5], digital and analog blocks were implemented
in two different chips to obtain the required resolution, even
using analog circuits with a high noise rejection and exploiting
techniques such as diffusion of guard bands, keeping separate
analog and digital supply lines, pads and wires [11]. As a consequence, alternative logic styles with reduced supply current
spikes during switching are needed to reduce the amount of
switching noise.
Until now, various topologies that draw an almost constant
supply current have been proposed [11]–[25]. The most successful among these are the source-coupled logic circuits (SCL)
[9], [11], [20], [25], based on the source-coupled pair of MOS
Manuscript received January 23, 2002; revised June 21, 2002. This paper was
recommended by Associate Editor C.-W. Jen.
M. Alioto was with the Dipartimento Elettrico Elettronico e Sistemistico
(DEES), Universita’ di Catania I-95125 Catania, Italy. He is now with the
Dipartimento di Inggegneria dell Informazione (DII), University of Siena,
I 53100 Siena, Italy.
G. Palumbo is with the Dipartimento Elettrico Elettronico e Sistemistico
(DEES), Universita’ di Catania I-95125 Catania, Italy (e-mail:GPalumbo@
dees.unict.it).
Digital Object Identifier 10.1109/TCSI.2003.811023
transistors, and their modified versions like folded source coupled logic (FSCL) circuits or Enhanced FSCL (EF SCL [14],
[25]. Indeed, compared to CMOS static logic, SCL logic style
allows switching noise to be reduced by two orders of magnitude [12], [14]. Since the low switching noise feature of SCL is
obtained at the cost of static power dissipation, a design strategy
of SCL gates is required to meet specifications, while keeping
power consumption as low as possible. Moreover, design criteria to consciously manage the power-delay tradeoff are required.
In this paper, a systematic design procedure to size the bias
current and transistor aspect ratio to satisfy noise margin (NM)
and delay requirements is proposed. To this end, an analytical
model of NM and delay is discussed for the SCL inverter both
with and without output buffer. The model affords a deeper understanding of the power-delay tradeoff, and, as the simulations
confirm, it is also accurate enough for this purpose. The relationships obtained are then used to size the design parameters.
More specifically, first the transistor aspect ratios are expressed
as a function of the bias current to meet the NM requirement,
and then the bias current is sized according to either power-efficient or high-speed design criteria. Successively the results are
extended to the case with the output buffer, providing an optimal size for its transistors and bias current to minimize delay,
assuming practical design conditions.
The proposed design strategy gives simple closed-form expressions of design parameters. Moreover, model and design
equations simply relate delay and the bias current, thus helping
designers to suitably balance speed and power without resorting
to tedious simulation iterations.
Modeling of the NM and delay of SCL gates with and without
an output buffer is discussed in Sections II and III, respectively.
Design strategies for SCL gates with and without output buffer
are presented in Sections IV and V, respectively, where design
examples are provided for each criteria considered. Finally, conclusions are reported in Section VI. Moreover, to enhance the
readability of this paper, two appendices have been added.
II. SCL GATES MODEL
The SCL inverter, shown in Fig. 1 (where
models the
load), is made up of an NMOS source-coupled pair having transistors working in the saturation or cutoff region, that approximate well the behavior of a voltage-controlled current switch.
The gate bias current, , is steered to one of the two output
branches and converted into a differential output voltage by two
PMOS transistors working in the linear region. Defining
the voltage drop of M3 (M4) due to a drain current equal to ,
, becomes equal to 2
.
the logic swing of the gate,
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ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
641
TABLE I
0.35-m PROCESS PARAMETERS
Fig. 1. SCL inverter.
A. Modeling of DC Parameters
As demonstrated in Appendix I using the standard BSIM3v3
MOSFET model [26], under the static condition, PMOS transistors can be suitably approximated by an equivalent linear regiven by [27]
sistance
(1a)
models the
where parameter
source/drain parasitic resistance and depends on the empiric
as well as the PMOS transistor effecmodel parameter
, with parameter
being given by
tive channel width
(1b)
that represents the “intrinsic” resistance of the PMOS transistor
in the linear region (i.e., it does not account for the parasitic
represents the
drain/source resistance). In (1b), the term
effective hole mobility (A1.3a) defined in Appendix I, paramis the PMOS effective channel length,
is the oxide
eter
is the threshold voltage.
capacitance per area, and
Using (1), the logic swing is equal to
(2)
Due to symmetry, the circuit logic threshold is equal to zero,
, where
and the associated small-signal voltage gain is
is the small-signal transconductance of transistors M1-M2
. Transconductance
for short-channel
with
transistors can be evaluated using the well-known expression
valid for long-channel devices [32] where the effective electron
, given by (1) must be used instead of the longmobility,
channel mobility.
and
Since
when the gate is biased around the logic threshold, voltage
of transistors M1-M2 is equal to their
, which can be
for the sake of simplicity. Hence, the
underestimated to
is
resulting expression of the voltage gain
(3)
where relationship
was substituted.
Fig. 2. Equivalent linear half circuit of the SCL inverter.
From algebraic manipulations developed in Appendix II, NM
can be expressed as
NM
(4)
(i.e., half the logic swing)
that is proportional to parameter
is in the order of 4.
and roughly equal to it if
The dc parameters expressions (2)–(4) were compared to
Spectre simulation results for an SCL inverter, using a 0.35- m
CMOS process, whose main parameters are summarized in
V,
Table I. Simulations were performed by setting
ranging from 5 to 100 A, and choosing the transistors
with
ranging from 2 to 7, and
from
aspect ratio to obtain
,
and NM
200 to 900 mV. The maximum error for
is equal to 25%, 26%, and 25%, respectively, and the average
error is 15%, 13%, and 8%, respectively.
B. Modeling of Propagation Delay
, of the SCL inTo model the propagation delay,
verter in Fig. 1, it is useful to observe that NMOS transistors
work in the saturation region most of the time, and their source
voltage is the same for both input logic values (it is fixed by the
NMOS transistor in the ON state). Thus, after linearizing the cir, the half-circuit concept
cuit around the logic threshold
applies, since the circuit is symmetrical and input is differential
[27].
In the half circuit obtained, shown in Fig. 2, transistor M1
(M2) is replaced by its small-signal model and transistor M3
. The para(M4) is substituted by its equivalent resistance
sitic capacitances of PMOS and NMOS transistors (associated
with subscripts and , respectively) affecting circuit switching
, which represents the drain-bulk junction capacitance,
are
, which schematizes the channel and the overlap contriand
bution between the gate and the drain.
The first-order circuit in Fig. 2 has a time constant ( ) that can
be evaluated by applying the open-circuit time constant method
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
[28], and whose resulting delay is 0.69 , assuming a step input
waveform and after neglecting the high-frequency zero. Hence,
of the SCL gate is given by
the propagation delay
(5)
in (5) is evaluated in the satuThe NMOS capacitance
ration region, it is thus almost equal to the overlap capacitance
between the gate and the drain. Junction capacitances
and
can be linearized by modifying their value in
according to [29].1
a zero-bias condition via coefficients
Capacitance
is equal to the sum of the overlap contribuand the intrinsic contribution associated with
tion
the channel charge of the PMOS transistors working in the linear
. In particular, we can adopt the BSIM3v3 caregion,
as the
pacitance model [26], that expresses capacitance
with respect to the
derivative of charge flowing into drain
[27]
drain voltage
Fig. 3.
C
Simulated and theoretical (5) delay versus bias current
= 50 fF.
I
with
As highlighted in Section II-B, the source voltage of transistors M1–M2 in Fig. 1 is independent of the input logic value;
seen from the gate of M1 (or
thus, the input capacitance
M2) can be assumed equal to its gate-source capacitance evaluated in the saturation region
(7)
(6)
obtained by considering that the gate, source, and bulk
evaluated
voltages are constant, using parameter
in Appendix I slightly greater than unity, and assuming
. It is apparent that the expression
valid for long-channel devices (i.e.,
[30], [31]) is significantly different from (6).
To validate the delay model, the bias current was varied from
5 to 100 A, the transistor aspect ratios were sized to obtain the
mV and
, and the load
typical values
was set to 0 F, 50 fF, 200 fF, and 1 pF.
capacitance
In order to show typical behavior, the predicted and simulated
equal to
delay is reported in Fig. 3, versus bias current for
50 fF. The error of the model, plotted in Fig. 4, is always within
F.
19% even in the nonrealistic case of
which shows from the actual value, an error of at most 15%, and
is typically less than 10%.
III. SCL GATES WITH AN OUTPUT-BUFFER MODEL
An output buffer can be added to the basic SCL gate as in
Fig. 5 either to improve its driving capability (and its switching
speed) or to shift the output common-mode voltage level. The
output buffer is implemented with a source-follower biased by
.
the current source
A. Modeling of DC Parameters
,
, and NM of the SCL gate in Fig. 5
Parameters
can be directly derived from (2)–(4) by properly taking into account the small-signal voltage gain of the common-drain stage
[31]
(8)
C. Evaluation of SCL Gates Input Capacitance
In the previous subsection, the delay was evaluated with an
, which modeled the wiring caassigned load capacitance
pacitances and the input capacitances associated with the subsequent gates. Therefore, to evaluate the delay of cascaded gates
of an SCL gate
one must express the input capacitance
to compute the delay of the previous gate.
1Coefficient
K
K
=
is equal to
V
0V
(
0V )
10m
0 ( 01 0V m)
where is the built-in potential across the junction, m is the grading coefficient
of the junction, and V and V are the minimum and maximum direct voltages
across the junction, respectively.
and
are respectively, the body effect
where
transconductance, and the transistor transconductance, and
their ratio is almost constant 2 .
, and the overall voltage gain
,
The logic swing
are then equal to the product of (8) with (2) and (3), respectively. Therefore, the NM can be evaluated by substituting the
and
in (4).
parameters obtained
Simulation results showed that, with respect to the case
without the buffer, the logic swing and the voltage gain were
invariably reduced by 12%, as accurately predicted by (8) [27].
g
2Typically,
g
=g
g
=
= 0:13 with the process used, giving v =(v ; buf1 0 v ; buf2) = 0:88
ranges from 0.1 to 0.2, and it is
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
Fig. 4.
643
Error of (5) with respect to simulated results versus bias current I .
Fig. 5. SCL inverter with output buffers.
B. Modeling of Propagation Delay and Validation
Fig. 6.
The propagation delay of the SCL gate with the output buffer
is equal to the sum of the SCL gate delay
in Fig. 5,
, and that of the buffer delay
(9)
is given by (5) setting
to zero, 3 and
Delay
is evaluated by driving it with the
that of the buffer
Thevenin equivalent circuit seen at the output of the internal
and a resistance
SCL gate, modeled with a voltage source
(equal to
). More specifically,
is evaluated by
analyzing the circuit in Fig. 6, where the linearized buffer circuit is driven by the Thevenin equivalent circuit of the SCL gate
and the source-bulk capacitance was neglected with respect to
.
and
represent the gateIn Fig. 6, capacitances
drain and the gate-source contributions, and are evaluated as
3In order to model interconnects between the inverter and the buffer, C can
be set to its equivalent value.
Equivalent linear circuit of the SCL inverter with output buffer in Fig. 5.
small-signal capacitances in the saturation region. For the sake
of simplicity, the body effect was taken into account only when
to the input
evaluating the contribution of capacitance
), neglecting that in the output
loop (i.e., in parallel with
loop with respect to load capacitance. More specifically, in ap, its contribution to the input
plying the Miller theorem to
with parameter that is
loop is obtained by multiplying
) and results in
equal to (
(10)
The transconductance of transistors implementing the buffer
can be evaluated [27] as shown in (11) at the bottom of
the page.
Despite the circuit in Fig. 6 having two poles and one highfrequency zero, it exhibits a dominant-pole behavior for pracand
(detailed analysis shows that the
tical values of
(11)
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
second pole is greater than the first at least by one order of magnitude), thus, we obtain the following expression of the buffer
delay:
(12)
From (12), we can see that buffer delay is equal to the sum
and models the
of two terms: the first is proportional to
loading effect of the buffer on the internal SCL gate, the second
, and hence it depends on the
is inversely proportional to
buffer driving capability.
The buffer delay model was validated with many simulations.
was varied from 5 to 100 A, and bias
The bias current
was set to 5, 20, 50, and 100 A, with
V
current
(the transistor aspect ratios and load capacitance were sized as
in the previous subsection).
The observed model error was always lower than 20% (unless
for unpractical cases in which it reach 35%), and the average
error found was 15%.
IV. DESIGN STRATEGIES OF SCL GATES WITHOUT
OUTPUT BUFFER
AN
In SCL gates, the transistors’ aspect ratio and bias current
must be sized to satisfy NM and speed requirements. Using the
model developed, in the following Sections IV-A and IV-B, the
aspect ratio which meets the specification and the associated
delay are expressed as a function of ; subsequently, the bias
current is set for a power-efficient (Section IV-C) or high-speed
design (Section IV-D).
A. Transistor Sizing Versus
The analysis of SCL gates without a buffer carried out in Section II provides closed-form expressions of their performance
that can be used in the design phase. More specifically, they
help us to choose proper values for transistor aspect ratios and
bias current to satisfy NM and speed requirements.
By inspection of (4), an adequate NM is obtained if
and
are sufficiently high. However, increasing
leads
to a logic swing increase that in turn determines speed degradation, thus, for an assigned value of NM, from (3) we have
with respect to
. Howto choose a sufficiently high
can only be achieved by inever, from (3), high values of
creasing the NMOS transistor aspect ratio, thus increasing parasitic capacitances and slowing down the circuit. A good compromise for an adequate NM without excessively degrading speed
(for instance, by
performance is obtained by setting
we get
NM). In the following,
choosing
and
are assumed to have already been chosen in a preliminary design phase on the basis of the NM requirement.
The PMOS transistor aspect ratio has to be sized to obtain the
resistance value
that, for a given value of ,
. Desired resistance
is achieved by
ensures the desired
properly setting the aspect ratio of PMOS, whose value may be
greater or lower than that obtained for the minimum transistor
, depending on
. To explain this point,
size
as the PMOS resistance obtained for
we first define
as
minimum transistor size, and
(13)
that, for example, is equal to 24.6 A for the 0.35- m techand
nology described above and setting typical values
mV. If
(or, equivalently, the desired
is greater than
) we have to set
and increase
according to 4
(14)
(i.e.,
that was derived by inverting (1). If
), we have to set
and increase
as
shown in (15) at the bottom of the page.
The NMOS transistor aspect ratio has to be sized to guarantee a voltage gain higher than (or equal to) the desired value
, for a given
. By inspection of (3), assuming a min(i.e.,
imum NMOS aspect ratio, a sufficiently high value of
) is achieved for bias currents such that
(16)
For example, using the considered technology and setting
and
mV,
results in 1.45 A,
which is very low with respect to practically used values. For
, (3) shows that the NMOS aspect ratio must be
. Hence, we
increased to guarantee the assigned value of
and
according to
have to set
(17)
regardless of the
It is worth noting that
process used (indeed, under the rough approximation
, the ratio
is equal to
, that is largely greater than unity).
In summary, the PMOS transistors’ sizing depends on
is lower or higher than
, while the NMOS
whether
is lower or greater
transistors’ sizing depends on whether
, according to the scheme reported in Table II,
than
4To simplify the inversion, (14) was obtained by expanding (1) in Taylor series
truncated to the first order, R = R (1 + R =R ) (for the 0.35- m
process described before, this leads to an error of 20%)
(15)
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
TABLE II
TRANSISTOR SIZING VERSUS BIAS CURRENT REGIONS
where three ranges of bias current can be recognized: low
, medium current ( ) for
current ( ) for
, and high current ( ) for
.
It is worth noting that in practical cases, logic gates are biased
or
range.
in the
B. Expression of Delay After Transistor Sizing Versus
The value of parasitic capacitances in the delay expression
(5) is affected by the transistor sizing, whose dependence on
changes according to the range ( ,
or ) which the bias
current belongs to.
For now, consider an SCL gate biased in the region , where,
and
are given by (17) and (14),
according to Table II,
and
are minimum. Substituting these
respectively, whilst
,
,
transistor sizes, expressions of capacitances
and
have the same dependence on bias current, that can
be expressed in the following compact way:
(18)
where and are the terminals that the capacitance considered
refers to, and the superscript refers to the biasing region . For
represents the NMOS gate-to-drain capacitance
instance,
ranging in the interval , and its dependence
expression for
,
and
on is described by the associated coefficients
. The analytical expressions of the three coefficients for all
the transistor capacitances are explicitly reported in Table III
(those not reported are equal to zero). It is worth noting that
and
they depend only on the previously assigned values of
, as well as the process used, hence they are constant in the
design.
Substituting (18) for all the capacitances into (5) using
Table III, and defining the coefficients as
(19a)
645
delay is from
due to the high value of , and has the same
expression (14) in both ranges and . Therefore, the delay
can be extended to region without
equation in the range
significant error. Analogously, for high-bias currents (both in
and at the end of range ), capacitances
the range
and
are dominant owing to the high value of
, which
and , allowing
has a unique expression (17) in both ranges
to be extended to the interval .
the model valid in the range
From an analytical point of view, the extension of (20) to other
regions can be understood by evaluating delay in regions and
, after applying the same procedure as for region . It can
be found that (18) still holds, and the resulting values of coefficients , and associated with each capacitance (reported in
Tables IV and V, for region and ) justify the extension of
(20), as numerical results in Table VI for the 0.35- m CMOS
process confirm.
In summary, the SCL gate delay can be approximately modeled with (20) regardless of the bias current, although this re.
lationship has been derived assuming
As an example, for the 0.35- m CMOS process used, this apin
proximation leads to the error in Fig. 7 (plotted versus
) with respect to
logarithmic scale in the worst case
expressions rigorously derived in each region. By inspection of
Fig. 7, it is apparent that the error is always lower than 14%, and
it can be shown that for more realistic load conditions, it is in
the order of a few percentage points.
C. Sizing of
for Power-Efficient Design
In Section IV-A, transistor aspect ratios have been expressed
being
on the basis of the NM requirement, with bias current
the only unknown design parameter. At this point, different criteria can be used to size , depending on the specific application. In this subsection, we discuss bias current sizing to minimize the power-delay product (PDP) that quantitatively expresses the efficiency of the tradeoff between delay and power
dissipation [29] to optimally balance delay and power consumption.
Since SCL gate power consumption is dominated by the static
, expression of PDP obtained from (20) is
contribution
PDP
(21)
has been considered. Equawhere a given load capacitance
given by
tion (21) is minimum for the bias current
(19b)
(19c)
we get the following expression of propagation delay of the SCL
gate versus :
(20)
Although (20) was derived assuming the gate was biased in
the region , it can also be used in the other regions. Indeed,
according to Table II, for low-bias currents (both in the range
and at the beginning of region ), the dominant contribution to
(22)
It is worth noting that the optimum current (22) does not depend
and
, which in turn
on the load, but only on coefficients
depend only on the NM specification and the process. For example, using the 0.35- m technology above described and set,
mV,
results in 10.7
ting
A (evaluated aspect ratio of NMOS and PMOS transistors are
4.2/0.3 and 0.6/1.8, respectively). Assuming a load capacitance
of 50 fF, predicted delay (20) is 1.42 ns, that differs by 20% with
respect to simulated value of 1.77 ns.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
TABLE III
CAPACITANCE COEFFICIENTS IN REGION M
TABLE IV
CAPACITANCE COEFFICIENTS
D. Sizing of
for High-Speed Design
When high-performance is required, two cases should be considered during the design of SCL gates. In the former, a delay
is given from considerations at gate level,
constraint
and the value of bias current that allows us to satisfy this spec(obviously, no soification is obtained by solving (20) for
). In the latter, no delay
lution exists if
constraint is given and the delay has to be kept as close to the
) as possible, in order
asymptotic value (obtained for
to exploit the speed potential of the circuit and the process used,
but keeping the bias current within a reasonable range.
, it is apparent that
From (20), for a given load capacitance
leads to a significant decrease in
only
an increase in
when
(23)
and in the case of strict equality, the delay is only twice the minimum achievable. Therefore, a reasonable choice to get almost
IN
REGION L
the best performance without wasting too much current is obtained when strict equality is satisfied, i.e., when
is equal to
(24)
especially for high
, as
that is much greater than
shown by comparing (24) with (22). This means that the criteria proposed leads to a high speed at the cost of a significantly worse PDP than the minimum achievable. For example,
under the same conditions as in the previous subsection and
fF,
results in the high value of 110 A
fJ [greater than value of 50 fJ obtained
that leads to PDP
using (22)]. The aspect ratio of NMOS and PMOS transistors are
41/0.3 and 2.4/0.3, respectively, while the predicted and simulated delay are 226 and 196.5 ps, respectively.
E. Remarks on Technology Scaling
To evaluate the effect of scaling on power consumption and
propagation delay for the design strategies proposed, let us conand
. From Table III, considering an
sider coefficients
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
647
TABLE V
CAPACITANCE COEFFICIENTS IN REGION H
TABLE VI
VALUES OF CAPACITANCE COEFFICIENTS
equal scaling of NMOS and PMOS parameters, the following
relationships are obtained:
(25a)
(26a)
is the unity length junction capacitance between the
where
source/drain and the substrate (including area and sidewall conis the overlap length, that is assumed to scale
tributions) and
like the minimum length.
Although the ratio between the junction capacitance and the
, as well as the ratio bechannel capacitance,
tween the threshold voltage and the power supply, increases with
technology scaling [34]–[38], to get a rough estimation we can
neglect this dependence and simplify (25a) and (26a) into
(25b)
(26b)
Fig. 7. Error of (20) with respect to the three-equation model versus bias
current for the 0.35-m CMOS process used.
By using (25) and (26) in (22), the bias current that minimizes
the PDP results
(27)
By scaling the channel length by a factor , the oxide capacitance
, while
and the power-supply voltage both scale by a factor
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
aspect ratio slightly increase [34]–[38], thus determining an in.
crease in the optimum bias current by a factor higher than
Regarding the corresponding speed, by neglecting term
with respect
, from (20) we get
formance (Section V-B). In both cases, design criteria are provided to split the assigned current allowed per gate,
, into
and
to maximize speed.
contributions
A. Buffer Used as a Level Shifter
(28a)
where (7) has been used to evaluate the scaling factor of the load
capacitance and represents the fan-out of the gate.
From (28a), the propagation delay results equal to the sum
and
have
of two terms. However, by considering that
opposite scaling factors and neglecting the scaling factor of the
aspect ratio, we can approximate (28a) by
(28b)
Thus, the propagation delay scales as the square of the minimum
length, which is much higher than propagation delay scaling
forecast for the traditional CMOS gates. Of course, consideration on PDP can be simply achieved by multiplying (27) and
(28).
Regarding the design strategy for high speed, we can simply
derive that the propagation delay is only proportional to coeffi, hence (28) still holds. Moreover, from (24) the bias
cient
current results
(29)
where parameter represents the scaling factor of the part in
the bracket which increases in a complex way as reducing the
minimum channel length.
V. DESIGN STRATEGIES OF SCL GATES WITH OUTPUT BUFFER
As clarified in Section III-A, the relationships between
and
with bias current
obtained in Section IV are still
valid in the case with an output buffer. Moreover, the delay of
can be approximated to
the internal SCL gate in (9),
must be substituted with the interconnections
(20) where
, otherwise is set to zero.
capacitance
Compared to the simple SCL gate, there are two other design
, and
parameters other than : the bias current of the buffer,
, whose appropriate
the aspect ratio of its transistors,
sizing depends on whether a buffer is added to intentionally introduce a level shifting (Section V-A) or to improve speed per-
When a buffer is used to implement a level shifter, it reduces
the common-mode output voltage of an SCL gate by the
voltage of its transistor, equal to
(30)
By inverting this expression, we determine the value of the ratio
from the assigned shift voltage,
, resulting in
(31)
has been assumed to be minimum, as occurs for
where
. Therefore, design parameters are
practical values of
and
. In particular, the current per
only the bias currents
, must be split into
and
, according to a factor
gate
that defines the amount of the total bias current
).
used in the internal SCL (accordingly,
, factor must be optimally chosen to miniFor a given
mize delay, and extensive numerical analysis shows that in prac(typically
). Hence,
is so small
tical cases
) that terms proportional to
are negligible
(
.
with respect to those proportional to
and
Using (31), substituting
, as well as substituting (20) in (9) after neglecting its
, leads to the following expression of
terms proportional to
, shown in (32) at the bottom of the
derivative
has been assumed and (31) has been used.
page, where
Equating (32) to zero and solving for , its value that minimizes
is approximately given by
(33)
which shows that, by increasing the load capacitance or the
used for
decreases as
gate current, the fraction of
and
. Extensive verification of (33) shows
that it agrees well with optimum evaluated numerically from
(32), with their difference being always lower than 25% of
the latter, and typically lower than 10%. The effect of this
difference on delay is reduced typically to a few percentage
with respect to is
points since the minimum of
rather flat, as can be observed in Fig. 8, which shows the delay
pF,
A,
of the SCL gate versus assuming
V under the conditions explained in the previous
(32)
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
Fig. 8.
Example of delay (ns) of an SCL gate with a buffer versus for C = 1 pF, I
design examples. In this case, (33) provides
, which
differs from the exact minimum 0.148 by 7%, while the
optimum delay (9 ns) is overestimated only by 0.15%.
649
= 30 A, V
= 1:2 V, in Section V-A.
This has been obtained by substituting (20) into (9), and expressing capacitances
,
as the product of their
(named
,
) and
value at minimum
the factor
B. Buffer Used to Improve Speed
, the choice
In some cases, for a given total gate current
into
of an SCL gate with a buffer (properly splitting
and
) leads to a better speed performance than an SCL gate
). In particular, this
without a buffer (biased with
is low and/or the
occurs when the available gate current
is large, as it can be seen by comparing
load capacitance
(20) and (9).
When a buffer is used to improve speed, design parameters
,
, and
must be evaluated. More specifically, design criteria are needed to split the assigned current per gate
into
and
, and to size the buffer transistor channel
(differently from Section V-A, no constraint bewidth
and
exists). To this end, let us rewrite the extween
to make its dependence on
more
pression of
explicit
(34)
(35)
that represents the channel width normalized to the minimum
results in its value at minallowed. Moreover, from (11),
,
, multiplied by
(minimum channel
imum
length has been assumed, as before).
Since (34) has to be optimized both for and , for the sake
(i.e., minimum
) and
of simplicity, first assume
as in the previous
evaluate the optimum ratio
subsection, and then optimize itself.
First, we minimize delay (34) with respect to the ratio
setting
, and, as in Section V-A,
as well as neglecting terms proportional to
assuming
in (34). Moreover, since the addition of a buffer makes
, we assume it to be much greater than
sense only for a high
(frequently satisfied in practical cases). Therefore, the
derivative of (34) with respect to becomes (36), shown at the
bottom of the page, that, equated to zero, gives the following
:
value of that minimizes
(37)
(36)
650
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
Fig. 9. Example of delay (ns) of an SCL gate with a buffer versus for C = 1 pF, I
From (37), the fraction of
used in
decreases as
when the load capacitance increases, while it dewhen the gate current increases.
creases as
Verification of (37) shows that, in the cases of interest (i.e.,
when the SCL gate with a buffer is faster than the one without
a buffer) it agrees well with an optimum , the difference always being below 30% of the latter (typically lower than 15%),
and the difference in associated delay of only a few percentage
points. For example, Fig. 9 shows the delay of SCL gate versus
assuming
pF,
A, under conditions explained in the previous design examples. In this case, (37) pro, while the exact value is 0.17, leading to about
vides
the same delay of 11.4 ns.
Once factor is optimized, further optimization is possible
by properly setting the normalized transistor channel width, ,
and
to minimize (34) after substituting
. Intuitively, the contribution of the load capacitance to delay (34) can be reduced by increasing , that in
turn determines an increase in the terms associated with
and
. Hence, an optimum value of exists, and can be
found by differentiating (34) for to obtain (38) shown at the
bottom of the page. Setting (38) to zero and solving for leads
= 30 A, in Section V-B.
to its optimum value,
, that minimizes delay as shown in
(39) at the bottom of the page.
In the cases of interest, (39) exhibits a lower than 25% error
with respect to numerical evaluation, and the delay is within 9%
of numerically minimized results due to the flat minimum, as can
be noted in Fig. 10, that shows the delay of an SCL gate versus
assuming
pF,
A, under conditions explained in the previous design examples. Equation (39) gives
, while the exact value is 63, and the associate delay values
are 2.65 and 2.74 ns, respectively, differing by 3.3%. It is worth
noting that the optimization of the buffer transistors’ size has led
to a delay reduction by a factor of four, compared to the case
with the minimum devices dealth with above in this subsection.
In general, (39) provides values of the order of several tens,
which are not always acceptable due to the area increase. Howwith respect to is very flat,
ever, the minimum of
as shown in Fig. 10, therefore can be reduced without a significant delay increase. Typically, reducing by a factor of two
leads to a delay increase of 10%, whilst with a factor of four the
delay increase is about 30%. To accurately estimate the delay
increase for a given reduction of with respect to (39), it is
preferable to resort to (34).
(38)
(39)
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
Fig. 10.
Example of delay (ns) of an SCL gate with a buffer versus for C = 1 pF, I
651
= 30 A, in Section V-B.
VI. CONCLUSION
APPENDIX I
In this paper, a strategy for the design of SCL gates has been
proposed. The strategy is based on simple analytical models
for the delay and NM of SCL gates, both with and without
an output buffer. The models have been validated by extensive
Spectre simulations using a 0.35- m CMOS process, and the
results confirm that the model is accurate enough for design
purposes.
Starting from model equations, closed-form design equations
were derived both for the transistor aspect ratios and bias current
to meet design goals concerning NM and delay. To this end, the
transistor aspect ratios were first expressed as a function of bias
current for an assigned value of NM, according to the practical
criteria introduced. Successively, the bias current was sized in
practical design conditions, assuming that either a high-performance or a power-efficient design is required. The design criteria developed have also been extended to the case of SCL gates
with an output buffer, providing guidelines for optimally distributing the available bias current per gate among the internal
stage and the buffer, as well as for sizing the transistor buffer
aspect ratio.
Due to the static power dissipation of SCL gates, the powerdelay tradeoff (measured by the PDP) was analytically evaluated, with the resulting design equations being quite simple,
thus providing the designer with the necessary understanding
of the mutual dependence between delay and power consumption. Therefore, the criteria proposed allow the designer to consciously manage tradeoff from the early design phases, avoiding
tedious simulation iterations.
According to the BSIM3v3 MOSFET model, the expression
valid for both NMOS and PMOS tranof the drain current
sistors working in the linear region is [26]
(A1.1)
models source-drain parasitic resistances, Taylor exwhere
[27],
pansion has been applied assuming
is given by
and parameter
(A1.2)
whose parameters are reported in the following with the subscript if referred to a PMOS transistor, and subscript in the
and are
case of an NMOS transistor. In (A1.2), parameters
is the oxide capacithe effective channel width and length,
is the threshold voltage,
and
are the
tance per area,
is the effective
gate-source and drain-source voltages, and
carrier mobility defined as shown in (A1.3a) at the bottom of the
is the critical electric field at which carrier
page, where
,
, and
are model paramevelocity becomes saturated,
is oxide thickness. It is worth noting that terms inters, and
model the mobility degradation due to the vertical
cluding
electric field in the MOS transistor, while those including
model the carrier velocity saturation due to the lateral electric
(A1.3a)
652
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 5, MAY 2003
Fig. 11. Typical trend of output voltage v versus input voltage v in an SCL inverter.
field. Moreover, in (A1.2) parameter
than unity and is given by
is slightly greater
To evaluate the PMOS equivalent resistance
defined
, consider (A1.2) and observing that
is small
as
and
for the PMOS transistors, neglect terms
both in (A1.2) and (A1.3), leading to
(A1.5)
represents the “intrinsic” resistance of the PMOS
where
transistor in the triode region, given by
(A1.4)
(A1.6)
which depends on , and various other BSIM3v3 model pacan be simplified by considering its
rameters. Function
, setting
to its minimum value
maximum value,
and maximizing the resulting function with respect to , with
straightforward calculations (as an example, for the PMOS tranV we get
sistor in a 0.35- m CMOS process and
).
to be
It is worth noting that with the gate-source voltage
small enough to neglect mobility degradation such as for M1
and M2, (A1.3a) simplifies into
(A1.3b)
whose value depends on the model parameter
and the bias value of
fective channel length
, the ef.
Therefore, from (A1.1) and (A1.6), the equivalent resistance
results
(A1.7)
APPENDIX II
The NM of an SCL gate can be obtained from the expression
of output voltage as a function of input voltage assuming
transistor operation in the saturation region [33] as shown in
(A2.1) at the bottom of the page, whose typical trend is plotted
versus the input voltage, , in Fig. 11. It is worth noting that
(A2.1) is symmetrical with respect to zero.
if
if
if
(A2.1)
ALIOTO AND PALUMBO: DESIGN STRATEGIES FOR SOURCE COUPLED LOGIC GATES
653
(A2.2)
The NM is defined as
(or, equivalently, as
, due to its symmetry with respect to zero),
and
are the input voltage values such
where
, while
and
are the corthat
and
responding output voltages (i.e.,
), as shown in Fig. 11. By differentiresults in (A2.2),
ating (A2.1) for and setting it to 1,
has been asshown at the top of the page, where
to
leads to the following
sumed. Approximating
expression of NM:
NM
(A2.3)
where
was assumed.
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Massimo Alioto (M’01) was born in Brescia, Italy,
in 1972. He received the Laurea degree in electronics
engineering and the Ph.D. degree from the University
of Catania, Italy, in 1997 and 2001, respectively.
Since 2001, he teaches courses on basic electronics
and microelectronics. In 2002, he joined the Dipartimento di Inggegneria dell Informazione (DII), University of Siena, Siena, Italy, as a Researcher. His
primary research interests are in bipolar and CMOS
high-performance digital circuits in terms of highspeed or low-power dissipation, as well as arithmetic
circuits, and recently in the design of CMOS circuits for cryptography.
Gaetano Palumbo (M’91–SM’98) was born in
Catania, Italy, in 1964. He received the laurea degree
in electrical engineering in 1988, and the Ph.D.
degree in 1993, both from the University of Catania,
Catania, Italy.
Since 1993, he conducts courses on Electronic Devices, Electronics for Digital Systems and basic Electronics. In 1994, he joined the Dipartimento Elettrico
Elettronico e Sistemistico, University of Catania as
a Researcher, subsequently becoming Associate Professor in 1998, and a full Professor in 2000. His primary research interest has been analog circuits with particular emphasis on
feedback circuits, compensation techniques, current-mode approach, and lowvoltage circuits. In recent years, his research has also embraced digital circuits
with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum
speed within the constraint of low-power operation. In all these fields he is developing some research in collaboration with STMicroelectronics of Catania.
In 1989, he was awarded a grant from AEI of Catania. He is the coauthor of
the books CMOS Current Amplifiers (Norwell, MA: Kluwer, 1999), and Feedback Amplifiers: theory and design (Norwell, MA: Kluwer, 2001). He is a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering.
In addition, he is the author or co-author of more than 180 scientific papers on
referred international journals (over 70) and in conferences. From June 1999 to
the end of 2001 he served as an Associate Editor of the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS—I, for “Analog Circuits and Filters.”