Chapter 3
CMOS Differential Amplifiers
As its name suggests, in a differential amplifier the output signal generally is the
amplified version of the difference of two inputs of the amplifier. Because of the
exclusive properties of this type of amplifier, it is considered as one of the most
important building blocks in many analog circuits. In this chapter, we first analyze
a source-coupled circuit as a differential voltage-to-current converter and then deal
with the CMOS differential amplifier in which a current mirror circuit is employed
as an active load for the source-coupled pair. This amplifier is regarded as an
integral part at the input of most single-ended output operational amplifiers so that
many properties of an op amp depend on the parameters of this block. We study
the large-signal characteristics of this amplifier in detail. Offset voltage, frequency
response, and noise behavior of the amplifier are the subjects for the rest of this
chapter.
3.1
Source-Coupled Differential Pair Characteristic
In the differential pair shown in Figure 3.1, it is assumed that M1 and M2 are
exactly the same and both operate in saturation. Furthermore, the channel length
modulation effect is ignored and it is presumed that the drain current of each
iD1
+
vi
-
iD2
M1
M2
I0
Figure 3.1 Differential pair amplifier.
33
34
CMOS Differential Amplifiers
device follows a quadratic relationship. Thus the gate-source voltage of M1 and
M2 can be written as
!fD
-e
H
t
%:ÅH2
Æ
(3.1)
where ° hY "V o p H . hY is the free electrons mobility, "V is the gate
capacitance per unit area, and o and p are the channel width and length of M1
and M2, respectively. Since !% !fD
!fD , from (3.1) we have
•®)
t !%
•®)
Æ
(3.2)
Summing drain currents at the common node of sources gives ®)
which yields
“•®)
•®) –
Substituting (3.2) into (3.3), we get
Since “•®)
•®) –
W
•®) •®)
•®)
•®) •®)
W
Æ
W
!%
®)
W,
(3.3)
(3.4)
•®) •®) , from (3.4) we obtain
•®)
t W
®)
•°W !% t
Æ
!%
(3.5)
The multiplication of (3.5) by (3.2) gives the differential current ®"Mq in terms of
the differential input voltage
®"Mq
®)
Æ 2
Ç{
(3.6)
Thus the drain current of each MOS transistor is obtained as
®)
®)
{
{
•°W t
•°W t
Æ 2
Ç{
(3.7)
Æ 2
Ç{
(3.8)
The plot of each drain current of the differential pair is illustrated in Figure 3.2.
3.1 Source-Coupled Differential Pair Characteristic
iD2
I0
35
iD1
0.5I0
-
0
2I0
β
vi
2I0
β
Figure 3.2 Differential pair drain currents versus differential input voltage.
We see that for • W ° !% • W ° both transistors conduct and when !%
goes beyond this range one of the two transistors, M1 or M2, turns off and the
entire tail current W is steered toward the other transistor. The large-signal
characteristic of the differential output current in terms of the differential input
variation based on (3.6) is plotted in Figure 3.3. As it can be seen, ®"Mq is an odd
function of !% . This means that for a large sinusoidal input voltage, the differential
output current contains only odd harmonics of the input signal frequency. Taking
the derivative of (3.6) versus !% , we can find the incremental transconductance of
the differential pair versus the differential input voltage
È0 !%
•°W
z% x‰
z
ÉS2
2Ê
/
Á /
{
tÆ
ÉS2
ËÊ
!%
{
tÆ
(3.9)
It is clear that the differential pair transconductance generally changes as an even
iout
+I0
-
2I0
β
0
2I0
β
-I0
Figure 3.3 Differential output current versus differential input voltage.
vi
36
CMOS Differential Amplifiers
function of the input signal and its small-signal value for !% … • W ° becomes
•°W .
3.2
CMOS Differential Amplifier with Active Load
A single-ended output differential amplifier can be implemented by putting a
PMOS current mirror on top of the circuit of Figure 3.1 as illustrated in Figure 3.4
[1]. In this circuit, (M1, M2) and also (M3, M4) are mutually identical with each
other and thus the tail current W is equally divided between M1 (M3) and M2
(M4) in the absence of differential input voltage. In this situation because of the
circuit symmetry, the dc voltage level at the drain of M1 and M2 is the same and
equals to
where °R hR "V o p
M3 and M4 aspect ratio.
-"#$
ŽHÇ .
-))
Ì-eR Ì
{
tÆ
(3.10)
Q
hR is the hole carriers mobility and o p
ŽHÇ
is the
3.2.1 Large-Signal Characteristic of CMOS Differential Amplifier
When an ac differential input voltage is superimposed on the bias common mode
voltage the drain current in M1 and M2 will change around its static value of W
in the opposite direction.
In the differential amplifier shown in Figure 3.5 for variation of !% in the
Figure 3.4 Single-ended output differential amplifier in dc state.
3.2 CMOS Differential Amplifier with Active Load
37
VDD
M3
M4
vo
+
+vi/2
Vcm
+
-
M1
M2
-
+
-
I0
VB
-vi/2
M5
Figure 3.5 Differential amplifier with differential input.
range of
• W ° !% • W ° , the drain current of M1 and M2 is
determined based on (3.7) and (3.8). When !% rises, due to the positive voltage
gain of the amplifier, the output voltage with a steep positive slope goes up and
M4 quickly approaches the triode region where the voltage gain starts dropping.
This occurs for a rather low positive change in !% . After M4 enters the triode
region, with more increase in !% , the output voltage !" continues to rise with a
lower rate. At the same time the tail current steers toward M1 and the current of
M2 and M4 approaches zero.
When differential input voltage reaches • W ° , the entire tail current flows
through M1 and thus M2 turns off. At this point, M4 is in triode with zero drain
current, which means the drain-source voltage of M4 is zero and thus the output
voltage is fixed on [ÍÍ . When input voltage changes in the negative direction, the
output voltage rapidly drops again due to the differential amplifier voltage gain
and this time M2 goes to the triode region. As long as the tail transistor operates in
saturation, M5 acts as a current source, and M3 with a diode connection structure
always remains in saturation. On the other hand, if the source-to-drain voltage of
M4 is more than -D)HKUq , it will operate in saturation and the current mirror
consisting of M3 and M4 forces M1 and M2 to have the same current even though
M2 is in triode and therefore the drain currents of M1 and M2 remain on W . For
large negative differential input voltage the tail transistor ultimately enters the
triode region where the tail current starts decreasing with the input. As a result, the
38
CMOS Differential Amplifiers
iD1
I0
0.5I0
iD2
0
vi
2I0
β
Figure 3.6 Variations of differential amplifier drain currents versus input.
drain currents of M1 and M2 also decrease in parallel with each other. The drain
currents of M1 and M2 versus the differential input voltage variation are plotted in
Figure 3.6. The large-signal characteristic of the CMOS differential amplifier with
a current mirror load is depicted in Figure 3.7.
3.2.2 Offset Voltage of CMOS Differential Amplifier
In a single-ended output differential pair that has perfect symmetry when two
inputs are the same, the output voltage places on -)) -DfŽ , as illustrated in
Figure 3.7. In practice, due to different mismatches in the circuit, the output dc
voltage has a different value from the ideal case. In this situation we have to apply
a differential voltage to the input in order to put the output back on -)) -DfŽ . In
such a case the applied differential input voltage is called the input-referred dc
offset voltage [2]. In the circuit of Figure 3.8 we can write
-ÎD
-fD
-fD
(3.11)
To obtain an analytic relationship for -ÎD , first we define average and
difference quantities for the circuit parameters as below
vo
VDD
VDD-VSG3
High Gain
Area
0
2I0
β
Figure 3.7 Large-signal characteristic of differential amplifier.
vi
3.2 CMOS Differential Amplifier with Active Load
39
VDD
M3
M4
Vo
ID2
ID1
M1
VOS
M2
+
−
I0
Figure 3.8 Differential amplifier with input offset voltage.
-eY
4£ÄÅ 4£Ä2
3-eY
-eY
W)
W)
°Y
H
-eY
(3.11), we have
t W)
H
-ÎD
°Y
3-eY
(3.13)
(3.14)
W)
(3.15)
ÆÄÅ ÆÄ2
3°Y
H
-eY
{:Å {:2
3W)
Since -fD
(3.12)
°Y
H
(3.16)
°Y
(3.17)
, by substituting the above expressions into
t Æ ÏÁ
{:
Ä
3Ê:
2Ê:
3ÉÄ
2ÉÄ
Á
3Ê
/2Ê:
:
3ÉÄ
2ÉÄ
/
Ð
(3.18)
After some manipulations on (3.18) and neglecting higher-order terms, we get
-ÎD
3-eY
W)Ž
W)
:
:
tÆ F {
{
Ä
In the current mirror active load we have -DfŽ
ÆQÑ
“-DfR
3{
:
-DfÇ
3ÆÄ
ÆÄ
G
(3.19)
-DfR and thus
Ì-eRŽ Ì–
(3.20)
40
CMOS Differential Amplifiers
W)Ç
W)
ÆQË
“-DfR
Ì-eRÇ Ì–
(3.21)
Again we define average and difference quantities for the current mirror circuit
parameters as follows:
Ì-eR Ì
3-eR
Ì4£QÑ Ì Ì4£QË Ì
°R
Ì-eRŽ Ì
(3.22)
Ì-eRÇ Ì
(3.23)
ÆQÑ ÆQË
3°R
°RŽ
(3.24)
°RÇ
(3.25)
By substituting the above quantities into (3.20) and (3.21) and neglecting higherorder terms, we can obtain the approximate expressions for the drain currents of
M3 and M4 as
W)Ž † W) ©
with 3W)
W)Ž
3ÆQ
W)Ç † W) ©
34£Q
¬
ÆQ
4k¡Q /Ì4£Q Ì
(3.26)
ÆQ
4k¡Q /Ì4£Q Ì
(3.27)
3ÆQ
34£Q
¬
W)Ç , from (3.26) and (3.27), we can obtain 3W) W)
3{:
{:
3ÆQ
ÆQ
34£Q
4k¡Q /Ì4£Q Ì
Now we substitute (3.28) into (3.19) and use -DfR
-ÎD
3-eY
Q
:
tÆ © Æ
{
Ä
3Æ
Q
3ÆÄ
ÆÄ
¬
(3.28)
Ì-eR Ì
• W) °R to reach
Q
tÆ 3-eR
Æ
Ä
(3.29)
where °YHR hYHR "V o p YHR . Mismatch in the size of two pairs of NMOS and
PMOS devices and also mismatch due to the difference in the gate oxide thickness
of devices represents itself as a mismatch in "V; all of them have been
summarized in two terms 3°R °R and 3°Y °Y in (3.29). It is obvious from (3.29)
that any threshold voltage mismatch in the input transistors M1 and M2 directly
appears in the input-referred dc offset voltage. This fact proves how significant it
is to have symmetrical devices at the input. In a careful design in order to achieve
maximum symmetry for M1 and M2 in the layout design, each transistor is split
3.2 CMOS Differential Amplifier with Active Load
41
into two identical parts and diagonally connected together, as illustrated in Figure
3.9. This technique is called common centroid, which makes M1 and M2 immune
from cross-chip gradients in the oxide thickness and doping and provides the best
matching performance for the circuit [3-5]. The price paid for that is to impose
more complexity on doing the layout. The common centroid technique helps to
evenly distribute the threshold voltage mismatches between two transistors that
leads to nearly zero average for 3-e . The absolute statistical variation of threshold
voltage is determined by the gate area as
@4£
£
diZ
(3.30)
where 4e is the threshold proportionality factor and depends on the technology
used. It is shown that it has a roughly linear relationship with the gate oxide
thickness [6]. From (3.30), minimum random variation in threshold voltage is
achievable by taking the maximum possible value for the MOS gate area. As
discussed later, choosing a large gate area helps to reduce the effect of the flicker
noise as well. From (3.29) it can be seen that any mismatch error in the parameters
of °Y and °R appears in the offset voltage by a weighting factor of the overdrive
voltage of the input transistors. Thus in a low-offset design we need to minimize
the input MOS device overdrive voltage. On the other hand, a small overdrive
voltage for input MOS devices results in a lower linear operating range of the
differential pair. This is a contradictory situation in a design that simultaneously
requires a low offset voltage and high linear operating range. Another interesting
point that can be deduced from (3.29) is that 3-eR as the mismatch of the load
transistors appears in the input offset voltage by a weighting factor of •°R °Y . So
minimizing this ratio can also help to reduce the total offset voltage. Moreover, as
will be shown later, a small °R °Y reduces the input-referred noise due to M3 and
M4. Every measure taken to reduce 3-eY in doing the layout for the input device
is applicable to 3-eR in the load transistors as well.
M1a
M2a
M2b
M1b
Figure 3.9 Common-centroid technique for better matching performance.
42
3.3
CMOS Differential Amplifiers
Common-Mode Behavior of CMOS Differential Amplifier
What has made a differential amplifier an important building block in analog
systems is its capability to amplify the differential changes at its input in the
presence of a large common-mode voltage. In an ideal differential amplifier we
expect that the amplifier output just changes in response to the differential part of
its input and any change in the input common mode does not impact on the output
voltage. This capability can provide a good immunity for the circuit against the
existing common mode noise and as a result raise the circuit performance,
especially in a noisy environment. In practice, the output of a differential amplifier
consists of the amplified voltage of both differential and common-mode parts of
the input
!"
(3.31)
#0 !%#
$0 !%$
where #0 and $0 express the amount of contribution of differential and
common-mode components at the output, respectively. In a good differential
amplifier the common-mode voltage gain of $0 is normally much less than the
differential voltage gain of #0 . In order to quantify the performance of a
differential amplifier in rejecting the input common mode variations, a parameter
called common-mode rejection ratio (CMRR) is defined as
& ''
*
+5
,5
*
(3.32)
To see what parameters of the amplifier can considerably affect $0 , we replace
the small-signal equivalent circuit for the amplifier of Figure 3.5, as illustrated in
Figure 3.10. In this circuit only the common-mode component of the input has
been considered and both body effect and ac output resistance of M1 and M2 are
neglected. 'q is the equivalent output resistance of the tail current source.
Summing voltages around the loop containing the input voltage 3-%$ , gate-source
voltage of M1 or M2 and potential across 'q , we obtain
3-%$
!
X0
Summing currents at the output node, we have
X0Ž !Ž
X0 !
X0 'q !
. Ë
(3.33)
(3.34)
Noting that !Ž
Ò"Ž Ó
X0Ž X0 ! and using (3.33) and (3.34), we can
obtain the common-mode gain as
3.4 CMOS Differential Amplifier Frequency Response
v3
43
gm4v3
ro3||(1/gm3)
ro4
+
∆Vic
+
vo
-
+
v
gm1v
-
gm2v
∆Vic
Rt
Figure 3.10 Small-signal equivalent circuit of differential amplifier for calculating common-mode
voltage gain.
Assuming Ò"Ž
$0
34 ,
Ô
¿
¯5Å /¯52 . Ñ / 52
¿5Ñ
Å
¯5Å ¯52 8‰ ÕF. Ñ
G
¿5Ñ
Ò"Ç
(3.35)
X0Ž and Ò"Ž † Ò"Ç , we can approximate (3.35) as
$0
¿
¯5Å /¯52 . Ñ / 52
¿5Ñ
¯5Å ¯52 8‰
(3.36)
From (3.36) we see the mismatch between M1 and M2 (X0 Ö X0 ) and the finite
output resistance of the tail current source 'q are two main reasons that cause the
differential amplifier to have a nonzero common-mode voltage gain. In order to
improve the CMRR parameter the matching between the input transistors is
important. In addition, the circuit used to implement the tail current source should
provide enough large output resistance (high 'q ).
3.4
CMOS Differential Amplifier Frequency Response
The study of the behavior of both differential and common-mode voltage gains
( #0 and $0 ) of a differential amplifier in the frequency domain is important.
Indeed, the first shows how fast the amplifier is able to follow the rapid changes in
the input differential signal and the second provides a figure of merit for the
44
CMOS Differential Amplifiers
amplifier about its capability to attenuate high-frequency disturbance signals that
appear at the input as common-mode noise. To simplify the frequency analysis we
consider only two main internal capacitances of the circuit that form two largest
time constants at their corresponding nodes. Figure 3.11 shows a differential
amplifier where
represents the gate capacitance of the current mirror load and
is
the
total
capacitance
including the load capacitance at the output node.
•
The equivalent resistance seen at node A is rather small ( X0Ž ) but its
parasitic capacitance
that mainly consists of the gate-source capacitance of M3
and M4 could be considerable in such a way that its corresponding time constant is
noticeable. The high resistance at the output and the equivalent capacitance at this
node create the dominant time constant of the circuit at this node. The highfrequency small-signal equivalent circuit of Figure 3.11 is depicted in Figure 3.12
in which we have ignored the body effect in M1 and M2 and also neglected the
output resistance of the tail current. It is also assumed that two pairs of (M1, M2)
and (M3, M4) are mutually symmetrical. The transconductance and output
resistance for NMOS devices are denoted by X0w and Ò"w , respectively, and those
of PMOS devices by X0× and Ò"× . Before writing the required equations to obtain
the circuit transfer function, first we replace the indicated lower-part of the circuit
with its Thevenin equivalent circuit. This can be done by replacing the two
voltage-controlled current sources by their Thevenin equivalent circuits as
illustrated in Figure 3.13. The equivalent Thevenin voltage and resistance are
-q X0w Ò"w - X0w Ò"w -% and 'q
Ò"w , respectively. By replacing the
lower-part circuit in Figure 3.12 with the Thevenin equivalent circuit, we get a
simplified form of the small-signal equivalent circuit shown in Figure 3.14 where
Ø
X0× ½
and Ø• Ò"×
Ò"× • ½ are the impedances obtained
VDD
M3
A
M4
CA
B
Vo
CB
+
M1
M2
vi
I0
Figure 3.11 Differential amplifier with two main capacitances impacting on frequency response.
3.4 CMOS Differential Amplifier Frequency Response
roP||(1/gmP)
v3
+
Thevenin
Equivalent
+
vi
+
v1
-
CA
gmPv3
roP
CB
A
+
vo
-
B
roN
gmNv1
45
+
roN v2
gmNv2
-
Figure 3.12 High-frequency small-signal equivalent circuit for differential amplifier.
from the parallel combination of
with
X0× and that of • with Ò"× ,
respectively. Summing voltages around the loop in Figure 3.14, we obtain
Substitution of -Ž
Since -"
Ø•
Ø
Ø•
'q W
Ø W in (3.37) gives
W
X0× Ø• -Ž
4‰
Ù1 Ù¨ 8‰ ¯5Ú Ù1 Ù¨
X0× Ø W and -q
Rt
-q
Vt
+
B
roN
roN
−
+
(3.38)
X0w Ò"w -% , we can obtain the circuit
A
-
(3.37)
−
+
gmNroNv1
Figure 3.13 Circuit for obtaining Thevenin equivalent circuit.
gmNroNv2
46
CMOS Differential Amplifiers
v3
I
ZA
ZB
+
+
−
Rt
gmPZBv3
vo
Vt
+
−
Figure 3.14 Simplified small-signal equivalent circuit.
voltage gain in the s-domain as follows:
-"
4 ½
-%
. Û . Ú 61 6¨ K 2 Ô61 . Ú
¯5Û . Û . Ú
. Û . Ú
¯5Ú K61
¯5Ú . Û 6¨ ÕK
¯5Ú . Û . Ú
(3.39)
Assuming the transfer function has two real poles, we can write the general form
of this function as
4
where
v
ÜÝ
v
v
©
¬
ÜQÅ
ÜQ2
½
4
4
¯5Û ¯5Ú . Û . Ú
¯5Ú . Û . Ú
©
LÞ
¯5Ú
61
(3.40)
(3.41)
(3.42)
Supposing LR is the dominant pole of the circuit (LR … LR ), from (3.39) and
(3.40) we can determine the approximate value of LR as
LR
61 . Ú
¯5Ú . Û . Ú
. Ú
¯5Ú . Û 6¨
. Û
C TC
and
LR
. Û Ó. Ú 6¨
¯5Ú . Û
. Û 61
(3.44)
In practice X0× Ò"w Ò"×
and (3.41) can be simplified as 4
X0w Ò"w Ó Ò"× . In (3.43) the second term in the denominator is much greater than
3.5 Noise Calculations in CMOS Differential Amplifier
47
the first one and thus the dominant pole can be approximated by
LR
. Û Ó. Ú 6¨
(3.45)
The first term in (3.44) is much less than the second one and also X0× Ò"w
so that we can approximate the second pole as
LR
¯5Ú
61
,
(3.46)
The nondominant pole is created by the current mirror circuit, hence known as the
mirror pole. The magnitude of this pole is half of the left-hand-side zero in the splane. The gain magnitude ¹ 4 ÀL ¹ and phase ß 4 ÀL are plotted versus
frequency in Figure 3.15
3.5
Noise Calculations in CMOS Differential Amplifier
A noisy differential amplifier can be viewed as a noiseless two-port network in
which all internal noise generators are modeled as two generally correlated voltage
and current noise sources at the input, as illustrated in Figure 3.16. In a CMOS
|AV(jω)|
AV0
ωp1
ωp2
ωz
ω
AV(jω)
0
-45
ω
o
-90o
Figure 3.15 Gain magnitude and phase versus frequency for CMOS differential amplifier.
48
CMOS Differential Amplifiers
RS
+
vs
-
V2n,i
RS
+
vs
Noisy
Differential
Amplifier
-
+
I2n,i
-
Noiseless
Differential
Amplifier
Figure 3.16 Amplifier noise viewed as equivalent input voltage and current noise sources.
differential amplifier for low-frequency operation, the input impedance is typically
much greater than the source resistance 'D and thus áááá
-YHà is the dominant noise
áááá
source. To calculate for
a
differential
amplifier,
we
first introduce the main
YHà
noise sources in an MOS device. In an MOS transistor the channel thermal noise
current and the flicker noise voltage are considered as the two main sources of
noise. When a transistor operates in saturation there is an inversion layer under the
gate with a limited resistance. This resistor like any other resistor generates some
thermal noise current whose mean-square is given by
WâY
T‘ãÈ3
(3.47)
where ‘ is Boltzmann’s constant with the value of CA ‹ / Ž š ›œ, ã is
temperature in ›œ, È
' is the conductance, and 3 is the bandwidth on which
noise is calculated. The inversion layer conductance in a long-channel NMOS
device that operates in saturation can be shown to be [7]
X#K
Ž
hY
i
"V Z
-fD
-e
(3.48)
In (3.48) hY "V o p -fD -e is the channel conductance when an MOS
device operates in triode with a zero drain-source voltage that is usually denoted
by X#K . On the other side, this term is similar to the relationship for the
transconductance of a long-channel MOS transistor working in saturation so it can
also be represented by X0 . For short-channel devices, some physical phenomena
such as hot electron effects occur that affect the effective channel resistance.
Therefore, the general relationship for the mean-square of the channel thermal
noise current is expressed as
WâY
T‘ã’X0 3
C T;
where ’ is a factor inserted to consider the short-channel effects with a value of
2/3 for a long-channel condition and higher value in short-channel situations. It
should be pointed out that in short-channel condition MOS transconductance has
more complex relationship and X#K cannot be simply replaced by X0 In a more
accurate relationship X0 in (3.49) is replaced by X0 ¾ in which ¾ is defined as
3.5 Noise Calculations in CMOS Differential Amplifier
¾
49
X0 X#K with the value of less than unity [8-9].
The channel noise current can be added in parallel with the voltage-controlled
current source in the small-signal equivalent circuit of an MOS device, as depicted
in Figure 3.17. In this circuit, we have
®
X0 !¯K
WY
X0 !¯K
{Ä
¯5
(3.50)
¼
By defining !¯K
!¯K !Y where !Y WY X0 , the noisy MOS device acts like a
noiseless device with the noise voltage !Y added to its ac gate-source voltage.
Another important noise source in an MOS device is flicker noise. The origin
of this type of noise in MOS devices is attributed to the lattice defects at the
interface of the silicon and gate oxide at the surface of the device. Dangling bands
and stress due to the different sizes of the silicon atoms and silicon dioxide
molecules at the interface of the silicon and gate oxide are the main reasons to
create energy states inside the silicon bandgap at the surface. These states act as
traps to randomly capture and release the channel carriers in such a way that
causes some fluctuation in the device threshold voltage. The time constant of the
capture and release process is in the range of a few tenths to several milliseconds
and thus the corresponding flicker noise has the most energy at low frequencies.
The mean-square of the flicker noise voltage is given by
-Y
‡
iZ6 —
3
(3.51)
where } is the flicker noise coefficient that depends on the technology and the
type of the device. Channel thermal noise and flicker noise voltages are generally
uncorrelated and thus the total input-referred noise voltage represented at the gate
of an MOS device is given by
i
G
+
D
gmvgs
vgs
ro
In
S
Figure 3.17 MOS device small-signal equivalent circuit including channel thermal noise current.
50
CMOS Differential Amplifiers
áááá
-YHà
F
ǘe¸
‡
¯5
iZ6 —
G3
3.52)
Now by adding an equivalent noise voltage source in (3.52) at the gate of each
transistor in a differential amplifier, we can calculate the effect of each noise at the
amplifier output and then by dividing the result by the low-frequency gain of the
amplifier reaching the equivalent input-referred noise voltage. Assuming that
transistor noises are uncorrelated, we calculate the total input-referred noise
voltage by adding the mean-square values of all transistor noises referred to the
amplifier input. The CMOS differential amplifier including all equivalent noise
voltages at the gates of transistors is shown in Figure 3.18.
Utilizing (3.52), we can write the noise contribution of each device at its gate
as
áááá
-Yä
©
ǘe¸
¯5å
‡å
iå Z å 6 —
¬3
À
H HCHTH=
(3.53)
Denoting the total input-referred noise voltage by ááááá
-YHàY , from Figure 3.18 we see
that áááá
-Y and áááá
-Y associated with the noise contribution of M1 and M2 directly
appear in áááááá
-YHàY . In order to calculate the noise contribution of M3 while only
-YŽ by X0Ž
considering áááá
-YŽ and setting other noise voltages to zero, we multiply áááá
to obtain the equivalent noise current at the drain of M3 and then replace the
small-signal equivalent circuit of Figure 3.18 as illustrated in Figure 3.19, in which
Ò"w represents the drain-source series resistance of M1 and M2 while it is
assumed that Ò" æ. Summing currents at node A, we have
where WYŽ
®
X0× !Ž
WYŽ
(3.54)
Ò"× ®
X0× !Ž
(3.55)
X0Ž -YŽ. We can also write
-Y"Ž
!Ž
The solution of above equations gives
In practice, X0× Ò"w
approximated as
Ò"×
-Y"Ž
Ò"w ®
-Y"Ž
. Ú / ¯5Ú . Û . Ú
W
¯5Ú . Û . Ú YŽ
and X0× Ò"w Ò"×
-Y"Ž
'"Mq WYŽ
(3.56)
(3.57)
Ò"× and thus (3.57) can be
(3.58)
3.5 Noise Calculations in CMOS Differential Amplifier
51
VDD
v2n3
v2n4
M3
M4
v2no
v2n1
v2n2
M1
M2
v2n5
M5
Figure 3.18 CMOS differential amplifier with noise contribution of all devices.
where '"Mq Ò"w Ó Ò"× . In the same way, we can obtain the noise contribution of
M4 at the output
. Ú ¯5Ú . Û . Ú
WYÇ
(3.59)
-Y"Ç
¯5Ú . Û . Ú
Applying the same approximations used for -Y"Ž , we reach the same result (i.e.,
-Y"Ç '"Mq WYÇ ). Since M3 and M4 can be considered identical, WYŽ WYÇ and
their mean-square is given by
áááá
WYŽ
áááá
WYÇ
In3
FT‘ã’X0×
X0×
‡Q
iÚ Z Ú 6 —
G3
(3.60)
v3
1/gmP
+
gmPv3
A
roP
2roN
Vn,o3
i
Figure 3.19 Small-signal equivalent circuit for calculation of M3 noise contribution.
52
CMOS Differential Amplifiers
where o× and p× are the channel width and length of PMOS load transistors (M3,
M4). The noise contribution of M3 and M4 in the total input-referred noise of ááááá
-YHàY
is obtained by dividing -Y"ŽHÇ by the amplifier low-frequency gain, X0w '"Mq .
Using (3.60), we have
áááááááá
-YHàY ŽHÇ
ááááááááá
4Ä2 ÑHË
ç
¯5Û 8 x‰ 2
ǘe¸¯5Ú
2
¯5Û
‡Q
iÚ Z Ú 6 —
F
¯5Ú
¯5Û
G è3
(3.61)
Based on (3.61) a large transconductance value for the input transistors M1 and
M2 can help to reduce the contribution of the thermal noise component of the load
transistor at the input. To reduce the contribution of the load flicker noise
contribution, first it needs to choose the largest possible gate area for M3 and M4
and then for a particular value of X0w , we need to minimize the load transistors
transconductance X0× . As discussed earlier, these measures also aid the designer
in reducing the effects of the load transistor mismatches on the input-referred
offset voltage. The noise current of the tail transistor flows through both M1 and
M2 as a common-mode current. As a result the amount of variation at the drain of
M1 and M2 due to this current is the same. Noting this point, to calculate the noise
effect of the tail transistor on the output noise, we first obtain the small-signal
voltage gain from the gate of M5 to the drain of M1. In Figure 3.18 the equivalent
resistance seen at the drain of M5 is
X0w and thus -Y appears at its drain as
( X0 -Y
X0w ). This voltage is amplified by the common-gate stage
consisting of M1 and M3 as its diode-connected load with the gain of
( X0w X0× ). The total voltage gain from the gate of M5 to the drain of M3 and
correspondingly to the output node of the differential amplifier will be
( X0
X0× ). The output noise due to the noise of M5 is obtained as
áááááá
-Y"
F
¯5é
Ç ¯5Û
G áááá
-Y
(3.62)
Dividing (3.62) by the square of the differential amplifier voltage gain, we can
obtain the noise contribution of the tail transistor in the total input-referred noise.
It should be noted that the coefficient of áááá
-Y in (3.62) is usually small. As a result,
when áááááá
-Y" is divided by the square of the differential amplifier voltage gain, the
input-referred noise owing to M5 will be negligible in comparison to that of the
other four transistors and the total input-referred noise of the CMOS differential
amplifier can be approximated as
ááááá
-YHàY
áááááá
-Y H
¯
áááááá
-YŽHÇ F 5Ú G
¯5Û
(3.63)
For X0× X0w … , from (3.63) we notice that M1 and M2 have the most
contribution to the input-referred noise. This noise can be minimized by increasing
3.6 Conclusion
53
both the gate area and transconductance of the input transistors M1 and M2.
3.6
Conclusion
In this chapter the large-signal and small-signal behaviors of an MOS differential
pair with a current mirror as its active load were studied. In the structure of an op
amp, a differential amplifier usually appears as the first stage. This causes several
important op amp parameters such as input offset voltage, common-mode rejection
ratio, and input-referred noise mainly affected by this stage. As a result an accurate
examination of the parameters of an MOS differential amplifier can help to design
a more realistic CMOS op amp. The input-referred offset voltage was defined and
some proper techniques to reduce this error voltage presented. The frequency
response of the amplifier was calculated and finally the noise behavior and
corresponding relationships in such an amplifier were briefly discussed.
References
[1]
Jaeger, R. C., Blalock, T. N., Microelectronic Circuit Design, McGraw-Hill, 2007, Ch. 15.
[2]
Witte, F., Makinwa, K., and Huijsing, J., Dynamic Offset Compensated CMOS Amplifiers,
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[3]
Baker, R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons,
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[4]
Hastings, R. A., The Art of Analog Layout, Second Ed., Pearson Prentice Hall, 2006.
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[6]
Pelgrom, M. J. M., Duinmaiger, A. C. J., and Welbers, A. P. G., “Matching Properties of MOS
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