Circuits, Devices, Networks, and Microelectronics
CHAPTER 15. EMITTER/SOURCE COUPLED PAIRS and DIFFERENTIAL TOPOLOGIES
15.1 INTRODUCTION
Circuit topologies that yield an output which is proportional to the difference between two inputs are
known as difference (differential) amplifiers, or diffamps, as represented by figure 15.1-1
Figure 15.1-1. Differential amplifier, generic context
Note that this symbol is the same as that for the operational amplifier (opamp). The opamp is a special
case of a diffamp, one with high voltage gain and high input resistance. The opamp uses the differential
input to compare one input to another fed back from the output, and in concert with its high gain and high
input resistance creates a nearly ideal nullator input.
The differential amplifier circuit primitive is relatively simple and commonly will be deployed within a
large circuit construct as a subcircuit. It is little more than a coupled pair of transistors with the two
differential inputs being the control nodes for the two transistors, as represented by figure 15.1-2.
The dependent control nodes, which for the BJT and the FET are the emitter and source nodes,
respectively, then offer a natural common coupling point. Because these nodes are dependent the action
of one transistor will influence the other and so the current IZ can then be steered from one transistor to
the other, which is exactly what a differential input should do.
Figure 15.1-2. Differential coupled pair , generic context
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The figure also shows that the shared node is sourced by a fixed current. This usage is collateral to the
fact that transistors are devices in which control the levels of current passing through them. Therefore
15.1-2 the flow of current flow obeys
I Z  I1  I 2
(15.1-1)
for which the current IZ is ‘steered’ between the transistors according to their relative input levels.
The rest of the story is that the differential pair topology is designed for symmetry. The voltage rails are
bipolar and of equal magnitudes. Devices Q1 and Q2 are as identical as their manufacture allows. The
inputs will therefore steer their transistors relative to the ground node, which makes both the usage and
analysis relatively simple.
15.2 THE EMITTER-COUPLED PAIR (ECP)
If the transistors are BJTs (Bipolar Junction Transistors) the figure becomes one like that of figure 15.2-1
with the labeling nomenclature as indicated:
Figure 15.2-1.
Emitter coupled pair (ECP).
Equation (15.1-1) becomes
I EE  I E1  I E 2
(15.2-1)
for which the emitter currents are related to their inputs by
I E1  I ES exp V BE 1 / VT 
(15.2-2a)
I E 2  I ES expV BE 2 / VT 
(15.2-2b)
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where VT is the thermal voltage and VBE = VB - VE .
It is the ratio between IE1 and IE2 that gives us the current steering factor
I E1
 expVBE1  VBE 2  / VT 
I E2
 expVI / VT 
(15.2-3)
since VB1 = V1 and VB2 = V2 and VI = V1 – V2.
Note that VE1 = VE2 = common to both transistors.
And for convenience we may rewrite (15.2-3) as
I E1
 e
I E2
(15.2-3a)
I E2
 e 
I E1
(15.2-3b)
And likewise
These equations can be carried back to equation (15.2-1) by
I EE
I
 1  E2
I E1
I E1
or
 1  e 


(15.2-4a)


(15.2-4b)
I E1  I EE 1  e 
And likewise
I E 2  I EE 1  e 
The outputs (notice that there are two) are usually taken off the collector nodes VC1 and VC2, also known
as the ‘stiff’ (current source) nodes of the transistor. The steered currents relate to the output nodes VC1
and VC2 according to
Vout  VC1  VC 2   RC I C1  I C 2 
  F RC I E1  I E 2 
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(15.2-5)
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where F is the collector/emitter current factor. Equation (15.2-5) can be combined with (15.2-4a) and
(15.2-4b) as
 I EE
I EE

Vout   F RC 

1  e 
 1 e

or
 

 e / 2  e  / 2

   F RC I EE   / 2
 / 2

e e
 V
Vout   F RC I EE tanh  / 2    F RC I EE tanh  I
 2VT






(15.2-6)
This result is plotted in figure 15.2-2 and affirms that the output characteristics of the ECP are not only
symmetric but are approximately linear about VI = 0, as desired.
Figure 15.2-2. Transfer characteristics of emitter-coupled pair.
The linearity is affirmed by an analysis in terms of small signals (on the order of a few mV). Then we
may assert the approximation tanh( x)  x . Then
 v
vout   F RC I EE  I
 2VT

 I
   F EE

 2VT

 RC v I   g m RC v I

(15.2-7a)
Or, more simply, as the transfer ratio (= voltage amplification)
v out
  g m RC
vI
(15.2-7b)
This result corresponds to the approximately linear part of the transfer characteristics shown by Figure
15.2-2 centered about vI = 0.
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The fact that each of the inputs are taken at the base node and the outputs are at the collector nodes also
let us interpret the circuit as two CE (common-emitter) topologies facing one another, as shown by figure
15.2-3
Figure 15.2-3. The emitter-coupled pair as two CE configurations facing one another. The CE
configuration usually includes an emitter bias resistance R4, as shown.
For the CE configuration (past chapter) the no-load transfer gain is (approximately)
vout
R3

vI
1 g m  R4
(15.2-8)
And if we take the output off of one side (usually the Q2 side) only half of vout will be resolved and the
single-ended output form will be
v L 1 R3 || RL
 
v I 2 1 g m  R4
= AVS
This context is represented by the topology of figure 15.2-4.
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(15.2-9)
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Figure 15.2-4. Single-ended ECP with load at the output.
Notice that we have suddenly discovered what is inside figure 15.1-1. Figure 15.1-1 was
presented as the generic diffamp and as a look-alike to the opamp except with finite gain. And
for this topology the gain is finite and given by equation (15.2-9).
Figure 15.2-4 also reveals that, with the single-ended topology, there is no need for Q1 to drive a
load R3. And so Q1 serves only as a current steering transistor. The resistance path between the
two inputs is represented by figure 15.2-4(b), which shows that Rin is the input resistance to the
base Q1 and is in series with the same resistance for transistor Q2.
Rin  2 RiB  2 F 1 g m  R4 
(15.2-10)
Considering the fact that the output is that for a CE configuration the output resistance is then
Rout  R3 || rouyt  R3
(15.2-11)
Where rout is the output resistance into the collector. The approximation is a good one since it is always
true that rout >> R3 .
Each half of the emitter-coupled pair (ECP) is a CE topology all by itself and will have a finite gain all by
itself. Each side will have the same gain in common, which then becomes identified as the commonmode gain, as represented by figure 15.2-4.
The common-mode gain is not large because the current source has a strong debiasing effect on the
common-emitter half, as represented by figure 15.2-5.
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Figure 15.2-5. ECP as two half-circuits, each of the CE topology. The current source also is split into
two halves, as is its conductance. The half conductance, GEE/2, is shown as 2REE in the half circuit.
The half circuit is the same as a CE configuration with a debiasing resistance in the emitter leg of value
R4'  R4  2REE  2REE
(15.2-12)
For which the gain of the common-mode half , equivalent to a CE (common-emitter) half, is
v LCM
R || RL
R || RL
 3
 3
'
v ICM 1 g m  R4
2 REE
≡ ACM
(15.2-13)
For any and all differential circuits the ratio of AVS to ACM is called the common-mode rejection ratio
(CMRR) and in the ratio of equations (15.2-9) and (15.2-13), for which
CMRR 
AVS
ACM

R EE
1 g m  R4
(15.2-14)
The resistance REE is expected to be large because it belongs to the current source. And the resistance of
an ideal current source is infinity.
15.3 CURRENT SOURCES FOR THE EMITTER-COUPLED PAIR
The entire context of current steering relies on the current source. It is assumed to be a reasonably ‘stiff’
source, which implies that IEE = constant for almost any voltage across the source, which also implies that
that REE = large.
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The fact that a stiff current source is a requirement also identifies the circuit and device context that is
needed, which is little more than the ‘stiff’ node of a transistor. For the BJT this node is the collector
node. The simplest circuit choice is one that has been encountered before, i.e. the simple current mirror
shown by figure 15.3-1.
Figure 15.3-1. Simple current mirror using BJTs.
The finite slope at the output of the current mirror is the conductance
gO 
I
I C
 C
VCE V A
(15.3-1)
where VA is the Early voltage, which in spice vernacular will be listed as parameter Vaf. For the ECP this
slope will translate into
V
(15.3-2)
REE  1 g O
 A
I EE
Typical Early voltages are VA = 75V, as represented by that for the 2n3904 (Note: It is the pspice model
file where this type parameters will be found). Typical device characteristics as represented by the I-V
characteristics (single trace) for the en3904 are shown by figure 15.3-2.
Figure 15.3-2. I-V trace rendered by pspice for npn BJT current mirror. The transistors are of
type 2n3904 npn, which has VA = 74.1V. For the current and the slope indicated, REE = 53 k.
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Circuits, Devices, Networks, and Microelectronics
Also notice that the trace shown by figure 15.3-2 has a small but finite VCE that must be achieved before
the transistor output reaches its stiffness level. This constraint is also called the compliance and
represents a limitation on the circuit imposed by the current source. For the BJT the compliance is
relatively small and is one of the reasons that the BJT is favored over the FET for differential-pair
circuits.
The rest of the story is that the characteristics of the current source play a significant role in the
performance of the coupled pair. There are a myriad of current sources, most of which sacrifice
compliance for stiffness, for example the Wilson mirror, (topology represented by figure 15.3-3) has an
output resistance that is
`
1
(15.3-3)
REE   F rO
2
The enhanced output resistance of the current source has a strong impact on the CMRR per equation
(15.2-14). The output trace as generated by pspice for the Wilson mirror and shown by figure 15.3-4
shows that the Wilson current source is very stiff. The trade-off is that there is a noticeable increase in
the compliance limit.
Figure 15.3-3. Wilson current mirror using BJTs.
Figure 15.3-4. I-V output trace for the Wilson mirror using discrete npn transistors. Rendered
by pspice . The current is very stiff and the slope is very flat, with REE = 2.65M
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The trace is for Ic = 1.4mA as selected by Rx . The transistors are all of type 2n3904. The compliance is
approximately 0.7V.
The increase in stiffness of the current source is due to feedback to the base of the output transistor Q3 by
the topology loop formed by transistors Q1 and Q2. Other high REE (shown as ROC) topologies will do
likewise. In all cases the output transistor will be debiased by a component in the emitter leg which either
applies a feedback condition to the emitter or a feedback loop to the output transistor (Q3 for the Wilson
mirror). Current mirror topologies may be of type npn or pnp. The npn type topologies were used for
illustration. The pnp types usually have a lower value of REE due do a lower value of VA.
15.4 TOPOLOGY OPTIONS for the EMITTER-COUPLED PAIR
It should be evident from the section on current mirrors that there is a sizeable menu of options for the
ECP. The rest of the story is that there are more options, e.g. for a higher input resistance than that
afforded by figure 15.2-4 and equation (15.2-10). This is reflected by figure 15.4-1 for which the ECP
may have a Darlington-pair input, with concurrent increase in the input resistance, with some loss of the
input range due to the increased VBE bias level.
Figure 15.4-1. Darlington pair inputs with simple current mirror current source.
EXAMPLE 15.4–1: A PC board circuit using 2n3904 transistors is used to construct a Darlington-pair
input circuit as shown by figure 15.1-1. Assume F = 100. The Early voltage for the 2n3904 is
approximately 75V.
Determine ECP circuit characteristics Rin, vL/vI and the CMRR for
(1) Rx = 50k (as shown) and
(2) Rx = 25k.
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SOLUTION: (1) For the current source shown IR = [5.7 – (-5.0) – 0.7V]/50k = 0.2mA.
So IEE is approximately = 0.2mA,
and REE = VA/IEE = 75/0.2 = 375 k.
Transconductance gm = 40 × IEE/2 = 40 × 0.2/2 = 4.0mA/V
S for the Darlington pair is
(F 2 + 2F) = 10200
So Rin = 2S × (1/gm) = 2 × 10200 × 1/4
The voltage gain AVS =
Common-mode gain
= 5.1 M
vL 1
 g m  40 || 60 =
vI 2
ACM 
(1/2) × 4.0 × 24
40 || 60
= 24/750
2  375
= 48 V/V
= 0.032V/V
Then the CMRR = 48/0.032 = 1500 or 63.5dB
(Note: CMRR is usually expressed in terms of dB.)
(2) For Rx = 25 k, the current IEE is increased by a factor of two.
So REE is decreased by a factor of two = (375/2) k
and gm is increased by a factor of two, i.e. gm = 8mA/V
for which the input resistance will then be
The voltage gain AVS will be
Rin = 2 × 10200 × 1/8
vL 1
 g m  40 || 60 = (1/2) × 8.0 × 24
vI 2
The common-mode gain ACM will be
ACM 
40 || 60
2  375/ 2
Then the CMRR will be AVS/ACM = 96/0.064 = 1500
= 24/(750/2)
= 2.55 M
= 96 V/V
= 0.064V/V
or 63.5dB
This example emphasizes the fact that the ECP performance facts are proportionally defined by the
current source. This control fact is the basis for a specialized circuit called an analog multiplier for which
another ECP is given control over IEE and the output is then a product of the two inputs.
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A more generic form for the ECP is represented by figure 15.4-2, for which the input resistance is
accommodated by emitter debiasing and the CMRR is enhanced by a Wilson mirror.
Figure 15.4-2. ECP with Wilson mirror and 1 k emitter debiasing resistances.
As indicated by the presence of values this circuit offers an example of the pnp version for the ECP, for
which the pnp transistors are usually not quite as strong as their npn brothers. For example, the Early
voltage for the 2n3906 transistor is VA = 18.7V.
EXAMPLE 15.4–2: A subcircuit using 2n3906 transistors as part of a power amplifier follows the
Wilson-mirror ECP topology as shown by figure 15.1-1. Assume F = 100 and VA ≅19V
Determine the ECP circuit characteristics Rin, vL/vI and the CMRR for
(1) Rx = 136k (as shown)
(2) Rx = 272k
SOLUTION: (1) For the Wilson current source shown
IR = [15 -1.4V]/136k = 0.1mA.
*note that the junction offset = 2 × 0.7V = 1.4V for the Wilson mirror
So IEE is approximately = 0.1mA
and rO = VA/IEE ≅ 19/0.1 = 190 k.
And therefore for the Wilson mirror
REE ≅ 0.5F × rO = 50 × 190

Transconductance
gm = 40 × IEE/2 = 40 × 0.1/2 = 2.0mA/V
Consequently the input resistance will then be
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Rin = 2F × (1/gm + R4) = 2 × 100 × (0.5 + 1.0)
= 300 k
Voltage gain will be
vL 1
75 || 75
 
vI 2 1/ g m  1.0
And since
ACM 
= AVS = 0.5 × 37.5/(0.5 + 1)
75 || 75
2  9.5 1000
Then CMRR = 12.5/.002
= 12.5V/V
 .002 V/V
= 37.5/19000
= 6250 or 76 dB
(2) For Rx = 272 k IR is halved and so current IEE is halved.
Consequently REE is increased by a factor of 2
Transconductance gm is decreased by a factor of 2:
gm = 1.0mA/V
The input resistance will then be increased according to
Rin = 2F × (1/gm + R4) = 2 × 100 × (1.0 + 1.0)
= 400 k
The voltage gain AVS will be decreased
vL 1
75 || 75
 
v I 2 1 / g m  1.0
= AVS = 0.5 × 37.5/(1.0 + 1.0) = 9.37 V/V
The common-mode gain ACM will be decreased by a factor of 2
= 37.5/(2 × 19000)
≅.000987V/V
And then the CMRR will be = 9.375/.000987 = 9500
or 79.6dB
This example also indicates how strongly the ECP performance facts are defined by the current source,
although the proportionality is different from the previous example because of the emitter debiasing..
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15.5 ACTIVE LOAD EMITTER-COUPLED PAIRS
There is a natural match between the coupled pair and the current mirror, as indicated by figure 15.5-1.
And since both of these topologies have stiff outputs it is to be expected that the consequence will be a
high gain.
Figure 15.5-1. Active-load ECP topology as coupled pair plus current source.
The current increments indicated by the figure tell the story, for which
i1  gm 
vI
2
(15.5-1)
The current mirror reflects this current increment to the output side as shown.
At the output side transistor Q2 will generate a current increment in the opposite direction
i2  gm 
vI
2
(15.5-2)
These two current increments both flow into the output node so that
v  
v 

iO  i2 i4    gm  I    gm  I   gmvI
2 
2

(15.5-3)
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and will drive the conductances at the node. For the no-load condition these are the intrinsic
conductances associated with transistors Q2 and Q4 and are gO4 = I/VA4 and gO2 = I/VA2.
The signal output is
vO  iO  Rout


1

 gmvI  
 gO4  gO2 
(15.5-4)
corresponding to (no-load) transfer gain
vO
gm

vI gO4  gO2
(15.5-5)
And since the current through transistors Q2 and Q4 is the same, and since gm = I/VT where VT = thermal
voltage ~ .025V at T = 300K then the no-load transfer gain is
vO
1/ VT

vI 1/ VA4 1/ VA2
(15.5-6)
EXAMPLE 15.5-1: An active-load ECP subcircuit using the 2n3904 and 2n3906 transistors is driven by
an ideal current source of value IEE = 0.5mA. The Early voltages for the two transistors are
approximately 75V and 19V, respectively. Determine the gain with (1) no load and (2) with next stage
load RL = 100k.
SOLUTION: (1) The no-load gain is given by equation (15.5-6) for which
vO
1/ VT

vI 1/ VA4 1/ VA2

1/ .025
1/ 751/ 19
= 606 V/V
which is at a level that is beginning to approach that expected of an opamp. If we include a load then we
have to drop back to equation 15.5-4 and revise it accordingly
vL  iO  Rout || RL


1

 gmvI  
 gO4  gO2  GL 
(15.5-7)
for which the transfer gain then becomes
vL
gm

vI gO4  gO2  GL
(15.5-8)
With this new revised equation and an IEE/2 = 0.25mA we then have
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gm = 40 × 0.25mA/V
gO2 = 0.25mA/75 = .0033 mA/V
gO4 = 0.25mA/19.0 = .01316 mA/V
For which
vL
10.0

vI .01316 .00333 .01
(since
1/100k = .01mA/V)
= 377 V/V
If a single-stage high-gain ECP is desired the active load circuit may be modified for a Wilson mirror
current source or some other stiff current source as the load. The Wilson current mirror option is shown
by figure 15.5-2.
Figure 15.5-2. Active-load ECP topology with Wilson mirror active load.
For this topology the Q4 + Q5 contribution to the no-load output is gout4 instead of gO4 where
gout4 = 1/rout4 = 2/(Fro4) = 2go4/F = 2 × 0.25mA/100 × 19.0 = .000026mA/V
which is so small it might as well be classified as ‘negligible’. The result of the example above would
then be
vL
10.0
= 2975 V/V with no load

vI .000026 .00333
vL
10.0

vI .000026 .00333 .01
= 749 V/V with 100k load
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These numbers are of such magnitude that they approximate the gain of an opamp, which tells us that this
topology has a role whenever a subcircuit is needed for linearizing the system characteristics, which is
one of the principle roles of an opamp.
15.6 THE SOURCE-COUPLED PAIR (SCP) and MOS EQUIVALENT DIFFERENTIAL
AMPLIFIER CIRCUITS
A direct analog may be made between the BJT topologies and the FET family, with some exceptions for
the JFET devices because of the requirement that the gate-drain and gate-source junctions must be
reverse-biased. The basic SCP (source-coupled pair) is shown by figure 15.6-1.
Figure 15.6-1.
Source-coupled pair (SCP).
Figure 15.6-1 is analogous to that for the ECP (figure 15.2-1). And its analysis is similar in that
I SS  I D1  I D 2
(15.6-1)
Assuming that the transistors are operating in the active mode and that we may approximate the
relationship to the inputs by the level-1 model for which
I D1  K V GS 1  VTH
2
2
 K V GS 2  VTH 
(15.6-2a)
I D2
(15.6-2b)
Where transistors M1 and M2 are assumed to be matched so that the conduction coefficients are the same,
i.e. K1 = K2 = K , and the threshold voltages are assumed to be the same, i.e. VT1 = VT2 = VTH .
In this case it is best to invert these two equations in order to relate to the difference between the inputs,
i.e.
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VGS 1  VTH  I D1 K
(15.6-3a)
VGS 2  VTH  I D 2 K
(15.6-3b)
The difference between VGS1 and VGS2 = VI since the source node is in common. So the mathematics will
be of the form
V I  VGS 1  VGS 2 


I D1  I D 2
(15.6-4)
K
Equation (15.6-4) is a little more tractable in the form
KV I2 

I D1  I SS  I D1

2
 I SS  2 I D1 I SS  I D1
Which can be restated as

4 I D1 I SS  I D1   I SS  KV I2

2
(15.6-5)
Equation (15.6-5) is quadratic in ID1, which was probably evident already, but give the standard form

 
I D2 1  I SS I D1  I SS  KV I2 / 2
2
0
(15.6-6)
The solution to (15.6-6) is
I D1 
1
I SS 
2 

2
I SS
 I SS  KV I2

2
  I SS

2

1  1  1  KV 2 I
I
SS


2


(15.6-7)
For representative values K = 500A/V2 , VTH = 1.0V and ISS = 100A the behavior of equation (15.6-7) is
shown.
Figure 15.6-2. Transfer characteristics of source-coupled pair (SCP).
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Circuits, Devices, Networks, and Microelectronics
Note the resemblance to the plot of the transfer characteristics for the ECP (figure 15.2-2). The same
symmetry and linearity is evident. And at VI = 0, the current through the two transistors = IDSS/2 (= 50uA
for the figures and parameters thereto).
In like manner the transfer gain for a single-ended output and load resistance RL will be
vL
1 R || RL
 AVS   3
vI
2 1 g m  R4
(15.6-8)
which is redundant to equation (15.2-9). And for the common-mode gain
ACM 
R3 || RL
R || R
 3 L
'
2 RSS
1 g m  R4
(15.6-9)
which is redundant to equation (15.2-13). In this case we use RSS for the output resistance of the current
source to emphasize the usage of FETs. The common-mode rejection ratio (CMRR) is redundant to
equation (15.2-14) except for the FET notation
CMRR 
RSS
1 g m  R4
(15.6-10)
Unlike the BJT the input resistance Rin is not an issue and may always be counted as infinite.
In like manner to the topology discussed in section 14-5 the SCP can be formulated with an active load, in
which case the topology will be of the CMOS form shown by figure 15.6-3.
Figure 15.6-3. The CMOS source-coupled pair with active load.
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Circuits, Devices, Networks, and Microelectronics
Take note that the current source and load are topologically identical to that of the BJT, since for the
MOSFET a connected gate and drain assures that the MOSFET is in the active mode. And its transfer
gain is the same as equation (15.5-8), i.e.
vL
gm

vI gO4  gO2  GL
(15.6-11)
or analogous to equation (15.5-5) for no load.
Beyond this context the MOSFET active load differential pair does not lend itself to the same simplicities
afforded by the BJT. Given the fact that MOSFETs are anything but level-1 at the technology levels at
which they are now fabricated, few if any of the convenient simplicities are available. Therefore the
design/analysis process for the CMOS topology is essentially a sequence of simulations correlated with
an optimum sizing of the devices. Analog IC design using CMOS is not suitable for any sort of simple
overview other than to say that it requires much attention to technology files.
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Circuits, Devices, Networks, and Microelectronics
PORTFOLIO and SUMMARY
Emitter-coupled pair (ECP)
v L 1 R3 || RL
 
v I 2 1 g m  R4
= AVS
Rin  2 RiB  2 F 1 g m  R 4 
Rout  R3 || rout  R3
v LCM
R || RL
 3
v ICM
2 REE
CMRR 
AVS
ACM
= ACM

REE
1 g m  R4
Current Mirrors (selected)
for simple mirror
V  0.7
IR  S
RX
for Wilson mirror
V 1.4
IR  S
RX
(a) Simple current mirror
(b) Wilson current mirror
Active-load emitter coupled pairs
vO
gm

vI gO4  gO2

1/ VT
1/ VA4 1/ VA2
vL
gm

vI gO4  gO2  GL
= AVS
Rin  2 RiB  2  F 1 g m  R4 
Rout  rO 2 || rO4
CMRR 
AVS
ACM
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
= no load AVS
REE
1 g m  R4
with load
Circuits, Devices, Networks, and Microelectronics
vO gm

vI gO2

VA2
VT
vL
gm

vI gO2  GL
= no load AVS
= AVS
with load
Rin  2 RiB  2  F 1 g m  R4 
Rout  rO2
CMRR 
AVS
ACM

REE
1 g m  R4
Source-coupled pair
R || RL
vL 1
  3
v I 2 1 g m  R4
= AVS
v LCM R3 || RL

v ICM
2 RSS
= ACM
Rout  R3 || rout  R3
CMRR 
R SS
1 g m  R4
Active-load source- coupled pair
vL
gm

vI gO4  gO2  GL
Rout  rO 2 || rO4
CMRR 
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RSS
1 g m  R4
= AVS
with load
Circuits, Devices, Networks, and Microelectronics
Simulation analysis of ECP
ECP with both common mode (10kHz) and differential (2kHz) inputs
Transfer slope for the ECP. The magnitude at peak is the no-load (i.e. RL = infinity) transfer gain of the differential pair. Note
the symmetry of the transfer response.
Distortion analysis: CMRR = AVS ACM  305mV 5mV  1.67 mV 50mV 
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= 1826 = 65.2 dB
Circuits, Devices, Networks, and Microelectronics
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