SPACE VECTOR MODULATION FOR ASYMMETRICAL CASCADED
MULTILEVEL CONVERTERS
Fernanda de Morais Carnielutti, Humberto Pinheiro and Cassiano Rech
Universidade Federal de Santa Maria - UFSM
Grupo de Eletrônica de Potência e Controle - GEPOC
Santa Maria, RS, Brazil 97105-900
fcarnielutti@yahoo.com humberto@ctlab.ufsm.br rech.cassiano@gmail.com
Abstract - This paper describes a new Space Vector modulation (SVM) strategy for asymmetrical cascaded
multilevel converters. A seven-level asymmetrical multilevel cascaded converter is considered. The modulation is carried out in a new coordinate system and is divided into two steps. First, the nearest switching-state vector to the reference vector is chosen for the high-voltagelow-frequency cells, and the synthesized voltage vector is
subtracted from the reference, resulting in the reference
for the low-voltage-high-frequency cells. Afterwards, the
three-nearest low-voltage switching-state vectors are selected, and, for each sector of the SV diagram, a switching sequence is defined, aiming, for instance, to minimize
the number of commutations. Simulation results are given
to validate the proposed method, which is compared to
the phase-shift and phase disposition carrier-based approaches, showing its superior performance.
Keywords – Asymmetrical Cascaded Multilevel Converter, Space Vector Modulation
I. INTRODUCTION
Different multilevel converter topologies have been increasingly employed in medium-voltage applications [1], [2].
When compared to two-level converters, multilevel converters
achieve reduced levels of harmonic content, as well as reduced
voltage stress on the power semiconductor switches. The
cascaded multilevel converters, comprised of multiple seriesconnected single-phase H-bridges (power cells) are widely
used due to their modularity and reliability. The power cells
can have the same (symmetrical) or different (asymmetrical)
DC bus voltages Vdc [2]. The first ones are usually modulated
by means of a carrier-based modulation approach, such as
phase-shift (commonly employed in industry applications) [2],
and phase-disposition [3]. The last ones are often modulated
via a hybrid approach [4], [5], in which the high- and lowvoltage cells switch respectively with low and high frequency
(PWM).
These carrier-based modulation approaches are well established in literature [1, 2, 6]. In recent years, though, Space
Vector Modulation (SVM) strategies are being considered for
multilevel converters, including the symmetrical cascaded, for
which different SVM approaches have been reported [7–11].
However, for asymmetrical multilevel converters the reality
is rather different, as few works have been published addressing SVM strategies [12]. This can be attributed to the fact
978-1-4577-1646-1/11/$26.00 ©2011 IEEE
that these converters are comprised of power cells that operate from different DC bus voltage levels and switching frequencies which, added to the increased number of voltage
levels, contribute to the complexity of the modulation. As a
result, for the SVM to remain attractive for implementation
with asymmetrical multilevel cascaded converters, the algorithm must not significantly increase the computational burden
as the number of levels increases. On the other hand, an advantage of the SVM is that different switching sequences can be
implemented, resulting in reduced output line-to-line voltage
THD levels when compared to other modulation approaches.
This paper proposes a new fast and simple SVM strategy
for the modulation of asymmetrical cascaded multilevel converters. An example is given for a seven-level asymmetrical
cascaded multilevel converter, as shown in Figure 1, in which
the cells A1 , B1 and C1 have DC bus voltage values of 1pu
and A2 , B2 and C2 of 2pu [4]. To obtain only switching-state
vectors with integer entries, the modulation is carried out in
a new coordinate system and is divided into two steps. First,
the nearest switching-state vector to the reference is chosen
for the high-voltage-low-frequency cells. The voltage synthesized by these cells is then subtracted from the reference,
resulting in the reference for the low-voltage-high-frequency
cells. The three-nearest switching-state vectors are selected,
similarly to [7] and [8] and, for each sector of the SV diagram, a switching sequence is defined off-line, so as to minimize the number of commutations. In addition, the proposed
SVM strategy can be easily extended to converters with more
cells per phase.
This paper is organized as follows: Section II gives an
overview of some of the existing SVM approaches for cascaded multilevel converters. Section III described the proposed method. Section IV shows simulation results, and, finally, the conclusions are elaborated in Section V.
II. DESCRIPTION OF PREVIOUS SVM APPROACHES
The major problem of SVM for multilevel converters is the
higher number of switching-state vectors for converters with
more cells per phase (n-level converters). Consequently, the
implementation of SVM algorithms usually becomes more
complex as the number of levels increases. As a result, in
many papers [7–9, 11, 13] the converter switching-state vectors are represented in different coordinate systems, having
only integer entries. This reduces the computational burden
of SVM algorithm implementation, allowing it to be an attractive option for the modulation of n-level multilevel converters.
238
converter. The modulation is carried out in a modified α0 β 0 coordinate system, in which the converter switching state vectors
are also normalized. The SV diagram is divided in rectangular
sectors with two associated switching-state vectors, vu and vl ,
as shown in Figure 2. The reference voltage vector vref (α0 ,β 0 )
is truncated, resulting in two indexes that are used to address
a table containing vu and vl , as well as the coefficients c1 and
c2 of the equation that defines the line dividing the rectangular
section. The indexes na and nb are given by:
g
Cell
A1
3Φ Input
Transformer
B1
C1
Bypass
A2
B2
C2
a
b
na = sign(vα0 )(ceil(|vα0 |))
nb = sign(vβ 0 )(ceil(|vβ 0 |))
c
(11)
(12)
Motor
Fig. 1. Asymmetrical cascaded multilevel converter with one 1pu
and one 2pu cells per phase (seven-level).
A fast SVM approach that uses such a coordinate transformation was firstly presented in [7] for general multilevel converters. The reference voltages are expressed as the desired
output line-to-line voltages, vab , vbc and vca , and are represented in the <2 hexagonal coordinate system, in which the
angle between the basis vectors is 60◦ . The switching-state
vectors are normalized in relation to the DC bus voltage, resulting in only integer entries. The four-nearest switchingstate vectors can then be obtained trough truncations of the
reference voltage vector, vref (g,h) :
vul = [ceil(vref (g) )
vlu = [floor(vref (g) )
vll = [floor(vref (g) )
vuu = [ceil(vref (g) )
floor(vref (h) )]T
y1 = c1a` + c2
v ref
vl
Fig. 2. Zoom in the SV diagram of an 11-level symmetrical
cascaded multilevel converter [9].
T
(2)
T
(3)
T
(4)
Following the same premise of coordinate transformation,
[11, 13], proposed another SVM approach for symmetrical
cascaded multilevel converters. The switching-state vectors are represented in the hexagonal coordinate system of
[7]. The reference is also truncated to obtain the threenearest switching-state vectors and their corresponding duty
cycles. The converter switching-state vectors are divided in
two groups. The sum of the entries of the first group is even,
and of the second, odd. According to [11], it is possible to calculate mean vectors for the switching-state redundancies. The
odd vectors always have an implementable mean vector, but
this is not true for the even ones. As a result, it is proposed
the concept of large and small switching vectors. To minimize
the THD of the output line-to-line voltages, the three-nearest
switching-state vectors are chosen following an alternation between the small and large vectors, called Large-Small Alternation (LSA).
As could be seen, all the methods described above are designed for symmetrical cascaded multilevel converters. On the
other hand, there is just a few methods described in the literature for asymmetrical cascaded multilevel converters. In [12],
the design and control of asymmetrical multilevel cascaded
converters with non-integer or dynamically changing DC bus
voltages is addressed. The voltage reference vector is decomposed into the fractions synthesized by the high-voltage and
low-voltage cells. The resulting SV diagram is composed of
a main hexagon, relative to the high-voltage cells, and smaller
ones surrounding each high-voltage vector. The problem is
floor(vref (h) )]
ceil(vref (h) )]
The vectors vul and vlu are always two of the threenearest vectors. The third is chosen by analyzing the signal
of vref (g) − vref (h) − (vul(g) + vul(h) ). If it is positive, vuu
is selected; otherwise, vll . If the third vector is vuu , the duty
cycles can be computed as
(5)
(6)
(7)
and, if it is vll , as
dul = vref (g) − vll(g)
dlu = vref (h) − vll(h)
dll = 1 − dul − dlu
vh
(1)
ceil(vref (h) )]
dul = −(vref (h) − vuu(h) )
dlu = −(vref (g) − vuu(g) )
dll = 1 − dul − dlu
If vβ 0 > c1 vα0 +c2 , the nearest switching-state vector to the
reference is vh , otherwise is vl . As only one switching-state
vector is chosen in a switching period, the converter switches
at low-frequency, as long as the reference vector does not
change significantly within one switching period.
(8)
(9)
(10)
In [8] this algorithm was slightly modified, suppressing the
coordinate transformation. The line-to-line reference voltages
are normalized in relation to the DC bus voltage, assuming values equal to the ones obtained by the coordinate transformation. However, the core of the algorithm remains equal to [7].
Other SVM using a coordinate transformation was described in [9] for an 11-level symmetrical cascaded multilevel
239
then reduced to the modulation of the low-voltage cells within
each smaller hexagon. If the voltage ratio changes, the size of
the smaller hexagons change as well. As a result, the DC bus
voltage of the low-voltage cells is monitored, and the size of
the smaller hexagons is redefined. However, in [12] it is not
described how the switching-state vectors are chosen, nor how
the vector redundance issue is addressed.
0.8
é1/3 3 / 3 0 ù
ë
û
In addition, the converter phase voltages can be expressed
in αβo coordinates as:
√  
 
  
1
0
1/√2 vα
vag
vα
√
 vbg  = T−1 vβ  = −1/2
 vβ  .
αβo
√3/2 1/√2
vcg
vo
vo
−1/2 − 3/2 1/ 2
(14)
As a result, vab , vbc and vo are written in αβo as:
√
  
 
3/2 − √3/2
0
vα
vab
 vbc  =  0
 vβ 
(15)
3
0
√
vo
vo
0
0
3 2/2
or
q = 60°
0
[2/3 0 0]
T
0.8
0.4
0.25
é0 0
ë
0.5
vo
2 / 3ùû
va
T
Fig. 3. Converter output line-to-line voltage basis in αβø coordinate
system.
The vector [vab vbc vo ]T , which has been derived as
the representation of [vα vβ vo ]T with respect to the basis
{b1 ,b2 ,b3 }, can also be considered as a vector in the vector space (<3 ,<) with respect to the orthonormal basis. The
first representation can be viewed as two coordinate systems
within one linear vector space, and the second, as two linear
vector spaces both spanned by orthonormal basis. In this last
case, the matrix in (15) defines the linear transformation that
maps the αβo into the vab vbc vo linear space. The projection
of the switching-state vectors into the vab × vbc plane is shown
in Figure 4.
The switching-state vectors of the high-voltage-lowfrequency and low-voltage-high-frequency cells are represented respectively by the larger and smaller dots. Each highvoltage-low-frequency switching-state vector is surrounded
by an hexagon comprised of the switching-state vectors of
the low-voltage-high-frequency cells, acting like a threelevel converter centered in its respective high-voltage-lowfrequency switching-state vector. In Figure 4, it can be seen
that there is a superposition of adjacent subhexagons.
vbc
4
-4
 
  
2/3 √1/3
0
vα
vab
vβ  =  0
3/3 √ 0   vbc  .
vo
vo
0
0
2/3
T
0.4
III. PROPOSED SV MODULATION APPROACH FOR
ASYMMETRICAL CASCADED MULTILEVEL
CONVERTERS
This paper proposes a new SV modulation approach for
asymmetrical multilevel cascaded converters, considering
some achievements of the methods described in the previous
section. To exemplify the proposed method, let us consider
the converter of Figure 1. Usually, three-phase three-wire converters are modulated in αβ coordinates. If the switching-state
vector redundancies are to be addressed, the αβo coordinates
can be used, in which the degree of freedom o is included. It
will be demonstrated here that the representation of a given
vector in αβo coordinates
with respect
to the basis vectors
√
√
[2/3 0 0]T , [1/3 3/3 0]T and [0 0 2/3]T is a vector whose
first two entries are the converter output line-to-line voltages,
while the third one is proportional to the converter commonmode voltage vo . Considering that the converter line-to-line
voltages are comprised of equally spaced voltage levels, then
the normalized representation of the converter switching-state
vectors in these new coordinates assumes only integer values.
Let us begin by defining the relationship among the output
line-to-line voltages vab , vbc , the converter phase commonmode voltage vo and the converter phase voltages vag , vbg and
vcg as:
 
  
vag
vab
1 −1 0
 vbc  = 0 1 −1  vbg  .
(13)
vcg
1 1
1
vo
vb
0
4
vab
(16)
The columns √
of the matrix above are the
√ basis b1 = [2/3 0
0] , b2 = [1/3 3/3 0]T and b3 = [0 0 2/3]T of the new
coordinate system. It must be stressed here that b1 and b2 are
not orthogonal, but have an angle of 60◦ , as illustrated in Figure 3. This is in agreement with the the hexagonal coordinate
system presented in [7] and [8].
-4
T
Fig. 4. SV diagram for an asymmetrical 7-level cascaded converter
represented in the output line-to-line voltages coordinates.
240
A. Modulation of high-voltage-low-frequency cells
During each timer interruption, the reference voltage is normalized in relation to the phase voltage (3pu). As a result,
(1)-(4) can be used to define the four-nearest switching-state
vectors. Then, it is calculated the spatial distance (length) between each one of the four-nearest switching-state vectors and
the reference vector in the vab vbc plane. The redundancies
are not yet considered. The switching-state vector whose associated length has the lowest value is chosen as the nearest.
As the basis for this coordinate system are not orthogonal, the
length must be calculated as:
d = vref (vab ,vbc ) − v(vab ,vbc )
p
dist = dT Md
(17)
(18)
output voltage vector. Other criteria could be employed, such
as to ensure the power balance among the cells or to balance
the capacitor voltages of the DC links. The updated d vector is
now the difference between the previous voltage vector vhigh
synthesized by the converter and each one of the redundant
switching-state vectors. The new matrix M is now written as:




4 2 0
b1 · b1 b1 · b2 b1 · b3
1
M =  b2 · b1 b2 · b2 b2 · b3  =  2 4 0  . (24)
9
0 0 2
b3 · b1 b3 · b2 b3 · b3
To illustrate the modulation of the high-voltage-lowfrequency cells, Figure 5 shows the synthesized phase voltages
vag(high) , vbg(high) and vcg(high) , for a modulation index ma
of 0.9.
2
Voltage (pu)
In this paper, the modulation is divided in two steps, described in the next subsections. First, the nearest high-voltagelow-frequency switching-state vector to the reference is chosen. Then, the reference vector for the low-voltage-highfrequency cells is calculated as the subtraction of the synthesized high-voltage-low-frequency voltage and the reference
vectors. The low-voltage-high-frequency cells are then modulated using the fast SVM described in [7].
0
-2
2
0
vag ( high )
vbg ( high )
-2
2
0
vcg ( high )
0.035
-2
M=
b1 · b1
b2 · b1
b1 · b2
b2 · b2
=
1
9
4
2
2
4
(19)
where dist is the length and the elements of M are the dot
products of the basis vectors b1 and b2 .
In the SV diagram of Figure 4, some vectors have redundant states when transformed back to abc coordinates if the
common-mode voltage vo is not considered. The inclusion of
vo allows each abc vector to have an unique representation in
the output line-to-line voltages coordinate system. If the nearest switching-state vector [vab vbc ]T has one or more redundancies in abc coordinates, vo is used to select one particular
redundant vector. We have that:
vag = vab + vbg
vbg = vbc + vcg
vag + vbg + vcg = vo .
(20)
(21)
(22)
Substituting (20)-(21) in (22):
vab + 2vbc + 3vcg = vo .
(23)
The phase voltage vcg can assume the values -2, 0, 2,
and, as a result, the maximum number of redundancies that
a switching-state vector can have is equal to three. Substituting -2, 0, 2 in (23), three possible values of vo are chosen.
By applying (15) to the αβo switching-state vectors, it can be
seen that the redundant vectors have vo that differ by a ratio
of six. For example, the vectors [-2 -2 -2]T , [0 0 0]T and [2 2
2]T in abc have equivalents in vab vbc vo equal to [0 0 -6]T , [0
0 0]T and [0 0 6]T . If some of the switching-state vectors in
abc coordinates do not correspond to switching-state vectors
that the converter is able to synthesize, it is discarded.
The criterium for the selection is to guarantee the least number of commutations in relation to the previously synthesized
Time(ms)
Fig. 5. Voltages vag(high) , vbg(high) and vcg(high) sintetize by the
high-voltage-low-frequency cells, ma = 1
B. Modulation of low-voltage-high-frequency cells
As shown in Figure 4, each high-voltage switching-state
vector is surrounded by an adjacent subhexagon, analogous
to a three-level symmetrical converter centered in its respec∗
tive high-voltage switching-state vector. The reference vref
for the low-voltage-high-frequency cells is obtained by subtracting the vector vhigh comprised of the voltages vag(high) ,
vbg(high) and vcg(high) synthesized by the high-voltage-lowfrequency cells from the original reference voltage vref , as
∗
will lie inside one of
shown in Figure 6. As a result, vref
the subhexagons of Figure 4. But, irrespectively of the po∗
sition of vref , and consequently of vref
, the modulation of
the low-voltage-high-frequency cells can always be treated as
the modulation of a three-level converter with output phase
voltages that can assume the values 1, 0 or -1, as the DC bus
voltage of these cells is equal to 1pu.
Without losing the generality, let us consider the subhexagon centered in [0 0 0]T . It can be divided in 24 sectors,
as shown in Figure 7. Each sector is comprised of three lowvoltage switching-state vectors and their associated redundancies, organized off-line in a switching sequence that ensures
the least number of commutations inside the switching period Ts . The sectors, their respective switching sequences
and the equations that define the values of comparison with
the triangular carrier are stored in a table, similarly to [9] and
[10]. During each timer interruption, the coordinates vab and
∗
vbc of vref
are truncated to obtain the four nearest converter
switching-state vectors through (1)-(4), and shown in Figure 7.
241
IV. SIMULATION RESULTS
The proposed SVM was implemented for the asymmetrical
cascaded multilevel converter of Figure 1, with Vdc1 = 100V
and Vdc2 = 200V. Figures 10 and 9 show the simulated
phase and output line-to-line voltages for a modulation index
ma = 1. The carrier frequency for the low-voltage highfrequency cells is fc = 3kHz.
v ref
v*ref
v high
300
After, the three nearest switching-state vectors are chosen and
their duty cycles are calculated by (5)-(10), as in [7] and [8].
-300
300
Voltage (V)
Fig. 6. Zoom of the SV diagram showing the reference, the
synthesized by the high-voltage-low-frequency cells and the
reference for the low-voltage-high-frequency cells voltage vectors.
vag
0
vbg
0
-300
300
vcg
0
vbc
-300
2
2
3
9
7
8
6
-2
vuu
vul5
* 11
v ref
10
vlu12
0
vll
13
15
14
Fig. 9. Phase voltages vag , vbg and vcg , ma = 1 and fc = 3kHz
2
19
17
18
16
22
20
24
-600
600
-2
Fig. 7. Subhexagon of the low-voltage-high-frequency cells, the
∗
and the four nearest switching-state vectors.
reference vref
The vab and vbc coordinates of vector vuu , through (11)(12), are used to address the position on the table relative to
∗
the square in which vref
is located. The lower and the upper
sectors are selected if the third nearest vector is vll or vuu , respectively. The duty cycles calculated are then used to update
the equations of the comparators for that specific sector, resulting in the voltages vag(low) , vbg(low) and vcg(low) illustrated in
Figure 8.
Voltage (pu)
vag (low)
1
0
-1
1
0
vbg (low)
-1
1
0
vcg (low)
-1
Time(ms)
vab
0
23
21
600
vab
0.035
Fig. 8. Voltages vag(low) , vbg(low) and vcg(low) synthesized by the
low-voltage-high-frequency cells, ma = 1 and fc = 3kHz
Voltage (V)
1
0.035
Time(ms)
4
0
vbc
-600
600
vca
0
-600
0.035
Time(ms)
Fig. 10. Output line-to-line voltages vab , vbc and vca , ma = 1 and
fc = 3kHz
The proposed SVM was compared to the hybrid modulation approach of [4], in which the low-voltage-high-frequency
cells are modulated with phase-shift (PS) and phase disposition (PD) carrier-based approaches. Figures 11 and 12 show,
respectively, the total harmonic distortion (THD) and the distortion factor (DF1) [14] for the output line-to-line voltages. It
can be seen that the proposed method has a good performance
concerning the THD and DF1 indexes. Comparing the SV
approach to the PD, it can be noticed that the two have very
similar values of THD, in accordance to [3]. For the majority of ma values, the SV modulation also gives the best DF1s,
meaning that the low-order harmonics are smaller in amplitude than in the carrier-based approaches. The results for the
SVM can be optimized even further, by the correct choice of
different switching sequences, specially regarding the higher
ma values.
242
50
45
40
THD PS
THD(%)
35
30
THDSV
25
20
15
THD PD
10
5
0
0.2
0.3
0.4
0.5
0.6
ma
0.7
0.8
0.9
1
Fig. 11. THD for the space vector (SV), phase-shift (PS) and phase
disposition (PD) modulation approaches.
0.5
DF1PS
0.4
DF 1(%)
DF1PD
0.3
0.2
DF1SV
0.1
0.2
0.3
0.4
0.5
0.6
ma
0.7
0.8
0.9
1
Fig. 12. DF1 for the space vector (SV), phase-shift (PS) and phase
disposition (PD) modulation approaches.
V. CONCLUSION
This paper proposed a new SVM method for asymmetrical cascaded multilevel converters, considering some achievements of SVM approaches previously described in literature.
The simulation results demonstrated its good performance,
specially regarding the THD and DF1 indexes. This is a fast
algorithm, as the truncation of the reference voltage vector
and the off-line definition of the switching sequences for the
high-voltage-low-frequency cells reduces the computational
burden. In addition, the algorithm can be easily extended to
converters with more low-voltage-high-frequency cells without substantially increasing its complexity. However, the adequate switching sequences must be determined off-line and
loaded into the DSP memory, and the definition of these sequences may increase the complexity of the space vector approach, when compared to carrier-based ones.
VI. ACKNOWLEDGEMENTS
The authors would like to thanks the Federal University of
Santa Maria - UFSM, CAPES and CNPq.
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