FAN5109
Dual Bootstrapped 12V MOSFET Driver
Features
Description
ƒ Drives N-Channel High-Side and Low-Side MOSFETs
The FAN5109 is a dual high-frequency MOSFET driver,
specifically designed to drive N-Channel power
MOSFETs in a synchronous-rectified buck converter.
These drivers, combined with a Fairchild multi-phase
pulse-width-modulated (PWM) controller and power
MOSFETs, form a complete core voltage regulator
solution for advanced microprocessors.
in a Synchronous Buck Configuration
ƒ Enhanced Upgrade to FAN5009
ƒ Direct Interface to FAN5019, FAN5182, and Other
Compatible PWM Controllers
ƒ 12V High-Side and 12V Low-Side Drive
ƒ Internal Adaptive Shoot-Through Protection
ƒ Fast Rise and Fall Times
ƒ Switching Frequency Above 500kHz
ƒ OD input for Output Disable – Allows Synchronization
The FAN5109 drives the upper and lower MOSFET
gates of a synchronous buck regulator to 12VGS. The
upper gate drive includes an integrated boot diode and
requires only an external bootstrap capacitor (CBOOT).
The output drivers have the capacity to efficiently switch
power MOSFETs at frequencies up to 500KHz. The
circuit's adaptive shoot-through protection prevents both
MOSFETs from conducting simultaneously.
with PWM Controller
ƒ SOIC-8 Package
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
March 2008
The FAN5109 is rated for operation from 0°C to +85°C
and is available in a low-cost SOIC-8 package.
Applications
ƒ Multi-Phase VRM/VRD Regulators for
Microprocessor Power
ƒ High-Current, High-Frequency DC/DC Converters
ƒ High-Power Modular Supplies
Related Application Notes
ƒ Application Note AN-6003 — "Shoot-through" in
Synchronous Buck Converters
ƒ Application Note AN-6065 — FAN5109 VCC Bypass
Considerations to Reduce Voltage Spikes
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing Method
Quantity Per Reel
FAN5109MX
0°C to 85°C
SOIC-8
Tape and Reel
2500
All packages are lead free per JEDEC: J-STD-020B standard.
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
12V
4
VCC
D1
1
Q1
PWM
OD
2
3
8
Overlap
Protection
Circuit
7
CVC C
BOOT
CBOOT
HDRV
L1
SW
Q2
V CC
5
6
VOU T
COUT
LDRV
PGND
Figure 1. Typical FAN5109 Application
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Application Diagram
Block Diagram
V CC
VCC
OD
BOOT
PWM
HDRV
tFall
Delay
t Fall
VCC/3
Delay
1.2V
SW
1.2V
VCC
LDRV
GND
Figure 2. Functional Block Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
2 of 14
BOOT
PWM
OD
VCC
1
2
3
4
FAN
5009
8
7
HDRV
6
5
PGND
SW
LDRV
Figure 3. Pin Assignments
Pin Definitions
Pin #
Name
Description
1
BOOT
Bootstrap Supply Input. Provides voltage supply to the high-side MOSFET driver. Connect to
the bootstrap capacitor (see the Applications section).
2
PWM
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
3
OD
4
VCC
Power Input. +12V chip bias power. Bypass with a 1μF ceramic capacitor.
5
LDRV
Low-Side Gate Drive Output. Connect to the gate of low-side power MOSFET(s).
6
PGND
Power ground. Connect directly to the source of the low-side MOSFET(s).
7
SW
8
HDRV
Output Disable. When LOW, this pin disables FET switching (HDRV and LDRV are held LOW).
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Pin Configuration
Switch Node Input. Connect as shown in Figure 1. SW provides return for the high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.
High-Side Gate Drive Output. Connect to the gate of high-side power MOSFET(s).
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
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Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. Absolute maximum ratings apply individually, not in
combination. Unless otherwise specified, voltages are referenced to PGND.
Min.
Max.
VCC to GND
Continuous
Parameter
-0.3
15.0
VCC to GND
Transient (t=4ns, f=500kHz)
-0.3
19.0
-0.3
5.5
-1
15
PWM and OD to GND
Continuous
SW to GND
BOOT to SW
BOOT to GND
V
25
-5
Continuous
-0.3
15.0
Transient (t<20ns, f=500kHz)
-2.0
17.0
Continuous
-0.3
30.0
Transient (t=100ns, f=500kHz)
Continuous
V
V
Transient (t=100ns, f=500kHz)
HDRV to GND
LDRV to GND
(1)
Unit
V
V
38
VSW -1
VBOOT+0.3
-0.5
VCC
Transient (t=200ns)
-2.0
(1)
Transient (t<20ns, f=500kHz)
-2.0
(1)
VCC+0.3
VCC+2.0
V
V
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Absolute Maximum Ratings
Note:
1. For transient derating beyond the levels indicated, refer to Figure 17 and Figure 18.
Thermal Information
Symbol
Parameter
Min.
Typ.
Max.
Unit
TJ
Junction Temperature
0
+150
°C
TSTG
Storage Temperature
-65
+150
°C
TL
Lead Soldering Temperature, 10 seconds
+300
°C
TVP
Vapor Phase, 60 seconds
+215
°C
TLI
Infrared, 15 seconds
+220
°C
PD
Power Dissipation, TA=25°C
715
mW
θJC
Thermal Resistance, Junction-to-Case
40
°C/W
θJA
Thermal Resistance, Junction-to-Ambient
140
°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Typ.
Max.
Unit
10.0
12.0
13.5
V
VCC
Supply Voltage
TA
Ambient Temperature
0
+85
°C
TJ
Junction Temperature
0
+125
°C
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
VCC to GND
Min.
www.fairchildsemi.com
4 of 14
VCC and VLDRV=12V, and TA=25°C using the circuit in Figure 4 unless otherwise noted, each side. The “•” denotes
specifications that apply over the full operating temperature range.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
6.4
12.0
13.5
V
2.5
4.0
mA
Input Supply
VCC
VCC Voltage Range
ICC
VCC Current
•
OD =0V
•
OD Input
VIH (OD)
VIL (OD)
VHYS(OD)
IOD
tpdl(OD)
tpdh(OD)
Input High Voltage
•
Input Low Voltage
•
Input Hysteresis
•
Input Current
OD =3.0V
(3)
Propagation Delay
•
2.0
V
0.8
550
+300
nA
25
40
ns
15
30
ns
–300
See Figure 5
V
mV
PWM Input
VIH(PWM)
Input High Voltage
•
VIL(PWM)
Input Low Voltage
•
IIL(PWM)
Input Current
•
3.5
V
-1
0.8
V
+1
µA
3.3
Ω
High-Side Driver
RHUP
ISOURCE(LDRV)
Output Resistance, Sourcing
Source Current
(3)
RHDN
Output Resistance, Sinking
ISINK(HDRV)
(3)
tR(HDRV)
t(HDRV)
tpdh(HDRV)
tdl(HDRV)
Sink Current
Transition Times
(3,5)
(3,4)
Propagation Delay
VBOOT – VSW =12V
2.5
VDS=-10V
2.0
VBOOT – VSW =12V
1.1
VDS=10V
3.0
See Figure 4
See Figure 6
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Electrical Characteristics
A
1.5
Ω
25
15
40
25
ns
ns
40
55
ns
25
40
ns
2.0
2.6
Ω
A
Low-Side Driver
RLUP
ISOURCE(LDRV)
RLDN
ISINK(LDRV)
tR(LDRV)
tF(LDRV)
Output Resistance, Sourcing
Source Current
(3)
VDS=-10V
Output Resistance, Sinking
Sink Current
(3)
Transition Times
(3,5)
tpdh(LDRV)
tpdl(LDRV)
0.9
VDS=10V
See Figure 4
See Figure 6
(3,4)
Propagation Delay
tpdh(LDF)
See Adaptive Gate Drive
Circuit Description
A
2.7
1.2
3.5
Ω
A
20
30
ns
15
25
ns
20
30
ns
15
25
ns
160
ns
Notes:
2. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.
3. Specifications guaranteed by design and characterization (not production tested).
4. For propagation delays, tpdh refers to low-to-high signal transition. tpdl refers to high-to-low signal transition.
5. Transition times are defined for 10% and 90% of DC values.
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
5 of 14
12V
1
BOOT
HDRV
8
2
PWM
SW
7
3
OD
PGND
6
4
VCC
LDRV
5
3000pF
3000pF
1µF
Figure 4. Test Circuit
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Test Diagrams
Figure 5. Output Disable Timing
Figure 6. Adaptive Gate Drive Timing
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
6 of 14
Figure 7. Gate Drive Rise and Fall Times (1)
Figure 8. Gate Drive Rise and Fall Times (2)
Figure 9. HDRV Rise and Fall Times vs. CLOAD
Figure 10. LDRV Rise and Fall Times vs. CLOAD
Figure 11. HDRV Normalized Impedance
vs. Temperature
Figure 12. LDRV Normalized Impedance
vs. Temperature
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics
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7 of 14
Figure 13.
Figure 15.
Figure 17.
HDRV Pull-Up (Sourcing)
Figure 14.
HDRV Pull-Down (Sinking)
Figure 16.
Negative SW Voltage Transient
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
Figure 18.
LDRV Pull-Up (Sourcing)
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics (Continued)
LDRV Pull-Down (Sinking)
Negative LDRV Voltage Transient
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8 of 14
ICC{mA}=2 x VCC x (0.26 + 3.38 x fSW ), where fSW is in MHz.
Figure 19.
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
Operating Current vs. Frequency
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
9 of 14
The FAN5109 is optimized for driving N-channel
MOSFETs in a synchronous buck converter topology. A
single PWM input signal is all that is required to
properly drive the high-side and low-side MOSFETs.
For an illustration of the FAN5109 and its features, refer
to the Typical Application diagram in Figure 1 and
Functional Block diagram in Figure 2.
Low-Side Driver
The low-side driver (LDRV) is designed to drive groundreferenced, low-RDS(on), N-channel MOSFETs. The bias
for LDRV is internally connected between VCC and
PGND. When the driver is enabled, the driver’s output
is 180° out of phase with the PWM input. When the
FAN5109 is disabled ( OD =0V), LDRV is held LOW.
High-Side Driver
The high-side driver (HDRV) is designed to drive a
floating N-channel MOSFET. The bias voltage for the
high-side driver is developed by a bootstrap supply
circuit, consisting of an external diode and bootstrap
capacitor (CBOOT).
During start-up, SW is held at PGND, allowing CBOOT to
charge to VCC through the diode. When the PWM input
goes HIGH, HDRV begins to charge the high-side
MOSFET gate (Q1). During this transition, charge is
transferred from CBOOT to Q1’s gate. As Q1 turns on,
SW rises to VIN, forcing the BOOT pin to VIN + VC(BOOT),
which provides sufficient VGS enhancement for Q1. To
complete the switching cycle, Q1 is turned off by pulling
HDRV to SW. CBOOT is recharged to VCC when SW falls
to PGND.
Adaptive Gate Drive Circuit
The FAN5109 advanced design ensures minimum
MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Refer to
the gate drive rise and fall time waveforms in Figure 7
and Figure 8 for the relevant timing information.
To prevent overlap during the low-to-high switching
transition (Q2 OFF to Q1 ON), the adaptive circuitry
monitors the voltage at the LDRV pin. When the PWM
signal goes HIGH, Q2 begins to turn OFF after a
propagation delay, as defined by tpdl(LDRV) parameter.
Once the LDRV pin is discharged below ~1.3V, Q1
begins to turn ON after adaptive delay tpdh(HDRV).
To preclude overlap during the high-to-low transition
(Q1 OFF to Q2 ON), the adaptive circuitry monitors the
voltage at the SW pin. When the PWM signal goes
LOW, Q1 begins to turn OFF after a propagation delay
(tpdl(HDRV)). Once the SW pin falls below ~VCC/3, Q2
begins to turn ON after adaptive delay tpdh(LDRV).
Additionally, VGS of Q1 is monitored. When VGS(Q1) is
discharged below ~1.3V, a secondary adaptive delay is
initiated, which results in Q2 being driven ON after
tpdh(LDF), regardless of the SW state. This function is
implemented to ensure CBOOT is recharged after each
switching cycle, particularly for cases where the power
converter is sinking current and the SW voltage does
not fall below the VCC/3 adaptive threshold. The
secondary delay tpdh(LDF) is longer than tpdh(LDRV).
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Circuit Description
HDRV output is in phase with the PWM input. When the
driver is disabled, the high-side gate is held low.
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
10 of 14
PH(R) and PH(F) are internal dissipations for the rising and
falling edges, respectively:
Supply Capacitor Selection
For the supply input (VCC), a local ceramic bypass
capacitor is recommended to reduce the noise and to
supply the peak current. Use at least a 1μF, X7R or
X5R capacitor. Keep this capacitor close to the VCC
and PGND pins.
PH(R) = PQ1 ×
RHUP
RHUP + RE + R G
(6)
PH(F ) = PQ1 ×
RHDN
RHDN + RE + RG
(7)
1 ×Q
G1 × VGS(Q1) × f SW
2
(8)
PQ1 =
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT) and an external diode, as shown in Figure 1.
These components should be selected after the highside MOSFET has been chosen. The required
capacitance is determined using the following equation:
CBOOT =
QG
ΔVBOOT
As described in Equations 6 and 7, the total power
consumed driving the gate is divided in proportion to the
resistances in series with the MOSFET's internal gate
node, as shown below:
BOOT
Q1
(1)
RHUP
where QG is the total gate charge of the high-side
MOSFET and ΔVBOOT is the voltage droop allowed on
the high-side MOSFET drive. For example, the QG of
the FDD6696 MOSFET is about 35nC at 12VGS. For an
allowed droop of ~300mV, the required bootstrap
capacitance is 100nF. A good quality ceramic capacitor
must be used. The average diode forward current,
IF(AVG), can be estimated by:
IF( AVG ) = Q GATE × fSW
(2)
where FSW is the switching frequency of the controller.
The peak surge current rating of the diode should be
checked in-circuit, since this is dependent on the
equivalent impedance of the entire bootstrap circuit,
including the PCB traces.
G
RG
RHDN
S
SW
Figure 20. Driver Dissipation Model
RG is the gate resistance internal to the FET. RE is the
external gate drive resistor implemented in many
designs. Note that the introduction of RE can reduce
driver power dissipation, but excess RE may cause
errors in the adaptive gate drive circuitry. For more
information, please refer to Application Note AN-6003,
"Shoot-through" in Synchronous Buck Converters.
PLDRV = PL(R) + PL(F)
Total device dissipation:
(9)
(3)
where PH(R) and PH(F) are internal dissipations for the
rising and falling edges, respectively:
(4)
PL(R) = PQ2 ×
RLUP
RLUP + RE + RG
(10)
PL(F) = PQ2 ×
RLDN
RHDN + RE + RG
(11)
PQ represents quiescent power dissipation:
PQ = VCC × [4mA + 0.036 ( fSW − 100)]
RE
PLDRV is dissipation of the lower FET driver:
Thermal Considerations
PD = PQ + PHDRV + PLDRV
HDRV
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Application Information
fSW is switching frequency (in kHz).
QG1 is total gate charge of the upper FET (Q1) for its
applied VGS.
PQ2 =
1 ×Q
G2
2
× VGS(Q2) × fSW
(12)
PHDRV represents internal power dissipation of the upper
FET driver.
PHDRV = PH(R) + PH(F)
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
(5)
www.fairchildsemi.com
11 of 14
Use the following general guidelines when designing
printed circuit boards (see Figure 21):
ƒ Trace out the high-current paths and use short, wide
(>25 mil) traces to make these connections.
ƒ Connect the PGND pin as close as possible to the
source of the lower MOSFET.
ƒ The VCC bypass capacitor should be located as close
as possible to the driver’s VCC and PGND pins and
connected to the top layer.
ƒ Use vias to other layers where possible to maximize
thermal conduction away from the IC.
Figure 21. Recommended Layout for SOIC-8
(Not to Scale)
Note!
The further the VCC bypass capacitor is located away
from the driver, the less effective it is in limiting VCC
spikes. Locate the capacitor as close as possible to the
driver and connect it as shown in Figure 21.
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Layout Considerations
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12 of 14
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
Physical Dimensions
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 22. 8-Lead SOIC Package, 0.150mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
13 of 14
FAN5109 — Dual Bootstrapped 12V MOSFET Driver
© 2005 Fairchild Semiconductor Corporation
FAN5109 • Rev. 1.2.0
www.fairchildsemi.com
14 of 14