1999 Power Electronics Specialists Conference
Advances in Averaged Switch
Modeling and Simulation
Dragan Maksimovic* and Robert Erickson
Colorado Power Electronics Center
CoPEC
http://ece-www.colorado.edu/~pwrelect
* Acknowledgment: the work by Dragan Maksimovic was supported in part by the National Science Foundation
CAREER Award, Grant No. ECS-9703449.
1. Introduction: converter modeling approaches and objectives
2. Averaged switch modeling of PWM converters operating in the
continuous conduction mode (CCM)
• Basics of averaged switch modeling
• Switch network steady-state and small-signal models
• Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in CCM
• PSpice implementation of the averaged switch model
• Application examples: small-signal dynamics,
conduction losses and efficiency of a Sepic converter
• Averaged switch modeling exercise: include switching losses
3. Averaged switch modeling of PWM converters operating in
discontinuous conduction mode (DCM)
• Averaged switch model in DCM
• Switch network steady-state and small-signal models in DCM
• Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in DCM
• Combined CCM/DCM averaged switch model
• PSpice implementation of combined CCM/DCM models
• Application examples:
Large-signal transient response of a SEPIC
Flyback converter small-signal frequency responses in CCM
and DCM
4. Averaged modeling of PWM converters with current-programmed
mode (CPM) control
• Averaged switch model in CCM and DCM
• Steady-state and AC models in CCM and DCM
• Large-signal averaged CCM/DCM model for CPM controller
• PSpice implementation of the CPM controller model
• Application example: buck converter with CPM controller
5. Single-phase low-harmonic rectifiers
•
The ideal rectifier
•
Averaged models of rectifiers
•
Application examples:
DCM boost rectifier
SEPIC rectifier with nonlinear-carrier control
6. Summary
7. Bibliography
•
•
•
•
•
http://ece-www.colorado.edu/~pwrelect/publications
seminar slides, collection of simulation examples, library of PSpice
models used in the examples, and many other CoPEC publications
and presentation materials
http://ece-www.colorado.edu/~pwrelect/ is the CoPEC home page
http://ece-www.colorado.edu/~pwrelect/book/bookdir.html
is the home page for the Textbook: R.W.Erickson, Fundamentals of
Power Electronics
Power Electronics courses at the University of Colorado:
• Power Electronics 1: http://ece-www.colorado.edu/~ecen5797
• Power Electronics 2: http:// ece-www.colorado.edu/~ecen5807
• Power Electronics Lab: http:// ece-www.colorado.edu/~ecen4517
All simulation examples completed using free PSpice evaluation
version available from: http://www.orcad.com
Engineering design based on converter modeling:
• Predict converter system behavior, validate models by experiments
• Use the model to predict performance under worst-case conditions
• Improve design until worst-case behavior meets specifications
(or until reliability and production yield are acceptably high)
Models:
• Circuit models that yield design-oriented, analytical results
• Models for computer simulation
Results of interest:
• Steady-state characteristics
• Component stresses, losses, efficiency
• Large and small-signal dynamic responses
•
•
•
•
•
Describe basic averaged switch modeling approach
Develop averaged models for
Converters in continuous conduction mode (CCM)
Converters in discontinuous conduction mode (DCM)
Converters with Current-Programmed Mode (CPM) controller
Single-phase power-factor correctors
Summarize analytical results for steady-state and dynamic responses
Demonstrate PSpice implementations of averaged-switch models and
controllers
Present application examples
Large-signal transient responses and small-signal dynamics of DC-DC
converters and single-phase power-factor correctors
!
•
•
•
•
•
•
•
Switch network is replaced by averaged circuit model. Switching
harmonics are removed, and low-frequency components of waveforms
are modeled in a simple way.
A very general approach to modeling converter losses, efficiency, and
dynamics.
Yields an intuitive understanding of converter behavior in CCM, DCM,
current-programmed mode, etc.
Applicable to all types of converters: dc-dc converters, as well as dc-ac
inverters, ac-dc low-harmonic rectifiers, ac-ac matrix converters.
Well-suited to simulation
Well developed and understood technique, easily taught to students.
Main reference for the material in this seminar:
R.W.Erickson, Fundamentals of Power Electronics, Chapman and
Hall, 1997.
Bibliography has a large collection of other selected references
Averaged switch modeling
averaging
Switching
network
d
+
–
Switching converter circuit
+
–
Large-signal averaged circuit model
simulation
model
1
-
S
2
4
ccm-dcm1
5
duty
D
+
Averaged
switch
model
3
linearization
A
K
+
–
D+d^
+
–
+
–
Model implementation for simulation
DC and small-signal averaged circuit model
Gc ( s ) = Gco
DC, AC and Transient simulation
1 − s / ws
1 + (1 / Q) s / wo + ( s / wo ) 2
Analytical results:
steady-state characteristics
and small-signal dynamics
•
•
•
•
•
•
Basics of averaged switch modeling
Switch network steady-state and small-signal models
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in CCM
PSpice implementation of averaged switch models
- ideal switches (ccm1)
- switches with conduction losses (ccm2)
- switches in converters with isolation transformer (ccm3)
- switch with conduction losses in converters with (possibly)
isolation transformer (ccm4)
Application example:
- SEPIC small-signal frequency response, conduction losses and
efficiency
Averaged switch modeling exercise: include switching losses
Averaged switch modeling
Basic approach
Given a PWM converter operating in continuous conduction mode:
L1
C1
D1
+
Vg
+
–
L2
C2
R
v
SEPIC
example
Q1
–
Separate the switching elements from the remainder of the converter...
Definition of switch network,
SEPIC example
• Define a switch
network,
containing all of
the converter
switching
elements.
• The remainder of
the converter is
linear and timeinvariant.
• The terminal
voltages and
currents of the
switch network
can be arbitrarily
defined.
L1
C1
+
iL1(t)
vg(t)
+ vC1(t) –
+
–
C2 vC2(t)
L2
iL2(t)
i1(t)
–
i2(t)
Switch network
–
+
v2(t)
v1(t)
–
Q1
D1
Duty d(t)
cycle
+
R
Switching converter system
with switch network explicitly defined
Power input
Load
Time-invariant network
containing converter reactive elements
+
–
C
+
vC(t)
L
+
i2(t)
Switch network
–
+
v2(t)
–
Control
input
d(t)
v(t)
–
port 2
v1(t)
R
iL(t)
–
i1(t)
port 1
vg(t)
+
Discussion
l
l
The number of ports in the switch network is less than or equal
to the number of SPST switches in the converter
Simple dc-dc case, in which converter contains two SPST
switches: switch network contains two ports
The switch network terminal waveforms are then the port voltages and
currents: v1(t), i1(t), v2(t), and i2(t).
Two of these waveforms can be taken as independent inputs to the
switch network; the remaining two waveforms are then viewed as
dependent outputs of the switch network.
Switch network also includes control input d(t)
l
Definition of the switch network terminal quantities is not unique.
Different definitions lead equivalent results having different
forms
Several ways to define the PWM switch network,
and the corresponding CCM models
i2(t)
⟨ i1(t) ⟩T
+
+
+
v1(t)
v2(t)
⟨ v1(t) ⟩T
⟨ v2(t) ⟩Ts
–
–
–
–
i2(t)
⟨ i1(t) ⟩T
s
+
+
+
v1(t)
v2(t)
⟨ v1(t) ⟩T
⟨ v2(t) ⟩Ts
–
–
–
–
i2(t)
⟨ i1(t) ⟩T
s
+
i1(t)
i1(t)
i1(t)
s
1:D
⟨ i2(t) ⟩T
s
+
s
D' : 1
⟨ i2(t) ⟩Ts
+
s
D' : D
⟨ i2(t) ⟩T
s
+
+
v1(t)
v2(t)
⟨ v1(t) ⟩T
s
⟨ v2(t) ⟩Ts
–
–
–
–
+
A few points
regarding averaged switch modeling
• The switch network can be defined arbitrarily, as long as
its terminal voltages and currents are independent, and
the switch network contains no reactive elements.
• It is not necessary that some of the switch network terminal quantities
coincide with inductor currents or capacitor voltages of the converter, or
be nonpulsating.
• The object is simply to write the averaged equations of the switch network;
i.e., to express the average values of half of the switch network terminal
waveforms as functions of
the average values of the remaining switch network terminal waveforms,
and
the control input.
Terminal waveforms of the switch network
v1(t)
vC1 + vC2
v1(t)
L1
Ts
C1
iL1(t)
0
0
dTs
0
i1(t)
Ts
L2
i1(t)
Ts
t
T2
v2(t)
Ts
t
Ts
t
iL1 + iL2
i 2(t)
Ts
0
0
dTs
Q1
D1
Duty d(t)
cycle
0
dTs
i2(t)
–
+
–
i2(t)
–
Switch network
v1(t)
vC1 + vC2
0
C2 vC2(t)
T2
dTs
0
v2(t)
0
+
–
iL2(t)
0
v2(t)
0
vg(t)
iL1 + iL2
i 1(t)
0
t
+
+ vC1(t) –
+
R
The averaging step
x(t) T = 1
s
Ts
t + Ts
x(t)dt
t
Now average all waveforms over one switching period:
Power input
Load
Averaged time-invariant network
containing converter reactive elements
s
+
–
C
+
⟨vC(t)⟩Ts
L
+
Averaged
switch network
–
+
⟨v2(t)⟩T
s
–
Control
input
d(t)
⟨v(t)⟩T
s
–
⟨i2(t)⟩Ts
port 2
⟨v1(t)⟩Ts
R
⟨iL(t)⟩Ts
–
⟨i1(t)⟩Ts
port 1
⟨vg(t)⟩T
+
The averaging step
The basic assumption is made that the natural time constants of the
converter are much longer than the switching period, so that the
converter contains low-pass filtering of the switching harmonics:
One may average the waveforms over an interval that is short
compared to the system natural time constants, without
significantly altering the system response.
In particular, averaging over the switching period Ts removes the
switching harmonics, while preserving the low-frequency
components of the waveforms.
This step removes the small but mathematically-complicated
switching harmonics, leading to a relatively simple and tractable
converter model.
In practice, the only work needed for this step is to average the switch
dependent waveforms.
Averaged terminal equations
of the switch network
(small switching ripple is neglected)
v1(t)
v1(t)
0
v2(t)
0
0
dTs
i1(t)
Ts
= d'(t)
Ts
vC1(t)
Ts
t
+ vC2(t)
= d(t)
Ts
i 2(t)
0
dTs
Ts
dTs
= d(t)
Ts
i L1(t)
Ts
+ i L2(t)
t
Ts
Ts
vC1(t)
Ts
+ vC2(t)
t
Ts
iL1 + iL2
T2
0
i 1(t)
0
i2(t)
i 1(t)
T2
0
v2(t)
Ts
iL1 + iL2
0
vC1 + vC2
Ts
0
v1(t)
0
v2(t)
vC1 + vC2
Ts
0
dTs
0
i 2(t)
Ts
= d'(t)
Ts
i L1(t)
Ts
+ i L2(t)
t
Ts
Derivation of switch network equations
(Algebra steps)
We can write
i L1(t)
vC1(t)
+ i L2(t)
Ts
Ts
+ vC2(t)
Result
Ts
=
Ts
=
i 1(t)
Ts
d(t)
v2(t)
d(t)
+
Ts
⟨v1(t)⟩T
s
–
Hence
v1(t)
i 2(t)
⟨i1(t)⟩Ts
d'(t)
v (t)
d(t) 2
–
Ts
+
–
d'(t)
i (t)
d(t) 1
Ts
⟨i2(t)⟩Ts
Averaged switch network
Ts
Ts
=
=
d'(t)
v (t)
d(t) 2
Ts
d'(t)
i (t)
d(t) 1
Ts
Modeling the switch network via
averaged dependent sources
⟨v2(t)⟩Ts
+
Steady-state switch model:
Dc transformer model
Original switch network
i1(t)
i2(t)
Switch network
–
+
v2(t)
v1(t)
–
Q1
D1
+
Duty d(t)
cycle
Averaged steady-state model:
“DC transformer”
• Correctly represents the
relationships between the dc
and low-frequency
components of the terminal
waveforms of the switch
network
I1
D' : D
+
–
V1
V2
–
I2
+
Steady-state CCM SEPIC model
Replace switch network with dc transformer model
L1
C1
+
IL1
Vg
+ VC1 –
+
–
C2 VC2
L2
IL2
I1
R
–
• Can now let inductors
become short circuits,
capacitors become open
circuits, and solve for dc
conditions.
D' : D
+
–
V1
V2
–
+
I2
• Can simulate this model
using PSPICE, to find
transient waveforms
Modeling converter dynamics:
Small-signal linearization of model
Perturb and linearize the switch
network averaged waveforms
about a quiescent operating
point. Let:
d(t) = D + d(t)
v1(t)
i 1(t)
v2(t)
i 2(t)
Ts
Ts
Ts
Ts
= V1 + v1(t)
= I 1 + i 1(t)
= V2 + v2(t)
= I 2 + i 2(t)
Voltage equation becomes
D + d V1 + v1 = D' – d V2 + v2
Eliminate nonlinear terms
and solve for v1 terms:
V1 + V2
D'
V1 + v1 =
V +v –d
D 2 2
D
V1
= D' V2 + v2 – d
D
DD'
Linearization, continued
Current equation becomes
D + d I 2 + i 2 = D' – d I 1 + i 1
Eliminate nonlinear terms
and solve for i2 terms:
I +I
I 2 + i 2 = D' I 1 + i 1 – d 1 2
D
D
I2
= D' I 1 + i 1 – d
D
DD'
Switch network:
Small-signal ac model
Reconstruct an equivalent circuit that corresponds to these smallsignal equations:
I1 + i1
V1 + v1
–
+
–
+
D' : D
V1
d
DD'
–
I2
d
DD'
V2 + v2
+
I2 + i2
Transistor port
Diode port
A general small-signal ac model for the PWM switch network
operating in CCM.
Small-signal ac model
of the CCM SEPIC
Replace switch network with small-signal ac model:
L1
I L1 + i L1
Vg + vg
C1
+
VC1 + vC1
+
–
L2
C2 VC2 + vC2
I L2 + i L2
R
–
D' : D
+
–
V1
d
DD'
I2
d
DD'
Can now solve this
model to determine ac
transfer functions
Small-signal models
of several basic switch networks
+
i2(t)
+
I1 + i1
I2 + i2
1:D
+
–
i1(t)
+
+
V1 d
v1(t)
v2(t)
V1 + v1
–
–
–
i2(t)
+
+
–
I1 + i1
+
I2 + i2
D' : 1
+
–
i1(t)
V2 + v2
I2 d
+
V2 d
v1(t)
v2(t)
V1 + v1
–
–
–
i2(t)
+
+
I1 + i1
+
v1(t)
v2(t)
V1 + v1
–
–
–
V2 + v2
–
I2 + i2
D' : D
+
–
i1(t)
I1 d
V1
d
DD'
+
I2
d
DD'
V2 + v2
–
Table of results
Transfer functions of the basic buck, boost, and buck-boost converters
Control-to-output and line-to-output transfer functions Gvd(s) and Gvg(s)
Converter
buck
boost
buck-boost
Gd0
ω0
V
D
V
D'
V
D D' 2
1
LC
D'
LC
D'
LC
Gg0
D
1
D'
– D
D'
ωz
Q
R
D'R
D'R
C
L
∞
D' 2R
L
D' 2 R
DL
C
L
C
L
where the transfer functions are written in the standard forms
Gvd(s) = Gd0
1 – ωs
z
1 + s + ωs
Qω0
0
Gvg(s) = Gg0
2
1
1 + s + ωs
Qω0
0
2
ccm1
i1(t)
+
i2(t)
1
D
v1(t)
S
_
2
switch
network
3
+
K
A
4
i1
averaging
+
v2(t)
v1
_
_
1-d v
2
d
averaged-switch
1
model
D (sub-circuit)
+ E
Gd
t
–
S
2
5
i2
3
K
+
1-d i
1
d
A
4
v2
_
duty
d
• Controlled voltage source Et replaces the transistor, controlled
current source Gd replaces the diode
• Duty ratio d is input to the subcircuit
• Large-signal, nonlinear model suitable for DC, AC or Transient
simulation
• The same model can be applied in any two-switch PWM converter
(the transistor and the diode need not have a common node)
• Limitations: ideal switches, CCM only, valid for two-switch
converters without isolation transformer
CCM Averaged-Switch Model
PSpice Implementation: ccm1
D
1
S
2
averaged-switch
3
network
(sub-circuit)
+ E
Gd
t
–
K
4
5
A
duty
U1
S
1
2
ccm1
4
A
5 3 K
duty
D
**********************************************************
* MODEL: ccm1
* Application: two-switch PWM converters
* Limitations: ideal switches, CCM only, no transformer
**********************************************************
* Parameters: none
**********************************************************
* Nodes:
* 1: transistor+ (D)
* 2: transistor- (S)
* 3: diode cathode (K)
* 4: diode anode (A)
* 5: duty ratio (duty)
**********************************************************
.subckt ccm1 1 2 3 4 5
Et 1 2 value={(1-v(5))*v(3,4)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends
**********************************************************
Sepic converter example
using ccm1 model
L1
1
+
2x
800u
R1
0.5
V
C1
2
3
100u
4
R2
0.1
Vg
C2
L2
100u
50V
-
100u
R3
50
U1
S
sepic-ccm1.sch
1
2
ACMAG=1V
DC=0.5V
ccm1
4
A
5 3 K
duty
D
+
Vd
-
Objective: generate small-signal control-to-output frequency responses
ccm1
(A) sepic-ccm1.dat
80
magnitude || vout/d ||
40
0
-20
0d
DB(V(4))
phase of vout/d
-100d
-200d
small-signal control-to-output response
Vout=50V, R=50, D=0.5
-270d
10Hz
P(V(4))
100Hz
1.0KHz
Frequency
10KHz
100KHz
•
•
•
•
Subcircuit ccm1 is implementation of a large-signal, nonlinear
averaged model of the switch network
Averaged circuit model of the converter is obtained simply by replacing
switching devices with the averaged-switch subcircuit model
Linearization and AC small-signal analysis are performed by the
simulator
Small-signal dynamic responses can be easily generated for different
operating points or different sets of parameter values
• MOS transistor model: on-resistance RON
• Diode model: constant forward voltage drop VD in series with Rd resistance
i1(t)
• Switch network
i2(t)
1
D
+
switch
network
3
v1(t)
v2(t)
S
_
+
K
A
4
2
_
v1(t)
i1(t)
v+VD+Rd i
• Waveforms
i
Ron i
0
dTs
Ts
t
v2(t)
0
dTs
Ts
t
Ts
t
i2(t)
v-Ron i
0
i
dTs -VD-Rd i Ts
t
0
dTs
ccm2
v1(t)
i1(t)
v+VD+Rd i
i
Ron i
0
dTs
Ts
t
0
v2(t)
dTs
Ts
t
=d i
i1
Ts
i2
Ts
= (1 − d ) i
i2(t)
v-Ron i
0
i
dTs -VD-Rd i Ts
v1
v1
Ts
v1
Ts
Ts
=
t
0
dTs
= dRon i
+ v2
Ron i1
d
Ts
Ts
Ts
= v
+
i2
Ts
Ts
(
Ts
Ts
1− d
=
i1
d
t
+ (1 − d ) v
Ts
+ VD + Rd i
Ts
)
Ts
(1 − d )Rd
d
2
i1
Ts
(
1− d
+
v1
d
Ts
+ VD
)
CCM Averaged-Switch Model
PSpice Implementation: ccm2
D
S
averaged-switch
3
sub-circuit
+ E
ron
–
Gd
+ E
t
–
2
4
5
1
K
A
duty
Subcircuit implementation
U2
S
1
2
ccm2
4
A
5 3K
duty
D
**********************************************************
* MODEL: ccm2
* Application: two-switch PWM converters, includes
*
conduction losses due to Ron, VD, Rd
* Limitations: CCM only, no transformer
**********************************************************
* Parameters:
*
Ron=transistor on resistance
*
VD=diode forward voltage drop (constant)
*
Rd=diode on resistance
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm2 1 2 3 4 5
+params: Ron=0 VD=0 Rd=0
Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/v(5))/v(5)}
Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends
**********************************************************
Sepic converter example using ccm2 model
L1
1
+
2x
800u
R1
0.5
V
C1
2
3
100u
4
R2
0.1
Vg
C2
L2
100u
50V
-
100u
Iload
1A
+
-
10K
R4
U1
PARAMETERS:
0.0
Ron
Ron={Ron} S
1
ccm2
2
DC=0.5V
4
A
5 3 K Rd=0.05
VD=0.8V
duty
D
+
Vd
-
Objective: find converter efficiency as a function of the transistor
on-resistance, for a range of loads
ccm2
(D) sepic-ccm2.dat
100
Efficiency [%] (only conduction losses are included)
95
Ron=0
90
0.1
0.2
0.3
85
0.4
-100*V(4)* I(Iload)/ V(1)/ I(Vg)
80
1.0A
1.5A
2.0A
Ron=0.5
2.5A
3.0A
I_Iload
3.5A
4.0A
4.5A
5.0A
ccm3
!"
Switch network
Waveforms
1:n
v1(t)
i1(t)
i
v
i1(t)
+
i2(t)
1
D
switch
network
v1(t)
_
3
+
K
v2(t)
S
A
2
4
0
dTs
t
v2(t)
0
dTs
Ts
t
Ts
t
i2(t)
i/n
nv
_
0
PRIMARY
Ts
dTs
Ts
t
0
dTs
i2
1− d
i1
=
nd
SECONDARY
v1
Ts
1− d
v2
=
nd
Ts
Ts
Ts
• Converters: Flyback, Cuk, Sepic, Inverse Sepic (Zeta), with isolation transformer
CCM Averaged-Switch Model
PSpice Implementation: ccm3
D
1
S
2
averaged-switch
3
network
(sub-circuit)
+ E
Gd
t
–
K
4
5
A
duty
U3
S
1
2
ccm3
4
A
5 3 K
duty
D
**********************************************************
* MODEL: ccm3
* Application: two-switch PWM converters,
*
with (possibly) transformer
* Limitations: ideal switches, CCM only
**********************************************************
* Parameters:
* n=transformer turns ratio 1:n (primary:secondary)
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm3 1 2 3 4 5
+params: n=1
Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n}
.ends
**********************************************************
ccm4
• Combined ccm2 and ccm3 averaged-switch models
• Parameters:
• Transistor on resistance Ron
• Diode forward voltage drop VD
• Diode on resistance Rd
• Transformer turns ratio n
• A general model implementation valid for all two-switch converters
operating in CCM
CCM Averaged-Switch Model
PSpice Implementation: ccm4
D
S
averaged-switch
3
sub-circuit
+ E
ron
–
Gd
+ E
t
–
2
4
5
1
K
A
duty
Subcircuit implementation
U4
S
1
2
ccm4
4
A
5 3K
duty
D
* MODEL: ccm4
* Application: two-switch PWM converters, includes
*
conduction losses due to Ron, VD, Rd
*
and (possibly) transformer
* Limitations: CCM only
**********************************************************
* Parameters:
*
Ron=transistor on resistance
*
VD=diode forward voltage drop (constant)
*
Rd=diode on resistance
*
n=transformer turns ratio 1:n (primary:secondary)
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm4 1 2 3 4 5
+params: Ron=0 VD=0 Rd=0 n=1
Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/n/n/v(5))/v(5)}
Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)/n}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n}
.ends
!"
• Use averaged-switch modeling approach to construct an
averaged model that includes switching losses
• Loss mechanism example: diode reverse recovery
Modeling switching loss
iL(t)
Example: diode stored
charge in boost converter
+
–
vg(t)
Waveforms:
v1(t)
L
i1(t)
+
v1(t)
–
v2
i2(t)
+
+
v2(t) C
R
–
v2
0
0
t
dTs
tr
Ts
i 2(t)
i1
i1
0
• Determine averaged terminal
waveforms of switch network
0
t
Area –Q
r
• Other switching loss mechanisms
are ignored in this example; one
can include other losses if
desired, using a similar procedure
• Construct averaged equivalent
circuit model
v(t)
–
Expressions for average terminal waveforms
Boost converter, switching loss example
v1 (t ) T
s
1
= ((1 − d )Ts + t r ) v2 (t ) T
s
Ts
i2 (t ) T = (1 − d ) i1 (t ) T −
s
s
v1(t)
v2
v2
Qr
Ts
0
0
t
dTs
tr
i 2(t)
Ts
i1
i1
tr = diode reverse recovery time
Qr = diode recovered charge
0
0
t
Area –Q
r
Averaged equivalent circuit
of switch network

t 
v1 (t ) T = 1 − d + r  v2 (t ) T
s
s
Ts 

 Qr + t r i1 (t ) T

tr 
s
i2 (t ) T = 1 − d +  i1 (t ) T − 
s
s

Ts
Ts 


i1 (t )
i2 (t )
+
+
v1 (t )
v2 (t )
_
_
switch network



 
i1 (t ) T
s
t 
1 − d + r  : 1
Ts 

i2 (t ) T
s
+
+
v1 (t ) T
v2 (t ) T
s
Qr + t r i1
s
Ts
_
averaged switch model
• Diode reverse recovery time affects conversion ratio
• Stored charge leads to power loss, modeled by current sink
Ts
_
Insert averaged switch model into converter circuit
iL(t)
L
i1(t)
Original
converter
+
vg(t)
+
–
v1(t)
–
⟨ iL(t) ⟩T
s
Averaged
model
⟨ vg(t) ⟩T
s
+
–
L
⟨ i1(t) ⟩T
s
tr
+ (1 – d) : 1
Ts
+
i2(t)
+
+
v2(t) C
R
v(t)
–
–
⟨ i2(t) ⟩T
s
+
⟨ v1(t) ⟩Ts
Q r ⟨ v (t) ⟩
2
Ts C
Ts
–
–
+
R
⟨ v(t) ⟩Ts
–
Efficiency Analysis
Boost converter, switching loss example
η=
Pout VI 2
=
Pin Vg I1
Qr
Ts
I1 =
1− D
I2 +


VI 2  1 − D
η=
=
Vg I1  1 − D + t r

Ts

V=


 I 2

Qr
+
I
 2 T
s

Vg
tr
+1− D
Ts
 
 
1
=
 
tr
+
1
  (1 − D )T
s
 




1



Qr 
+
1


I
T
load
s


Efficiency due to diode reverse recovery. Other switching loss mechanisms
can be included using a similar procedure.
$%
•
•
•
•
Basic idea of average-switch modeling:
Define a switch network, containing all of the converter switching
elements
Average terminal waveforms over a switching period
Use controlled sources with values equal to average of the switch
network terminal waveforms
The result is a large-signal, nonlinear, time-invariant model that can be
inserted back into the converter network
The choices of the switch network and the independent terminal
waveforms are not unique - there are many ways to construct averaged
switch models
Averaged-switch model (suitable for circuit analysis or simulation)
yields predictions of converter steady-state and low-frequency dynamic
properties
Next: apply the averaged-switch modeling approach to other cases of
interest.
•
•
•
•
•
Averaged switch model in DCM
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in DCM
Combined CCM/DCM averaged switch model
PSpice implementation of combined CCM/DCM models
- ideal switches (ccm-dcm1)
- ideal switches in converters with isolation transformer (ccm-dcm2)
Application examples:
- comparison of transient simulation results in a SEPIC example
using (1) switching circuit model and (2) averaged model
- small-signal dynamic responses of a flyback converter operating in
CCM or DCM
- more converter examples using averaged-switch subcircuits
Change in characteristics at the CCM/DCM boundary
l
l
l
l
Steady-state output voltage becomes strongly load-dependent
Simpler dynamics: one pole and the RHP zero are moved to very high
frequency, and can normally be ignored
Traditionally, boost and buck-boost converters are designed to operate
in DCM at full load
All converters may operate in DCM at light load
So we need equivalent circuits that model the steady-state and smallsignal ac models of converters operating in DCM
The averaged switch approach yields an intuitive result that is relatively
easy to solve
Derivation of DCM averaged switch model
Buck-boost example
• Define switch terminal
quantities v1, i1, v2, i2, as
shown
• Let us find the averaged
quantities ⟨ v1 ⟩, ⟨ i1 ⟩ , ⟨ v2 ⟩, ⟨
i2 ⟩, for operation in DCM,
and determine the
relations between them
i1
+
vg
+
–
Switch network
i2
–
v1
v2
–
+
+
vL
–
L
iL
+
C R
v
–
DCM waveforms
iL(t)
i1(t)
ipk
Area q1
v
L
vg
L
ipk
i 1(t)
0
Ts
t
vL(t)
vg
vg – v
v1(t)
v1(t)
vg
Ts
0
0
v
i2(t)
ipk
i1
+
vg
+
–
Switch network
i2
i 2(t)
–
v1
v2
–
+
+
vL
–
L
iL
Area q2
Ts
+
v2(t)
C R
vg – v
v
v2(t)
–
0
d1 T s
d2Ts
Ts
Ts
–v
d3Ts
t
Basic DCM equations
i1(t)
Peak inductor current:
i pk =
Area q1
vg
dT
L 1 s
ipk
i 1(t)
Ts
Average inductor voltage:
vL(t)
Ts
= d 1 vg(t)
Ts
+ d 2 v(t)
Ts
+ d3 ⋅ 0
v1(t)
In DCM, the diode switches off when the
inductor current reaches zero. Hence, i(0)
= i(Ts) = 0, and the average inductor
voltage is zero. This is true even during
transients.
vL(t)
Ts
= d 1(t) vg(t)
Ts
+ d 2(t) v(t)
Ts
vg – v
v1(t)
=0
vg
Ts
0
i2(t)
ipk
i 2(t)
v2(t)
Area q2
Ts
vg – v
v2(t)
Solve for d2:
vg(t)
d 2(t) = – d 1(t)
v(t)
Ts
–v
0
Ts
d1Ts
d2Ts
Ts
Ts
d3Ts
t
Average switch network terminal voltages
i1(t)
Average the v1(t) waveform:
v1(t)
Ts
= d 1(t) ⋅ 0 + d 2(t)
vg(t)
Area q1
Ts
– v(t)
Ts
+ d 3(t) vg(t)
Ts
ipk
i 1(t)
Ts
Eliminate d2 and d3:
v1(t)
Ts
= vg(t)
vg – v
v1(t)
Ts
v1(t)
vg
Ts
0
Similar analysis for v2(t) waveform leads to
i2(t)
v2(t)
Ts
= d 1(t)
= – v(t)
vg(t)
Ts
– v(t)
Ts
+ d 2(t) ⋅ 0 + d 3(t) – v(t)
ipk
Area q2
Ts
i 2(t)
Ts
v2(t)
Ts
vg – v
v2(t)
Ts
–v
0
d1Ts
d2Ts
Ts
d3Ts
t
Average switch network terminal currents
Average the i1(t) waveform:
i 1(t)
1
=
Ts
Ts
i1(t)
t + Ts
i 1(t)dt =
t
q1
Ts
The integral q1 is the area under the i1(t)
waveform during first subinterval. Use triangle
area formula:
t + Ts
q1 =
t
Area q1
i 1(t)dt = 1 d 1Ts i pk
2
i 1(t)
v1(t)
0
i2(t)
i 2(t)
Ts
v2(t)
i 2(t)
Ts
=
v1(t)
d (t) Ts
2L
v2(t)
Area q2
Ts
vg – v
v2(t)
Similar analysis for i2(t) waveform leads to
2
1
vg
Ts
ipk
Note ⟨i1(t)⟩Ts is not equal to d ⟨iL(t)⟩Ts !
2
Ts
Ts
Ts
vg – v
v1(t)
Eliminate ipk:
d 21(t) Ts
i 1(t) T =
v1(t)
s
2L
ipk
Ts
–v
0
d1Ts
d2Ts
Ts
d3Ts
t
Input port: Averaged equivalent circuit
d 21(t) Ts
i 1(t) T =
v1(t)
s
2L
i 1(t)
Ts
=
v1(t)
Ts
Re(d 1)
Re(d 1) = 2L
d 21 Ts
i 1(t)
Ts
Ts
+
v1(t)
Ts
Re(d1)
–
Low-frequency components of input port waveforms
obey Ohm’s law
Output port: Averaged equivalent circuit
d 21(t) Ts v1(t)
i 2(t) T =
s
2L
v2(t)
2
v1(t)
2
i(t)
+
Ts
Ts
p(t)
i 2(t)
Ts
v2(t)
Ts
=
Ts
Re(d 1)
= p(t)
Ts
• Output port is a source of power p(t)
• Power p(t) is independent of load characteristics
• Power p(t) is dependent on (equal to) the power apparently
consumed by the switch network input port
v(t)
–
The dependent power source
i(t)
i(t)
+
v(t)i(t) = p(t)
p(t)
v(t)
–
• Must avoid open- and short-circuit
connections of power sources
• Power sink: negative p(t)
v(t)
How the power source arises
in lossless two-port networks
In a lossless two-port network without internal energy storage:
instantaneous input power is equal to instantaneous output power
In all but a small number of special cases, the instantaneous power
throughput is dependent on the applied external source and load
If the instantaneous power depends only on the external elements
connected to one port, then the power is not dependent on the
characteristics of the elements connected to the other port. The other
port becomes a source of power, equal to the power flowing through
the first port
A power source (or power sink) element is obtained
Properties of power sources
Series and parallel
connection of power
sources
P1
P1 + P2 + P3
P2
Reflection of power
source through a
transformer
P3
n1 : n2
P1
P1
The loss-free resistor (LFR)
i 1(t)
p(t)
+
v1(t)
i 2(t)
Ts
Ts
Ts
Re(d1)
–
A two-port lossless network
Input port obeys Ohm’s Law
Power entering input port is transferred to output port
Ts
+
v2(t)
–
Ts
Averaged switch model: buck-boost example
i1
+
Original circuit
vg
+
–
Switch network
–
v1
v2
–
+
+
vL
–
i 1(t)
Averaged model
Ts
+
v1(t)
vg(t)
Ts
+
–
i2
Ts
p(t)
+
C R
L
v
–
iL
i 2(t)
Ts
–
v2(t)
Re(d)
–
+
L
Ts
+
Ts
C
R
v(t)
–
Ts
Solution of averaged model: steady state
I1
Let
+
L → short circuit
C → open circuit
P
Vg
+
–
Re(D)
R
V
–
Converter input power:
V 2g
P=
Re
Equate and solve:
V 2g V 2
P=
=
Re
R
Converter output power:
2
V
P=
R
V =±
Vg
R
Re
Steady-state LFR solution
V =±
Vg
R
Re
is a general result, for any system that can
be modeled as an LFR.
For the buck-boost converter, we have
Re(D) = 2L
D 2Ts
Eliminate Re:
V =–
Vg
D 2TsR
=– D
2L
K
which agrees with the results of previous steady-state analyses.
Averaged models of other DCM converters
• Determine averaged terminal waveforms of switch network
• In each case, averaged transistor waveforms obey Ohm’s law, while
averaged diode waveforms behave as dependent power source
• Can simply replace transistor and diode with the averaged
model as follows:
i1(t)
+
i2(t)
+
v1(t)
v2(t)
–
–
i 1(t)
p(t)
+
v1(t)
–
i 2(t)
Ts
Ts
Re(d1)
Ts
Ts
+
v2(t)
–
Ts
DCM buck, boost
Buck
Re(d)
Re = 2L
d 2Ts
L
+
vg(t)
Ts
+
–
p(t)
C
Ts
R
v(t)
Ts
–
Boost
L
+
vg(t)
Ts
+
–
Re(d)
p(t)
C
R
v(t)
Ts
–
Ts
DCM Cuk, SEPIC
Cuk
L1
C1
Re =
L2
+
vg(t)
Ts
+
–
p(t)
Re(d)
Ts
C2
R
v(t)
Ts
–
SEPIC
L1
C1
+
vg(t)
Ts
+
–
Re(d)
L2
p(t)
Ts
C2
R
v(t)
–
Ts
2 L 1||L 2
d 2Ts
Steady-state solution: DCM buck, boost
Let L → short circuit
Re(D)
C → open circuit
+
Buck
Vg
+
–
P
R
V
–
+
Boost
Vg
+
–
Re(D)
P
R
V
–
Steady-state solution of DCM/LFR models
Converter
Buck
M, CCM
M, DCM
D
2
1 + 1 + 4Re/R
Boost
1
1–D
Buck-boost, Cuk
–D
1–D
SEPIC
D
1–D
I > I crit for CCM
I < I crit for DCM
1+
–
Vg
1
–
D
I crit =
D Re(D)
1 + 4R/R e
2
R
Re
R
Re
Small-signal ac modeling of the DCM switch network
Large-signal averaged model
i 1(t)
i 2(t)
Ts
p(t)
+
v1(t)
Perturb and linearize: let
+
Ts
d(t) = D + d(t)
v1(t) T = V1 + v1(t)
s
v2(t)
Re(d)
Ts
Ts
–
–
i 1(t)
Ts
v2(t)
i 2(t)
Ts
Ts
Ts
= I 1 + i 1(t)
= V2 + v2(t)
= I 2 + i 2(t)
d(t)
d 21(t) Ts
i 1(t) T =
v1(t)
s
2L
i 2(t)
Ts
=
2
1
v1(t)
d (t) Ts
2L
v2(t)
2
Ts
Ts
Ts
v
i 1 = r 1 + j1d + g 1v2
1
v
i 2 = – r 2 + j2d + g 2v1
2
A more convenient way to model the buck and boost
small-signal DCM switch networks
i1(t)
+
i2(t)
+
v1(t)
–
i1(t)
i2(t)
+
+
v2(t)
v1(t)
v2(t)
–
–
–
In any event, a small-signal two-port model is used, of the form
i1
i2
+
v1
–
+
r1
j1d
g 1v2
g 2v1
j2d
r2
v2
–
Small-signal DCM switch model parameters
i1
i2
–
v1
+
–
r1
g 1v2
j1d
g 2v1
r2
j2d
v2
+
Switch type
g1
j1
r1
g2
Buck,
Fig. 10.16(a)
1
Re
2(1 – M)V 1
DR e
Re
2–M
M Re
Boost,
Fig. 10.16(b)
1
(M – 1) 2 Re
(M – 1) 2
Re
M
Buck-boost,
Fig. 10.7(b)
0
Re
2MV1
D(M – 1)Re
2V1
DRe
j2
r2
2(1 – M)V1
DMRe
M 2R e
2M – 1
(M – 1) 2 Re
2V1
D(M – 1)Re
(M – 1) 2Re
2M
Re
2V1
DMRe
M 2R e
DCM small-signal transfer functions
l
l
l
l
When expressed in terms of R, L, C, and M (not D), the smallsignal transfer functions are the same in DCM as in CCM
Hence, DCM boost and buck-boost converters exhibit two poles
and one RHP zero in control-to-output transfer functions
But, value of L is small in DCM. Hence
RHP zero appears at high frequency, usually greater than
switching frequency
Pole due to inductor dynamics appears at high frequency, near
to or greater than switching frequency
So DCM buck, boost, and buck-boost converters exhibit
essentially a single-pole response
A simple approximation: let L → 0
The simple approximation L → 0
Buck, boost, and buck-boost converter models all reduce to
DCM switch network small-signal ac model
+
vg
+
–
r1
j1d
g 1v2
g 2v1
j2d
r2
C
v
R
–
Transfer functions
control-to-output
line-to-output
Gvd (s) =
Gvg(s) =
v
d
v
vg
=
vg = 0
=
d=0
Gd0
1 + ωs
Gg0
1 + ωs
with
p
Gd0 = j2 R || r 2
1
ωp =
R || r 2 C
Gg0 = g 2 R || r 2 = M
p
Transfer function salient features
Converter
Gd0
Gg0
ωp
Buck
2V 1 – M
D 2–M
M
2–M
(1 – M)RC
M
2M – 1
(M– 1)RC
M
2
RC
Boost
2V M – 1
D 2M – 1
Buck-boost
V
D
DCM boost example
Control-to-output transfer function Gvd(s)
i(t)
R = 12 Ω
L = 5 µH
D1
L
iD(t)
+ vL(t) –
Vg
+
–
+
iC(t)
Q1
C
R
C = 470 µF
v(t)
–
f s = 100 kHz
The output voltage is regulated to be V = 36 V. It is desired to determine Gvd(s) at the
operating point where the load current is I = 3 A and the dc input voltage is V g = 24 V.
Evaluate simple model parameters
P = I V – Vg = 3 A 36 V – 24 V = 36 W
V 2g (24 V) 2
Re =
=
= 16 Ω
P
36 W
D=
2L =
ReTs
2(5 µH)
= 0.25
(16 Ω)(10 µs)
2(36 V)
Gd0 = 2V M – 1 =
D 2M – 1
(0.25)
ωp
2M – 1
=
=
fp =
2π 2π (M– 1)RC
(36 V)
–1
(24 V)
2
(36 V)
–1
(24 V)
2
2π
= 72 V ⇒ 37 dBV
(36 V)
–1
(24 V)
(36 V)
– 1 (12 Ω)(470 µF)
(24 V)
= 112 Hz
Control-to-output transfer function, boost example
60 dBV
|| Gvd ||
40 dBV
∠ Gvd
Gd0 ⇒ 37 dBV
|| Gvd ||
20 dBV
fp
112 Hz
–20 dB/decade
0 dBV
0˚
–20 dBV
0˚
∠ Gvd
–90˚
–40 dBV
–180˚
10 Hz
100 Hz
1 kHz
f
10 kHz
–270˚
100 kHz
!"
•
•
Observed high-frequency response due to inductor dynamics
Averaged-switch model derivation used:
vL
Ts
=0
which is consistent with the fact that in DCM the inductor current starts
from zero and ends at zero in each switching cycle, even in transients
• However, high-frequency dynamics due to the inductor indicates that
the AC voltage across the inductor in the small-signal model is not zero
• Model predictions at high frequencies are not quite correct
• Corrected averaged models that include the inductor in the averaged
switch model have recently been described
See References: [Sun et. al. PESC’99], [Ben-Yaakov et.al. PESC’94]
Objective: a general large-signal averaged-switch model
• Valid in CCM and DCM
• 5 terminals:
transistor port (2 terminals)
diode port (2 terminals)
duty ratio input (1 terminal)
• DCM/CCM boundary resolved within the model, based only on the
terminal voltages/currents of the model
• Spice compatible
i1(t)
+
v1(t)
i2(t)
switch
network
1
3
+
v2(t)
_
2
4
_
averaged-switch
model
averaged-switch
model
CCM
i1
1
+
v1
_
3
+
–
1-d v
2
d
2
1-d i
1
d
Gd
Et
+
+
v2
v1
duty
1
p(t)
2
d
averaged-switch
model
CCM/DCM
i1
1
i2
3
?
_
2
duty
d
v2
4
5
+
_
+
v2
4
5
duty
d
i2
3
Re(d)
_
_
4
5
DCM
i1
i2
_
averaged-switch
model
CCM/DCM
i1
1
+
v1
3
K
D
+
–
1-u v
2
u
Et
2
+
1-u i
1
u
Gd
S
_
i2
v2
A
4
5
_
duty
d
CCM/DCM boundary:
d,
CCM



u=
d2
, DCM
 2
i1
 d + 2 Lf s
v2



u = MAX  d ,



u = equivalent switch duty ratio


2
d

i1 
2
d + 2 Lf s 
v2 
CCM/DCM Averaged-Switch Model
PSpice Implementation: ccm-dcm1
**************************************************************************************
* MODEL: ccm-dcm1
* Application: two-switch PWM converters, CCM or DCM
* Limitations: ideal switches, no transformer
**************************************************************************************
* Parameters:
*
L=equivalent inductance (relevant for DCM)
*
fs=switching frequency
**************************************************************************************
* Nodes: (same as in ccm1)
**************************************************************************************
.subckt ccm-dcm1 1 2 3 4 5 params: L=1 fs=1E6
Et 1 2 value={(1-v(u))*v(3,4)/v(u)}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Rdummy b 0 10
Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
**************************************************************************************
averaged-switch
model
CCM/DCM
i1
1
+
v1
3
K
D
+
–
1-u v
2
nu
2
A
4
5
+
1-u i
nu 1
Gd
Et
S
_
i2
v2
_
d,
CCM



u=
d2
, DCM
 2
i1
 d + 2nLf s
v2

duty
d
CCM/DCM boundary:


u = MAX  d ,



u = equivalent switch duty ratio


2
d

i1 
2
d + 2nLf s 
v2 
CCM/DCM Averaged-Switch Model
PSpice Implementation: ccm-dcm2
* MODEL: ccm-dcm2
* Application: two-switch PWM converters, CCM or DCM with (possibly) transformer
* Limitations: ideal switches, no transformer
****************************************************************************************
* Parameters:
*
L=equivalent inductance (relevant for DCM), referred to primary
*
fs=switching frequency
*
n=transformer turns ratio 1:n (primary:secondary)
****************************************************************************************
* Nodes: (same as in ccm1)
****************************************************************************************
.subckt ccm-dcm2 1 2 3 4 5 params: L=1 fs=1E6 n=1
Et 1 2 value={(1-v(u))*v(3,4)/v(u)/n}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)/n}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Rdummy b 0 10
Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*n*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
****************************************************************************************
•
•
•
•
ccm-dcm1 (for non-isolated converters) and ccm-dcm2 (for converters
that may include isolation transformer) are general, large-signal
averaged-switch models (PSpice subcircuits) valid for both CCM and
DCM
Can be applied to DC, AC, or Transient simulation of any two-switch
PWM converter
Limitations: ideal switches, no losses are modeled, but the model can
be refined further to include conduction losses
Application examples:
• Comparison of Transient simulation results in a Sepic converter
example using:
– (1) switching circuit model
– (2) ccm-dcm2 averaged switch model
• AC simulation results for a flyback converter operating in CCM or
DCM
Sepic converter example:
switching circuit model
L3
800u
21
+
-
22x
R6
22
0.5
V
C3
100u
23
24
Resr3 R4
0.2
0.1
R11
20
Vg2
C4
L4
100u
50V
100u
R5
100
S2
+
-
switch
M1
D1
IRF640
R7
10
V3
+
-
MUR820
+
-
Switching frequency 100kHz, duty ratio D=0.5
+
-
V4
Sepic converter example:
averaged model using ccm-dcm2
L1
1
-
0.5
2
V
C1
3
Resr1
0.2
100u
4
R10
R2
0.1
Vg
20
C2
L2
100u
50V
100u
R3
100
S1
+
U6
D
S
1
4
ccm-dcm2
2
5
ACMAG=1V
DC=0.5V
+
3
duty
+
800u
2x
R1
A
+
-
switch
K
Vd
-
Exactly the same PSpice circuit, except the MOSFET M1 and the
diode D1 replaced by the ccm-dcm2 subcircuit, and pulsating
gate drive V3 replaced by a duty-ratio voltage source Vd
+
-
V4
(B) sepic-switch.dat
80V
Vout
60V
40V
Averaged model
Switching model
start-up transient
load transient
20V
0V
0s
V(24)
V(4)
5ms
10ms
Time
Start-up and load transient response
15ms
20ms
(B) sepic-switch.dat
10A
Diode current during load transient
8A
6A
4A
switching model
2A
0A
averaged model
-2A
10.0ms
10.2ms
10.4ms
I(D1) I(X_U6.Gd)
10.6ms
10.8ms
Time
11.0ms
11.2ms
11.4ms
Details of the diode current waveform around the load transient
Flyback converter example
using ccm-dcm2 averaged-switch model
T1
1
1
Lm=50u
n=0.25 Lm
PARAMETERS:
2
Rload
+
2
-
transformer
R2
0.2
2
L=50u
fs=100K
n=0.25
4
U1
D
S
1
4
4
ccm-dcm2
2
AC=1
0.25
5
+
-
V
3
3
duty
Vg
48V
3
1:n
**
A
C1
500uF
R1
{Rload}
K
Vd
CCM for Rload=1 Ohm, DCM for Rload=2 Ohm
ccm-dcm2
(C) flyback-ccm-dcm2.dat
50
Magnitude response, control-to-output v/d
Rload = 1, CCM
0
Rload = 2, DCM
-50
DB(V(4))
0d
Rload = 1, CCM
Rload = 2, DCM
-100d
Phase response, control-to-output v/d
-200d
10Hz
P(V(4))
100Hz
1.0KHz
Frequency
10KHz
100KHz
Frequency responses generated by PSpice AC analyses
Other Converter Examples
transformer
1
2
Lm
Vg
Watkins-Johnson converter
+
1:n
**
-
3
4
S
2
Lm
1
1
2
Vg
D
transformer
ccm-dcm2
+
5
3
duty
K
3
4
A
4
1:n
**
-
+
-
Vd
Pspice averaged circuit model
using ccm-dcm2
averaged-switch subcircuit
Other Converter Examples
1
1:n
**
Vg
+
3
Cuk converter with
isolation transformer
Lm
-
2
4
transformer
1
1:n
**
Vg
+
3
Lm
2
PSpice averaged circuit model
using ccm-dcm2
averaged-switch subcircuit
4
transformer
U2
D
S
1
4
ccm-dcm2
2
5
duty
-
3
A
K
•
•
•
•
•
•
•
Averaged switch model for current-programmed mode (CPM) in
CCM
Steady-state and simple AC model in CCM
Averaged switch model for CPM in DCM
Steady-state and small-signal AC model in DCM
Large-signal averaged CCM/DCM model for current-mode
controller
PSpice implementation of the averaged CPM controller model
Application examples
- Buck converter with current-programmed mode controller
Current-programmed control
Buck converter
L
is(t)
iL(t)
+
Q1
vg(t) +
–
v(t)
C
D1
R
The peak transistor current
replaces the duty cycle as the
converter control input.
–
Measure
switch
current
is(t)
Clock
0
is(t)Rf
Control
input
Ts
S Q
+
–
ic(t)Rf
Control signal
ic(t)
Analog
comparator
m1
Latch
Current-programmed controller
0
Transistor
status:
Compensator
Switch
current
is(t)
R
–+
Rf
v(t)
vref
Conventional output voltage controller
Clock turns
transistor on
dTs
on
Ts
off
Comparator turns
transistor off
t
A simple approximation
i L(t)
Ts
= i c(t)
• Neglects switching ripple and artificial ramp (slope compensation)
• Yields physical insight and simple first-order model
• Accurate when converter operates well into CCM (so that switching
ripple is small) and when the magnitude of the artificial ramp is not
too large
• Well-accepted by practicing engineers
• Resulting small-signal relation:
i L(s) ≈ i c(s)
Averaged switch modeling
with the simple approximation
Buck converter example
i1(t)
vg(t) +
–
i2(t)
+
+
v1(t)
v2(t)
–
–
L
iL(t)
+
C
R
v(t)
–
Switch network
Averaged terminal waveforms,
CCM:
v2(t)
i 1(t)
Ts
Ts
= d(t) v1(t)
= d(t) i 2(t)
Ts
Ts
The simple approximation:
i 2(t)
Ts
≈ i c(t)
Ts
CPM averaged switch equations
v2(t)
Ts
i 1(t)
Ts
= d(t) v1(t)
= d(t) i 2(t)
i 2(t)
Ts
Ts
≈ i c(t)
Ts
Eliminate duty cycle:
i 1(t)
i 1(t)
Ts
Ts
= d(t) i c(t)
v1(t)
Ts
Ts
v2(t)
=
= i c(t)
v1(t)
Ts
Ts
i c(t)
Ts
Ts
v2(t)
Ts
= p(t)
So:
•
Output port is a current source
•
Input port is a dependent power sink
Ts
Ts
CPM averaged switch model
⟨i2(t)⟩T
⟨i1(t)⟩Ts
+
⟨vg(t)⟩Ts
+
–
⟨v1(t)⟩Ts
s
L
⟨iL(t)⟩T
s
+
⟨ p(t)⟩Ts
⟨ic(t)⟩Ts
–
⟨v2(t)⟩T
s
–
Averaged switch network
+
C
R
⟨v(t)⟩T
–
s
Results for other converters
⟨iL(t)⟩Ts
Boost
L
+
⟨ p(t)⟩Ts
⟨vg(t)⟩Ts
⟨ic(t)⟩Ts
+
–
C
R
⟨v(t)⟩T
–
Averaged switch network
Averaged switch network
Buck-boost
⟨ p(t)⟩Ts
⟨vg(t)⟩T
s
⟨ic(t)⟩T
+
s
+
–
C
R
⟨v(t)⟩Ts
L
⟨iL(t)⟩T
s
–
s
Perturbation and linearization
to construct small-signal model, CCM
Let
Resulting input port equation:
v1(t)
i 1(t)
v2(t)
i 2(t)
i c(t)
Ts
Ts
Ts
Ts
Ts
= V1 + v1(t)
= I 1 + i 1(t)
= V2 + v2(t)
= I 2 + i 2(t)
= I c + i c(t)
V1 + v1(t) I 1 + i 1(t) = I c + i c(t) V2 + v2(t)
Small-signal result:
V2
Ic
I1
i 1(t) = i c(t)
+ v2(t)
– v1(t)
V1
V1
V1
Output port equation:
î 2 = îc
Resulting small-signal model
Buck example
i1
i2
+
+
vg
+
–
v1
ic
V2
V1
–
V1
I1
v2
Ic
V1
ic
–
v2
–
Switch network small-signal ac model
i 1(t) = i c(t)
V2
I
I
+ v2(t) c – v1(t) 1
V1
V1
V1
L
+
C
R
v
–
Predicted transfer functions of the CPM buck converter
L
ig
iL
+
vg
+
–
i c D 1 + sL
R
2
D
–
R
Dv
R
ic
C
R
v
–
v(s)
Gvc(s) =
i c(s)
Gvg(s) =
v(s)
vg(s)
= R || 1
sC
vg = 0
=0
ic = 0
Table of results
basic converters
ig
+
vg
+
–
r1
f1(s) i c
g1 v
f2(s) i c
g 2 vg
r2
C
v
R
–
Converter
g1
Buck
D
R
Boost
0
Buck-boost
–D
R
f1
D 1 + sL
R
1
D 1 + sL
D'R
r1
g2
f2
r2
– R2
D
0
1
∞
∞
1
D'R
D' 1 – sL2
D' R
R
– D'R
D2
2
– D
D'R
– D' 1 – sDL
D' 2R
R
D
Discontinuous conduction mode
in current-programmed converters
•
Again, use averaged switch modeling approach
•
Result: simply replace
Transistor by power sink
Diode by power source
•
Inductor dynamics appear at high frequency, near to or greater
than the switching frequency
•
Small-signal transfer functions contain a single low frequency pole
•
DCM CPM boost and buck-boost are stable without artificial ramp
•
DCM CPM buck without artificial ramp is stable for D < 2/3. A
small artificial ramp ma ≥ 0.086m2 leads to stability for all D.
DCM CPM buck-boost example
iL(t)
i1(t)
vg(t)
+
–
Switch network
i2(t)
+
–
v1(t)
v2(t)
–
+
L
iL(t)
ic
– ma
ipk
+
C R
m1
v(t)
=
v1
–
vL(t)
m2 =
v2
Ts
L
Ts
0
L
t
v1(t)
Ts
0
v2(t)
Ts
Analysis
i pk = m 1d 1Ts
v1(t)
m1 =
L
Ts
iL(t)
ic
– ma
ipk
m1
i c = i pk + m ad 1Ts
= m 1 + m a d 1Ts
d 1(t) =
=
vL(t)
v1
m2 =
Ts
L
Ts
0
L
t
v1(t)
Ts
i c(t)
m 1 + m a Ts
v2
0
v2(t)
Ts
Averaged switch input port equation
1
i 1(t) T =
s
Ts
i 1(t)
Ts
=
1
2
t + Ts
i 1(τ)dτ =
t
q1
Ts
i1(t)
Area q1
ipk
i pk(t)d 1(t)
i 1(t)
i 1(t)
i 1(t)
i 1(t)
Ts
Ts
Ts
=
1
2
Ts
2
1
m 1d (t)Ts
1
2
=
v1(t)
v1(t)
Ts
Ts
=
i2(t)
Li 2c fs
ma
1+
m1
1
2
ipk
2
i 2(t)
Li 2c fs
ma
1+
m1
Area q2
2
= p(t)
Ts
Ts
d1Ts
d2Ts
Ts
d3Ts
t
Discussion: switch network input port
•
Averaged transistor waveforms obey a power sink characteristic
•
During first subinterval, energy is transferred from input voltage
source, through transistor, to inductor, equal to
1
W = 2 Li 2pk
This energy transfer process accounts for power flow equal to
p(t)
1
Ts
= W fs = 2 Li 2pk fs
which is equal to the power sink expression of the previous slide.
Averaged switch output port equation
1
i 2(t) T =
s
Ts
q2 =
1
2
t + Ts
i 2(τ)dτ =
t
Area q1
v1(t)
v2(t)
p(t)
i 2(t)
i1(t)
i pkd 2Ts
d 2(t) = d 1(t)
i 2(t)
q2
Ts
Ts
Ts
=
v2(t)
v2(t)
Ts
i 1(t)
Ts
Ts
Ts
i2(t)
ipk
Ts
Ts
=
ipk
i 2(t)
1
2
Area q2
Ts
Li 2c (t) fs
m
1 + ma
1
2
= p(t)
Ts
d1Ts
d2Ts
Ts
d3Ts
t
Discussion: switch network output port
•
Averaged diode waveforms obey a power sink characteristic
•
During second subinterval, all stored energy in inductor is
transferred, through diode, to load
•
Hence, in averaged model, diode becomes a power source,
having value equal to the power consumed by the transistor
power sink element
Averaged equivalent circuit
i 1(t)
Ts
+
v1(t)
vg(t)
Ts
+
–
p(t)
i 2(t)
Ts
–
v2(t)
Ts
–
+
L
Ts
+
Ts
C
R
v(t)
–
Ts
Steady state model: DCM CPM buck-boost
+
P
Vg
+
–
R
V
–
Solution
V2 = P
R
P=
1
2
V= PR = I c
LI 2c (t) fs
Ma
1+
M1
2
RL fs
Ma
2 1+
M1
for a resistive load
2
Models of buck and boost
L
Buck
+
vg(t)
Ts
+
–
p(t)
C
Ts
R
v(t)
Ts
–
Boost
L
+
vg(t)
Ts
+
–
p(t)
C
R
v(t)
Ts
–
Ts
Summary of steady-state
DCM CPM characteristics
Converter
M
Buck
Pload – P
Pload
Boost
Pload
Pload – P
Buck-boost
Depends on load characteristic:
1
2
Pload = P
Icrit
Stability range
when m a = 0
I c – M m a Ts
0≤M <2
3
I c – M – 1 m a Ts
M
2M
0≤D≤1
M m T
M –1 a s
0≤D≤1
Ic –
2 M –1
I > I crit
for CCM
I < I crit
for DCM
Linearized small-signal models
Buck
i1
+
vg
+
–
v1
L
i2
iL
+
r1
g 1v2
f1 i c
g 2v1
f2 i c
r2
–
+
v2
C
v
R
–
–
Boost
iL
L
i1
i2
+
vg
+
–
v1
–
+
r1
f1 i c
g 1v2
g 2v1
f2 i c
r2
v2
–
+
C
R
v
–
Linearized small-signal models: Buck-boost
i1
i2
+
v1
vg
+
–
–
r1
f1 i c
g 1v2
g 2v1
–
f2 i c
r2
v2
+
+
C
R
v
–
L
iL
DCM CPM small-signal parameters: input port
Buck
Boost
f1
g1
Converter
m
1 – ma
1
m
1 + ma
1
2
1 M
R 1–M
M
– 1
R M –1
2
I1
Ic
r1
–R 1–M
M2
R
2 I
Ic
M2
Buck-boost
0
2
I1
Ic
m
1 + ma
1
m
1 – ma
1
m
2 ma
2–M +
1
m
M –1 1+ a
m1
m
1 + ma
1
–R
M 2 1 – ma
m1
DCM CPM small-signal parameters: output port
Buck
1 M
R 1–M
Boost
Buck-boost
f2
g2
Converter
ma
m1 2 – M – M
2 I
Ic
m
1 + ma
1
1
M
R M –1
ma
m1
2M
R
m
1 + ma
1
r2
m
1 + ma
1
m
1 – 2M + m a
1
1–M
R
2
I2
Ic
R M –1
M
2
I2
Ic
R
Simplified DCM CPM model, with L = 0
Buck, boost, buck-boost all become
+
vg
+
–
r1
g 1v
f1 i c
g 2vg
f2 i c
r2
C
R
v
–
Gvc(s) =
v
ic
=
vg = 0
Gc0
1 + ωs
Gc0 = f2 R || r 2
1
ωp =
R || r 2 C
p
v
Gvg(s) =
vg
ic
Gg0
=
s
1
+
ω
=0
Gg0 = g 2 R || r 2
p
!"#
-ma
i pk = ic − ma dTs
ic
ipk
-ma
iL(t)
m1
iL(t)
-m2
m1
t
0
iL
1 − d

d2 =  i
 pk
 m2Ts
ic
ipk
Ts
dTs
d2Ts=(1-d)Ts
m dT

= d  i pk − 1 s
2

0
dTs
(d+d2)Ts
d2Ts
t
Ts
m2 d 2Ts 


d
i
+
−

 2  pk
2 


CCM
CCM/DCM:
DCM
Ts
-m2

d 2 = MIN 1 − d ,

i pk 

m2Ts 
!"#
Inputs:
m1
ic
m2
iL

i − ma dTs 

d 2 = MIN 1 − d , c
m2Ts 

d2
Model:
d=
Output: duty ratio
2ic (d + d 2 ) − 2 iL
Ts
− m2 d 22Ts
m1dTs + 2ma (d + d 2 )Ts
d
Ts
CPM Large-Signal Averaged Model:
PSpice Implementation
**********************************************************
* MODEL: CPM
* Current-Programmed-Mode CCM/DCM controller model.
* All parameters and inputs are referred to
* the primary side.
**********************************************************
* Parameters:
* L=equivalent inductance, referred to primary
* fs=switching frequency
* va=amplitude of the artificial ramp, va=Rf*ma/fs
* Rf=equivalent current-sense resistance
**********************************************************
* Nodes:
* ctr: control input, v(ctr)=Rf*ic
* current: sensed average inductor current v(current)=Rf*iL
* 1: voltage across L in interval 1, slope m1=v(1)/L
* 2: (-) voltage across L in interval 2, slope m2=v(2)/L
* d: duty ratio (output of the controller)
**********************************************************
.subckt CPM ctr current 1 2 d
+params: L=100e-6 fs=1e5 va=0.5 Rf=0.1
*
* generate d2 for CCM/DCM
Ed2 d2 0 table
+ {MIN(
+ L*fs*(v(ctr)-va*v(d))/Rf/(v(2)),
+ 1-v(d)
+ )} (0,0) (1,1)
*
Em1 m1 0 value={Rf*v(1)/L/fs}
Em2 m2 0 value={Rf*v(2)/L/fs}
*
* generate duty-ratio d (valid CCM and DCM operation)
*
Eduty d 0 table
+{
+ 2*(v(ctr)*(v(d)+v(d2))
+ -v(current)-v(m2)*v(d2)*v(d2)/2)
+ /(v(m1)*v(d)+2*va*(v(d)+v(d2)))
+ } (0.01,0.01) (0.99,0.99)
*
.ends ; end of subcircuit CPM
**********************************************************
•
•
•
•
•
Demonstrate how CCM/DCM averaged-switch model can be used
together with CCM/DCM averaged model of the current-mode controller
Use DC sweep simulation to show steady-state characteristics
including operation in DCM or CCM
Use AC simulation to show control-to-output responses compared for
duty-ratio control and current-mode control, in DCM or CCM
Use parametric sweep simulation to find the amplitude of the artificial
ramp to minimize input-to-output audio-susceptibility
Specifications:
• Input Vg = 28V, output V = 5-20V, 0.5-2A
• Switching frequency fs=100kHz, inductance L = 35uH
• Equivalent current-sense resistance Rf = 1
• Artificial-ramp amplitude Va = 0-3V
Buck Converter with Current-Mode Control
U2
1
L=35uH
fs=100K
DC=28V Vg
S
1
2
4
ccm-dcm1
3
5
duty
D
+
L1
A
VDB
2x R1
35uH
3
5.315V
0.05
K
C1
-
100u
d
2
L=35uH
duty fs=100kHz
va={Va}
Rf=1
V2
OUT-
E3
OUT+
531.52mV
IN-
EVALUE
i(L1)
IN+
OUT-
OUT-
OUT+
IN-
IN-
IN+
V1 1
-
Rf iL CURRENT
D
OUT+
+
Vc
IN+
DC=2V
177.09mV
U1
CPM
Vc CTR
ctr
E2
E4
EVALUE V(1)-V(2x) EVALUE
Example: Cpm-buck
R2
10
V(2x)
PARAMETERS:
1
Va
(E) cpm-buck.dat
1.0V
1-d
DCM
0.8V
CCM
d2
0.6V
0.4V
0.2V
u
d
0V
0.5V
V(d)
1-V(d)
1.0V
1.5V
V(Xs.u) V(Xcpm.d2)
2.0V
2.5V
3.0V
Vc
Duty ratio d, equivalent duty ratio u, and diode conduction
interval d2 as functions of the control input Vc
(F) cpm-buck.dat
3.0
2.5
2.0
Vc=Rf*Ic
1.5
iL
1.0
0.5
0
0.5V
I(L1)
v(ctr)
1.0V
1.5V
Vc
2.0V
2.5V
3.0V
Average inductor current iL as a function of the control input Vc
(H) cpm-buck.dat
100
50
MAGNITUDE
v/d
v/vc
0
PHASE
-50
v/vc
Vc=2.0, CCM
-100
v/d
-150
-200
10Hz
100Hz
DB(V(3)) DB(V(3)/v(d)) P(V(3))
1.0KHz
P(V(3)/v(d))
Frequency
10KHz
100KHz
Control-to-output frequency responses for duty-ratio control (v/d)
and current-mode control (v/vc). The converter operates in CCM.
(H) cpm-buck.dat
50
MAGNITUDE
0
v/d
v/vc
PHASE
-50
Vc=1.5, DCM
v/vc
-100
-150
10Hz
100Hz
1.0KHz
DB(V(3)) DB(V(3)/v(d)) P(V(3)) P(V(3)/v(d))
v/d
Frequency
10KHz
100KHz
Control-to-output frequency responses for duty-ratio control (v/d)
and current-mode control (v/vc). The converter operates in DCM.
(A) cpm-buck.dat
-20
Audio-susceptibility v/vg as a function of the artificial-ramp amplitude Va
-30
-40
-50
-60
-70
Va=0.8, v/vg(0) = -62.848dB
0
VDB(3)
0.5
1.0
1.5
2.0
Va
Parametric sweep used to determine amplitude of the artificial ramp
Va to minimize input-to-output response (audio-susceptibility) v/vg.
•
•
•
•
Ideal rectifier
Averaged model obtained by averaging over switching period
Averaged model obtained by averaging over line period
Application examples:
- Power factor corrector based on boost converter operating in DCM
- Power factor corrector based on SEPIC with nonlinear-carrier control
Properties of the Ideal Rectifier
It is desired that the rectifier present a resistive load to the ac power
system. This leads to
• unity power factor
• ac line current has same waveshape as voltage
vac(t)
i ac(t) =
Re
Re is called the emulated resistance
iac(t)
+
vac(t)
–
Re
Control of power throughput
V 2ac,rms
Pav =
Re(vcontrol)
Power apparently “consumed” by Re
is actually transferred to rectifier dc
output port. To control the amount
of output power, it must be possible
to adjust the value of Re.
iac(t)
+
vac(t)
Re(vcontrol)
–
vcontrol
Output port model
The ideal rectifier is
lossless and contains no
internal energy storage.
Hence, the
instantaneous input
power equals the
instantaneous output
power. Since the
instantaneous power is
independent of the dc
load characteristics, the
output port obeys a
power source
characteristic.
iac(t)
Ideal rectifier (LFR)
+
vac(t)
2
p(t) = vac /Re
Re(vcontrol)
i(t)
+
v(t)
–
–
ac
input
dc
output
vcontrol
v 2ac(t)
p(t) =
Re(vcontrol(t))
v 2ac(t)
v(t)i(t) = p(t) =
Re
Equations of the ideal rectifier / LFR
Defining equations of the
ideal rectifier:
vac(t)
i ac(t) =
Re(vcontrol)
When connected to a
resistive load of value R, the
input and output rms voltages
and currents are related as
follows:
v(t)i(t) = p(t)
Vrms
=
Vac,rms
R
Re
v 2ac(t)
p(t) =
Re(vcontrol(t))
I ac,rms
=
I rms
R
Re
A switch network that is capable of satisfying the above (averaged)
equations can be employed in low-harmonic rectifier applications
Single-phase system with internal energy storage
iac(t)
vac(t)
pload(t) = VI = Pload
Ideal rectifier (LFR) i (t)
2
ig(t)
⟨ pac(t)⟩T
+
vg(t)
+
+
s
Re
C
–
vC(t)
Dc–dc
converter
–
i(t)
v(t)
–
Energy storage
capacitor
Energy storage capacitor
voltage vC(t) must be
independent of input and
output voltage waveforms, so
that it can vary according to
d
=
1
2
Cv 2C(t)
dt
= pac(t) – pload(t)
This system is capable of
•
Wide-bandwidth control of
output voltage
•
Wide-bandwidth control of
input current waveform
•
Internal independent energy
storage
load
Large signal model
averaged over switching period Ts
⟨ ig(t)⟩Ts
Ideal rectifier (LFR)
s
⟨ p(t)⟩T
⟨ vg(t)⟩T
s
+
–
⟨ i2(t)⟩T
Re (vcontrol )
+
s
C
⟨ v(t)⟩T
s
–
ac
input
dc
output
vcontrol
Ideal rectifier model, assuming that inner wide-bandwidth loop
operates ideally
High-frequency switching harmonics are removed via averaging
Ac line-frequency harmonics are included in model
Nonlinear and time-varying
Load
Predictions of large-signal model
Ideal rectifier (LFR)
⟨ ig(t)⟩Ts
If the input voltage is
vg(t) = 2 vg,rms sin ωt
⟨ p(t)⟩T
⟨ vg(t)⟩T
s
+
–
Re (vcontrol )
⟨ i2(t)⟩T
s
+
s
C
⟨ v(t)⟩T
–
Then the
instantaneous power
is:
vg(t)
ac
input
dc
output
vcontrol
2
v 2g,rms
p(t) T =
=
1 – cos 2ωt
s
Re(vcontrol(t)) Re(vcontrol(t))
Ts
which contains a constant term plus a secondharmonic term
s
Load
Separation of power source into its constant and
time-varying components
⟨ i2(t)⟩T
s
+
V 2g,rms
–
cos 2 2ωt
Re
V 2g,rms
Re
C
⟨ v(t)⟩Ts
Load
–
Rectifier output port
The second-harmonic variation in power leads to second-harmonic
variations in the output voltage and current
Removal of even harmonics via averaging
v(t)
⟨ v(t)⟩Ts
⟨ v(t)⟩T
2L
t
T2L =
1
2
2π = π
ω ω
Resulting averaged model
⟨ i2(t)⟩T2L
+
V 2g,rms
Re
C
⟨ v(t)⟩T2L
–
Rectifier output port
Time invariant model
Power source is nonlinear
Load
Perturbation and linearization
The averaged model predicts that the rectifier output current is
p(t)
i 2(t)
T 2L
=
v(t)
T 2L
T 2L
=
v 2g,rms(t)
Re(vcontrol(t)) v(t)
= f vg,rms(t), v(t)
Let
T 2L
, vcontrol(t))
T 2L
with
v(t)
i 2(t)
T 2L
T 2L
= V + v(t)
V >> v(t)
= I 2 + i 2(t)
I 2 >> i 2(t)
vg,rms = Vg,rms + vg,rms(t)
vcontrol(t) = Vcontrol + vcontrol(t)
Vg,rms >> vg,rms(t)
Vcontrol >> vcontrol(t)
Linearized result
vcontrol(t)
I 2 + i 2(t) = g 2vg,rms(t) + j2v(t) –
r2
where
df vg,rms, V, Vcontrol)
g2 =
=
dvg,rms
– 1 =
r2
v g,rms = V g,rms
df Vg,rms, v
d v
, Vcontrol)
T 2L
T 2L
=–
dvcontrol
I2
V
v T =V
2L
df Vg,rms, V, vcontrol)
j2 =
Vg,rms
2
Re(Vcontrol) V
v control = V control
V 2g,rms
dRe(vcontrol)
=–
VR 2e (Vcontrol) dvcontrol
v control = V control
Small-signal equivalent circuit
i2
+
r2
j2 vcontrol
g 2 vg,rms
C
v
R
–
Rectifier output port
Predicted transfer functions
Control-to-output
v(s)
1
= j2 R||r 2
vcontrol(s)
1 + sC R||r 2
Line-to-output
v(s)
1
= g 2 R||r 2
vg,rms(s)
1 + sC R||r 2
Constant power load
ig(t)
iac(t)
vac(t)
pload(t) = VI = Pload
i2(t)
⟨ pac(t)⟩Ts
+
vg(t)
Re
–
+
+
C
vC(t)
Pload V +
–
v(t) load
–
–
Ideal rectifier (LFR)
Energy storage
capacitor
Dc-dc
converter
Rectifier and dc-dc converter operate with same average power
Incremental resistance R of constant power load is negative, and is
2
V
R=–
Pav
which is equal in magnitude and opposite in polarity to rectifier
incremental output resistance r2 for all controllers except NLC
i(t)
Transfer functions with constant power load
When r2 = –R, the parallel combination r2 || R becomes equal to zero.
The small-signal transfer functions then reduce to
j
v(s)
= 2
vcontrol(s) sC
g
v(s)
= 2
vg,rms(s) sC
!
Objectives:
• Example of how large-signal averaged-switch model can be used for
analysis and simulation of a power-factor corrector
• Show examples of averaged pulse-width modulator model, and
implementation of closed-loop control
• Use transient simulation to study start-up transient response of the PFC
and harmonic distortion of the AC line current in steady state
Specifications:
• Input: 120Vrms, 50Hz. Output: 300VDC, 100W
• Switching frequency: 100kHz
!
L
iline
vline
+
ig = <iL>
<id>
L
is
id
vg
+
+
vco
Vo
Co
_
_
_
Switching circuit model
iline
vline
+
ig = <iL>
vg
_
<is>
Re
+
+
p(t) vco
V
Co
_
_
Averaged circuit model (in DCM)
Boost converter operates in DCM at constant duty ratio, constant frequency
i g = is
Ts
+ id
vg
v g2
p
=
+
=
+
Re V − v g Re Re (V − v g )
vg
Ts

vg  1
ig = 
Re  vg
1−
 V






2L
Re = 2
D Ts
Line current distrortion due
to this term
DCM Boost PFC
D1
D2
Vac
VAMPL=170
FREQ=50
Averaged
model of
the boost
rectifier
0.2
diode
+
output
200uH
D3
diode
U1
D
fs=100KHz
L=200uH
S
-
PARAMETERS:
900
Rload
1
4
ccm-dcm1
2
3
5
V
diode
L1
duty
R2
A
K
C1
150uF
R1
{Rload}
D4
diode
R6 10K
12V
VCC
d
0.9
Voffset
-
+
0.5
m
+
-
5V
Vref
4
U2A
+ 3
V+
1
LM324
V- 2
11
+
-
R3
600K
2V
0.1
PWM
Averaged PWM model: d=vm/VM=0.5vm,
Dmin=0.1, Dmax=0.9 limits
R5 3.3K C2 1u
R4
10K
Closed-loop output
voltage control
(A) dcm-boost-rectifier-closed-loop.dat
0.8
Duty ratio d
100W load
0.4
50W load
0
400V
V(d)
50W load
100W load
200V
0V
0s
V(output)
50ms
100ms
Time
150ms
Start-up transient response for full load and 50% load
200ms
(A) dcm-boost-rectifier-closed-loop.dat
1.5A
100W load
1st harmonic: 0.87A
3rd harmonic: 0.14A (16.4%)
THD: 16.4%
1.0A
0.5A
0A
50W load
1st harmonic: 0.48A
3rd harmonic: 0.08A (16.2%)
THD: 16.2%
-0.5A
-1.0A
-1.5A
180ms
I(Vac)
185ms
190ms
Time
195ms
AC line current waveforms at full load and 50% load
200ms
(A) dcm-boost-rectifier-closed-loop.dat
2.0A
0A
50W load
-2.0A
100W load
150W load
-4.0A
-6.0A
Converter operates in CCM
-8.0A
500ms
I(Vac)
505ms
510ms
Time
515ms
AC line current waveforms at full load (100W),
50% load, and 150% load
520ms
136 turns #18
2400uF
1uF
IRF840
53 turns
#18
AC line
voltage
120V, 60Hz
R s is
Nonlinear-Carrier
Controller
53 turns
#18
Magnetics 1F19 UU
vm
+
–
is
Vref
voltage-loop
error amplifier
• Active current shaping using Nonlinear Carrier Control method
• Sepic converter has integrated magnetics designed for zero switching
ripple in the AC line current
• Specifications:
• Input: 90-120Vrms, 60Hz. Output: 48VDC, 200W
• Switching frequency: 90kHz
Objectives:
• Show application of the CCM/DCM averaged-switch model in powerfactor correctors with active current shaping and closed-loop output
voltage control
• Show average model implementation of a nonlinear pulse-width
modulator (NLC controller)
• Compare average model predictions to experimental results:
• AC line current waveshapes
• Start-up and load transient responses
switch
drive
switch
current sensor
d
vq(t) = Rs < is >
Q
R
Q
S
+
–
is [5A/div]
NLC generator
vc(t) vc(t) = vm f(t/Ts)
vm
clock
vc
T
f (t / Ts ) = vm s
t

t 
1 − 
 Ts 
1 − d vg
=
d
V
i g = is
Ts
Rs is
Ts
1− d
= vm
d
 v
ig =  m
 RsV

vg

vq
c(t)
d=
Ideal current shaping
vm
Rs is
Ts
+ vm
NLC Controller Model
Sepic PFC with NLC Control:
Simulation Model
n=0.94
1uF
D4
diode
C3
2
-
4
0
0
68K
U1
S
2
3
5
K
Vcc
12V
0
Vref
4
U2A
+ 3
V+
1
LM324 10.4V
V- 2
11
+
0
R2
A
E1
EVALUE
V(m)/(Rs*I(Vsense)+V(m))
0
NLC controller
NLC controller model
OUT+
IN+
OUT-
IN-
m
0
R4 15k
0
C4
0
-
L=180uH
fs=90kHz
4
ccm-dcm1
-
1
duty
D
0
17
0
transformer
0
D2
diode
Rload
Vsense
+
VAMPL=170
D1
diode
2400uF
Lm
+
-
Vac
950uH
n=1
T1 Lm=180uH
1:n 3
1
**
L-13-23
TX1 C1
+
D3
diode
1 * * 3
0
2 1:n 4
Coupledinductor
model
1uF
18K
R3
0
Closed-loop output
voltage control
1A
0.5A
2A
iline
iline
0A
0A
-0.5A
Simulation
-1A
Simulation
-2A
iline [2A/div]
iline [1A/div]
0
0
Line current harmonics [2.4%/div]
3
5
7
9
Line current harmonics [1.6%/div]
11
13
15
17
Experiment
3
5
7
9
11
13
15
17
Experiment
AC line current waveform and spectrum at 50W load (left) and
170W load (right)
vo
50V
vo
30V
vm
10V
vm
0V
iline [2A/div]
3A
iline
0A
-3A
Simulation
Experiment
50W to 125W load transient in the Sepic PFC
200V
vg
vg
0V
3A
iline [2A/div]
iline
0A
-3A
10V
vm
vm
0V
vo
100V
vo
0V
Experiment
Simulation
Start-up transient in the Sepic PFC at 50W load
•
•
•
•
The averaged switch modeling approach: replace switch network with
an equivalent circuit that correctly predicts the low-frequency
components of the switch network terminal waveforms
Seminar addressed:
- PWM converters in continuous and discontinuous conduction modes
- PWM converters with current-programmed mode (CPM) control
- Single-phase low-harmonic rectifiers (power-factor correctors)
In each case, the large-signal averaged switch model can be used:
- to develop steady-state and (by linearization) small-signal circuit
models suitable for analysis
- to construct Spice-compatible model implementations suitable for
DC, Transient and AC simulations
A number of PSpice model implementation examples and converter
application examples were presented
Selected books:
R.W. Erickson, Fundamentals of Power Electronics, Chpman & Hal, 1997.
Web page: http://ece-www.colorado.edu/~pwrelect/book/bookdir.html
J.G.Kassakian, M.F.Schlecht, G.C.Verghese, Principles of Power Electronics, Addison-Wesley, 1991.
A.Kislovski, R.Redl, N.Sokal, Dynamic Analysis of Switched-Mode DC/DC Converters, New York: Van
Nostrand Reinhold, 1994.
P.T. Krein, Elements of Power Electronics, Oxford University Press, 1998.
Daniel M. Mitchel, DC-DC Switching Regulator Analysis, New York: McGraw-Hill, 1988.
N.Mohan, T.Undeland, W.Robbins, Power Electronics: Converters, Applications and Design, Second Edition,
John Wiley & Sons, 1995.
S.M. Sandler, SMPS Simulation with Spice 3, McGraw Hill, 199.
Selected papers on averaged modeling of switching power converters
R. M. Bass, J. Sun, “Averaging under large-signal conditions,” IEEE PESC 1998, pp. 630-632.
R.Erickson, M.Madigan, S.Singer, “Design of a simple high power factor rectifier based on the flyback
converter,” IEEE APEC, 1990, pp.792-801.
P. Krein, et al, "On the Use of Averaging for the Analysis of Power Electronic Systems," IEEE Transactions on
Power Electronics, Vol. 5, No. 2, pp 182-190, April
1990.
K.Mahabir, G.Verghese, J.Thottuvelil, A.Heyman, “Linear averaged and sampled data models for large signal
control of high power factor AC-DC converters,” IEEE PESC, 1990, pp. 372-381.
D.Maksimovic, S.Cuk, ``A unified analysis of PWM converters in discontinuous modes,'' IEEE Trans. on Power
Electronics, Vol.6, No.3, July 1991.
D.~Maksimovic, Y.Jang and R.Erickson, ``Nonlinear-carrier control for high power factor boost rectifiers,'' IEEE
Transactions on Power Electronics, Vol.11, No.4, July 1996, pp.578-584.
R.D.Middlebrook and Slobodan Cuk, “A general unified approach to modeling switching-converter power
stages, International Journal of Electronics, Vol.42, No.6, pp.521-550, June 1977.
R.D.Middlebrook, “Topics in multiple-loop regulators and current-mode programming,” IEEE PESC, 1985, pp.
716-732.
Selected papers on averaged modeling of switching power converter (continued)
R.D.Middlebrook, “Modeling current programmed buck and boost regulators,” IEEE Trans. On Power
Electronics, Vol.4, No.1, January 1989, pp.36-52.
S.R.Sanders, G.C.Verghese, “Synthesis of averaged circuit models for switched power converters,” IEEE
Transactions on Circuits and Systems, Vol.38, No.8, pp.905-915, August 1991.
S.Singer, R.W. Erickson, “Power source element and its properties,” IEE Proceedings - Circuits Devices
Systems, Vol.141, Np.3, pp.220-226, June 1994.
J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, “Averaged modeling of PWM converters in discontinuous
conduction mode: a reexamination,” IEEE PESC 1998, pp.615-622.
J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, “Averaged models for PWM converters in discontinuous
conduction mode,” HFPC 1998.
J.Sun, R.M.Bass, “Modeling and practical design issues for average current control,” IEEE APEC 1999.
R. Tymerski and V. Vorperian, “Generation, classification and analysis of switched-mode DC-to-Dcconverters
by the use of converter cells,” INTELEC 1986, pp.181-195.
E. Van Dijk, H.J.N.Spruijt, D.M.O’Sullivan, J.B.Klaassens, “PWM switch modeling of DC/DC converters,” IEEE
Transactions on Power Electronics, Vol.10, No.6, November 1995, pp. 659-665.
Selected papers on averaged modeling of switching power converter (continued)
G. Verghese, C. Bruzos, K. Mahabir, “Averaged and sampled-data models for current mode control: a
reexamination,” IEEE PESC, 1989, pp.484-491.
V.Vorperian, R.Tymerski, F.C.Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE
Transactions on Power Electronics, Vol.4, No.2, pp.205-214.
V.Vorperian, “Simplified analysis of PWM converters using the model of the PWM switch: Parts I and II,” IEEE
Transactions on Aerospace and Electronic Systems, Vol.AES-26, pp.490-505, May 1990.
G.W.Wester and R.D.Middlebrook, “Low-frequency characterization of switched Dc-Dc converters,” IEEE
Transactions on Aerospace and Electronic Systems, Vol.AES-9, pp.376-385, May 1973.
R.~Zane, D.~Maksimovic, ``Nonlinear-carrier control for high-power-factor rectifiers based on flyback, Cuk or
Sepic converters,'’ Proc. IEEE APEC, March 3-7, 1996, San Jose, CA, pp.814-820.
Selected papers on averaged model implementation for computer simulation
V. Bello, "Computer Aided Analysis of Switching Regulators Using SPICE2," IEEE PESC, 1980 Record, pp 311.
V. Bello, "Using The SPICE2 CAD Package for Easy Simulation of Switching Regulators in Both Continuous
and Discontinuous Conduction Modes," Powercon 8, April, 1981, pp H3-1-14.
V. Bello, "Using the SPICE2 CAD Package to Simulate and Design the Current Mode Converter," Powercon
11, April 1984.
Y. Amran, F. Huliehel, S. Ben-Yaakov, “A unified SPICE compatible average model of PWM converters,” IEEE
Transactions on Power Electronics, Vol. 6, No. 4, pp. 585-594, 1991.
S. Ben-Yaakov, “Average simulation of PWM converters by direct implementation of behavioral relationships,”
IEEE APEC, pp.510-516, 1993.
S.Ben-Yaakov, D.Adar, “Average models as tools for studying dynamics of switch mode DC-DC converters,”
IEEE PESC 1994, pp.1369-1376
S. Ben-Yaakov, Z. Gaaton, “Generic SPICE compatible model of current feedback in switch mode converters,
Electronics Letters, Vol. 28, No. 14, 2nd July 1992.
V.M.Canalli, J.A.Cobos, J.A.Oliver, J.Uceda, “Bihavioral large signal averaged model for DC/DC switching
power converters,” IEEE PESC 1996.
Selected papers on averaged model implementation for computer simulation
D. Edry, M. Hadar, O. Mor, S. Ben-Yaakov, “A SPICE compatible model of tapped inductor PWM converter,”
IEEE APEC 1994, pp.1035-1041.
S. Hageman, "Behavioral Modeling and PSPICE Simulate SMPS Control Loops,” PCIM, April 1990, pp 13-24
and May 1990, pp 47-50.
N. Jayaram, D. Maksimovic, “Power factor correctors based on coupled-inductor Sepic and Cuk converters
with nonlinear-carrier control,” IEEE APEC 1998.
D. Kimhi, S. Ben-Yaakov, “A SPICE model for current mode PWM converters operating under continuous
inductor current conditions,” IEEE Transactions on Power Electronics, Vol.6, No.2, pp.281-286, 1991.
R. Michelet and W. Roehr, "Evaluating Power Supply Designs with CAE Models” APEC 89, pp 323-334.
D. Monteith and D. Salcedo, "Modeling Feedforward PWM Circuits Using the Nonlinear Function Capabilities
.
of SPICE II," Powercon 10,March 1983