CLOSING
THE
FEEDBACK
LOOP
by
Lloyd
Switching
feedback
power
systems
and
load
the
closed
supplies
in order
regulation
and
loop
can
be
dynamic
82(5):
Pulse
width
He(5):
Output
Fortunately,
only
once
use
of
Bode
a
in
the
gain
plots
provide
a
loop
The
the
switching
frequency,
pulse
width
modulator
the
filter,
choice
is
to
He(s),
of
circuit
define
compensation
closed
load
loop
regulation
are
the
the
and
The
characteristic
and
circuit
Nyquist
powerful
by
task
in
the
that
for
good
be
stabilized
crossover
occurs
permitting
stability
method
(see
of
81(5),
can
gain
characteristic,
predetermined
gain-bandwidth
1,
elements:
networks
the
error
and
application
the
and
feedback
amplifier
result
dynamic
displaying
B).
characteristics
circuit,
82(5),
closing
will
the
criterion.
of
Appendix
fc,
the
gain-frequency
and
power
switching
networks,
Figure
switching
systems
Unity
parameters
topology.
in
major
diagram
control
of
simple
shown
these
power
block
frequency
gain
negative
for
line
filter
version
the
and
loop
vs.
As
of
compensation
techniques.
simplified
calculating
and
closed-loop
analytical
closed-loop
objectives
comparator
Control
these
simple
use
design
terms
modulator
power
1.
in
and
amplifier
Figure
Jr
response.
described
Error
( 5 ) :
Dixon,
almost
always
to
achieve
Reference
81
using
H.
and
in
response,
the
of
and
the
loop
related
optimum
line
and
stability.
2-1
UNITRODE
CORPORATION.
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LEXINGTON,
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TEL
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95-1064
CLOSED LOOP DESIGN PROCEDURE
(1]
Define
loop
the
Goal:
Make
characteristic
bandwidth
that
for
good
a
Bode
will
dynamic
plot
of
achieve
the
the
response,
line
desired
best
and
closed-
possible
load
gain-
regulation
and
stability.
(2)
Define
method.
the
Make
pulse
width
(3)
Design
phase
the
THE
Stabilit~
the
to
feedback
systemJ.
The
'phase
at
is
at
the
At
the
overshoot
is
amount
is
slightly
will
ringing.
A
very
to
practice.
The
conditionall~
gain
That
when
the
easy
the
gain(dB)
is
and
the
G1(s)
objective.
it
then
phase
the
180
the
lag
(in
negative
may
is
phase
less
exceed
180
degrees
will
unity
If
the
'gain
(0
the
(small
exhibit
45
at
The
than
degrees.
of
lag
degrees.
180
but
dB)
phase
phase
condsiderable
degrees
provides
for
60
good
be
40
the
6AIN
becomes
(~J
what
runs
as
load.
20
into
with
The
oscillate
underdamped
of
phase
degrees
BO
if
exactly
system
180
magnitude
the
stable.
gain
margin
if
shift
which
than
gain
than
the
is
the
stable
overshoot.
will
signal
bounds,
step
changes
in
will
a
but
is
less
than
below
than
system
decreases
unstable.
It
is
stability
of
exceed
not
stable,
if
is
be
stable,
phase
this
is
is
lag
little
lag
2,
phase
criterion
phase
but
Cut
loop
system
the
less
0
Short
closed
by
phase
be
at
frequencies
gain
is
greater
severe
the
Figure
less
which
180
degrees
fc
where
the
have
control
filter.
the
result
still
fc,
the
stability
the
system
the
the
Subtract
frequencies,
will
by
with
Nyquist's
large
large
He(s),
The
the
the
only
and
happens
upon
characteristic
(1).
fc,
other
system
response
loop
and
degree
system
where
is
to
180
factor
the
dB,
attain
once,
normal
the
fc
permits
from
freq~ency,
frequency
good
only
margin'
margin),
gain
switch,
Referring
d8J
frequency,
the
lag
to
and
crossover
margin'
Decide
the
Network:
necessary
(0
addition
degrees
power
above
crossover
180
and
Gain:
G2(s),
GOAL
unity
at
Outgut
of
(2)
Criterion:
crosses
to
plot
Com~ensation
in
characteristic
lag
Bode
modulator
plotted
DEFINE
Control
a
o
or
ringing.
-20
Frequency
Stabilization
by
frequency
gain
Unity
at
gain
substantially
filter
to
achieve
using
a
pole
off
Method:
to
a
roll
very
cross
loop
low
PHASE
loop
-w
the
low
""
+
frequency.
over
below
pole
good
dominant
o
must
the
frequency
occur
-100
output
to
avoid
Figure
2-2
UNITRODE
CORPORATION.
5 FORBES
ROAD.
LEXINGTON,
MA 02173.
TEL
(617) 661-6540
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.TELEX
95-1064
the
additonal
cut
stabilization
Closed
phase
Looc
network
to
by
lag
lower
frequencies
low
goal
-20
as
fc
Crossover
to
sampling
[2)
The
cycle,
is
drive
high
the
In
in
the
plane
zeros
to
well
before
Because
the
to
C,
shows
it
fc.
is
1/2
fs/2).
fs/[2~D)
system
error
not
than
frequency,
with
duty
response
amplifier
ripple
a crossover
amplifier
gain
voltage
a
to
further
frequency
because
of
fc
=
right-half-
gain-bandwidth.
how
to
Control
closed
the
The
width
upon
loop
run
mode
at
fixed
the
Bode
of
and
only
of
part
the
usually
of
the
to
of
designed
the
total
loop
is
loop,
output
This
task
each
PWM-switching
the
The
design
started.
control
of
PWM
it
gain
--the
in
error
facilitated
by
topology
previously
circuit
defined
into
gain
and
plots.
operation
has
a
of
design
PWM
methods
This
which
a
is
the
the
He(sJ.
to
are
switching
the
frequency,
basis
for
and
networks.
considers
is
the
translate
PWM
the
system
on
C
modulator
the
performance
compensation
discussion
the
filter,
loop
remainder
eq.uations
for
method:
the
of
Appendix
of
output
elements
gain
the
is
of
fundamental
network.
in
frequency
the
are
plot
design
These
of
the
pulse
great
effect
plus
output
compensation
given
characteristic,
characteristics
closing
a Bode
parameters
vs.
of
make
transfer
These
to
and
or
filter
to
know
physical
function
linearly
necessitating
error
supply.
process
equations
that
a
at
above
greater
output
attained
G2(sJ,
control
combination.
the
of
gain
off
well
theory
the
frequency
and
power
the
amplifier
of
falls
until
switching
always
vs.
circuit
necessary
phase
that
high
frequency
saturation,
gain,
phase
circuit,
switching
switching
the
all
response.
amplified
Appendix
not
output
and
switching
order
in
but
insufficient
gain
the
is
and
extremes.
Gain
fs/[27rD)
into
given
or
control
PWM,
=
the
fc
instability.
is
when
fc
exceeds
At fc = fs/[27rD),
fc
at
and
THE CONTROL TO OUTPUT GAIN
combined
and
180
fc.
attempted,
DEFINE
At
the
dynamic
frequencies.
resulting
lag
any
is
cause
amplifier
examples
is
The
[3)
to
error
reduction
fs/4
fast.
The
Sampling
at
unstable
0.5.[1)
high
of
dynamic
[1)
[which
and
to
operating
phase
signal
short
stabilization
characteristic
2.
information
enough
out
regulation.
Freauenc~:
system
becomes
D, greater
than
be
degree
frequency
maximally
may
DC
90
the
degrees
loop
this
regulation
circuit
Figure
good
of
ringing
at
closed
in
small
transmit
45
made
the
good
possible
the
within
be
designing
gain
oscillations,
avoid
with
Maximum
loop
result
response.
load
approach
provides
provides
in
and
to
shown
d8/decade
High
goal
high
for
pole
The
dynamic
line
must
frequency
at
The
not
analysis
single
poor
optimize
must
A practical
net
introduces.
is
providing
Phase
Stability
it
Objective:
is
response
lag
method
POWER
SWITCH
v
s 0-!
Vc Q-J
rnmm
~~~:1...
all
comparator
Figure
3
2-3
UNITRODE
CORPORATION.
5 FORBES
ROAD.
LEXINGTON,
MA 02173.
TEL.
(617) 861-6540
.TWX
(710) 32&-6509.
TELEX
95-1064
as
shown
fixed
in
Figure
frequency
3.
A
linear
output
provides
rectangular
power
switching
transistors.
conduction
is
between
Vc
Direct
Dut~
most
most
is
constant
and
Control:
IC's.
response
to
audio
regulation,
gain
to
phase
filter
input
poor
Poor
open
to
the
relationship
to
a
v
v,t-
~r1
Figure
provides
changes
desired
4.
In
no
characteristic
Control
make
.-
loop
[2)
filter
help
in
with
dealing
its
with
sudden
must
propagate
through
output
correction,
180
these
resulting
Control:
duty
cycle
Functions
control
one
key
sawtooth
ramp
is
but
input
in
tage
direct
[see
exception
not
~1
--the
constant
amplitude,
proportion
Figure
5).
to
The
I
v-,
the
ef-
,1
I
~
/
/
/.
-L
~
v..T7:ji-
fect
of
this
dramatic.
the
input
input
VinD,
Current
Mode
IC,
voltage
to
a
the
Figure
a
voltage
compared
control
voltage
longer
the
current
a
the
second,
a
voltage
programs
controls
ramp.
inner
reference,
the
the
duty
inductor
cycle
current
the
before,
but
the
6).
control
The
from
via
the
inductor
the
loop.
as
case,
generator,
(Figure
to
derived
the
control
circuit
back
control
is
this
ramp
resistor
fed
in
the
In
a
switching
is
amplifier
embodied
comparing
sampling
ramp
error
to
by
power
required,
is a third
capability.
from
current
5.
gain
is
UC184O
method,
cycle
sawtooth
from
formin~
of
control
duty
artificially
through
out
loop
The
feedforward
newest
derived
inductor
comparator,
no
prob-
voltage
frequency
not
rT
line
the
the
directly
voltage
and
with
This
fixed
is
waveform
Thus
loop
and
controls
provided
current
IC
;1
:J m
...
without
Open
Control:
also
voltage
is
constant
constant
good,
control
UC1846
ramp
is
inversely
with
the
volt-second
direct
duty
cycle
control
in [1)
are
corrected.
Much
less
closed
to achieve
good
dynamic
response.
generation
but
very
directly
Vc
remains
is
of
if
change.
regulation
is
varies
varies
Thus
control
lems
above
mostly
modification
Vs
voltage,
duty
cycle
voltage.
product,
any
simple
Because
with
two
in
v
02
,~
with
varies
vol
the
degree
response.
Feedforward
like
direct
above
switch
loop
higher
regulators,
pole
dynamic
Voltaae
exactly
changes.
Poor
mode
shift.
poles
the
power
the
Slow
specifications.
two
a
Provides
changes.
requiring
continuous
drive
the
as
anticipate
voltage
achieve
resonant
[1)
to
susceptibility.
line
which
of
4),
exactly
are:
sudden
v
ramp
Figure
operates
input
oldest,
sawtooth
[see
feedforward
of
to
comparator
implemented
The
Disadvantages
affects
compared
The
pulses
cycle
according
The
method,
amplitude,
voltage
duty
is
Vs.
frequency
The
controlled
used
circuit
above.
no
C~cle
control
the
Vc,
voltage,
Vs.
commonly
in
voltage,
ramp
fixed
thereby
and
control
sawtooth
control
output
now
inner
the
loop
directly.
2-4
UNITROOE CORPORATION.
5 FORBES ROAO .LEXINGTON,
MA 02173. TEL. (617) 861-6540. TWX (710) 326-6509. TELEX 95-1064
~
The
results
of
this
method
Vcc
are
~
profound.
All
of
the
problems
of
the
di rect
duty
cycl
e control
method
(1)
and
(2)
above
are
corrected
mode
with
control.
In
having
the
characteristic
voltage
neous
open
input
changes,
control
tor
filter
pole
is
reduces
order
filter
to
response
the
order
simpl
single
capacitor)
Current
mode
switching
required
Appendix
upon
the
the
\1-
used
from
~
with
,
U
U
L
greater
magnetizing
acts
to
rather
mode
compensation,
cycles
transformer
load
current
6.
continuous
slope
duty
is
I
,
Figure
at
amount
I'
,
Latch
n
n
n
output-J
LJ
LJ
L
circuits
stability
but
pole
benefit
A.
Power
reflected
sation,
\I-."
permits
networks.
control
for
Clock
easy
first
circuits
1
J:
loop.
not
filter,
which
compensation
er
~
J1..:
second
is
a
a
Letch
this
inner
to
filter
R
mode
pole
which
comoareto,
induc-
because
two
PWM
~.~
to
the
compensate
(the
to
current
inside
~
feedforward
with
instanta-
pole,
This
k
current
eliminates
t
Error
amplIfier
addition
loop
~
Reference
-
than
current
provide
some
variable
and
power
and
it
50%.
is
Ref.
superimposed
slope
compen-
indeterminate.
DESIGN THE COMPENSATION NETWORK
The
control
overall
sought
to
closed
in the
general,
(1)
excess
phase
shift
poles
has
frequency.
Put
poles
ESR zeros
output
gain.
teristic
(3)
and
low
If
regulation
pair
(4)
an
In
prevent
it
frequency
from
gain
of
power
switching
use
of
has
is
the
voltage
off
added
a
as
desired.
to
obtain
step
gain.
certain
(1),
so
the
near
the
occur
in the
low
in
to
the
In
frequencies
gain
up
flatten
the
that
cross-
frequencies
control
gain
to
charac-
desired
add
a
DC
pole-zero
amount
of
juggling
will
handle
most
These
circuits
with
inevitable.
Two
are
example
the
will
too
the
output
degrees)
network
zeros
circuits
given
that
in
problems
essentially
input
invariably
flat
that
A.
Appendix
method
C.
to
with
appear
the
to
that
of
avoid
the
circuits
on
Try
combination
characteristic
capacitor,
results
levels
Appendix
in
tapalagy/cantral
no
that
(45
falling
is
boost
to
from
characteristic
network.
near
control
zeros
zeros
Circuits:
to
network
the
margin
these
low
frequency
to
complex
situations,
applied
abnormal
in
adequate
requirements
which
behavior
involves:
compensation
Otherwise
ComDensation
subtracted
defines
the
compensation
in
the
compensation
and
right-half-plane
solutions
sation
characteristic
roughly
with
its
occur
because
at
trial
the
gain
objective
amplifier
the
procedure
Put
zeros
in
the
where
over
(2)
where
output
loop
error
compenare
use
the
allows
circuit
A-1
poor
large
signal
like
A-2
because
of
input
capacitor,
Ci.
2-5
UNITRODE
CORPORATION.
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LEXINGTON,
MA 02173.
TEL.
(617) 861-6540
.TWX
(710) 326-6509
.TELEX
95-1064
Determine
Closed
DC
regulation
but
this
is
gain
of
the
Loop
of
Reaulation:
the
often
It
system
using
awkward
and
often
changes
system
is
possible
classical
of
to
questionable
as
calculate
closed
loop
value,
a function
the
analysis,
because
of
input
the
and
load
variables.
It
is
simpler
the
and
large
equation
examples)
of
maintain
the
line
less
output
circuit.
(3)
provide
the
percentage
The
result
Vc
of
the
(2)
for
range
frequency
the
the
One
alternative
gain
because
is
mode
when
the
ramp
such
correspondingly
use
required
be
to
expressed
as
a
gain-bandwidth
scheme,
an
IC
with
there
is
are
a better
some
amplifier,
frequency.
control
pole
slope
as
in
method
that
are
filter
is
is
now
error
Control
to
highest
available
requires
less
eliminated
with
characteristic
is
the
or
duty
loop
input
gone
with
error
also
to
and
The
control
by
the
full
voltage
is
increased
reduces
set
slope
voltage.
requirement
This
be
control
ramp
smaller
gain-bandwidth
is
the
clamp
a
can
greater
reducing
cycle
voltage.
input
UC1846,
with
gain-bandwidth
the
comparator
by
controlled
output
of
the
UC1840
achieved
amplifier
output
requirement
at
the
reducing
range
and
the
compensation
voltage
amplifier
problems
two
gain-bandwidth
range,
a
be
even
Divide
E/A
can
of
course
not
control.
independently,
output
the
crossover
use
the
error
the
to
extremes
of
will
(2)
the
which
compensation
regulation
and
current
of
DC
(Eq.
1a in
required
under
conditions.
as
the
voltage.
(1)
the
to
line
feedforward,
output
on
Use
swing
must
the
system
gain
If
desired
than:
down
of
swing,
output
regulation
Vc,
level
Vc
or
output
control
DC
(1)
combination
voltage,
desired
low
nominal
other
back
Also,
the
Gain-bandwidth:
enough
alternatives
or
at
is
is:
method
control
desired
the
desired
Insufficient
not
by
the
really
The
extreme
ramp
amplitude
the
swing
calculate
it
DC
voltage
over
Vc
to
that
conditons.
sawtooth
control
extreme
direct
problem
the
topology/control
calculate
the
to
and load
than
the
have
more
signal
reduced.
sensing
the
gain-bandwidth
amplifier.
EXAMPLES OF CLOSING THE LOOP
Examples
are
operated
in
worked
modes,
and
voltage
feedforward
In
examples
the
current
actual
to
be
primary
ratio,
if
basis
in
three
an
10:1
is
used,
for
to
voltages,
not
feedback
for
range
of
the
of
currents
The
duty
current
cycle
of
consistency
level
visible.
voltage
topologies
control,
control.
voltage
the
basic
inductor
direct
elements
transformed
are
input
most
continuous
mode
assumed
All
C for
as
methods:
current
given,
side
well
control
and
of
Appendix
as
comparison.
assumed
the
using
range
direct
out
discontinuous
12
power
a 12
and
volt
2:1
and
and
to
circuit
volt
are
output,
and
transformer
output
load
permit
turns
is
used
as
sensing.
2-6
UNITRODE
CORPORATION.
5 FORBES
ROAD.
LEXINGTON.
MA 02173.
TEL.
(617) 861-6540
.TWX
(710) 326-6509
.TELEX
95-1064
MISCELLANEOUS POINTS
EMI
Filter
its
resonance
near
Resonance:
the
Phase
pulse
the
laq:
This
DOWer
and
~
to
the
sure
is
or
not
severe
additional
phase
crossover
frequency
loop
instability.
of
Ji.!lg
the
the
lag
with
of
1
phase
the
control
of
pulse
width
time,
td,
value
modulation
cause
and
of
ideally
Ji.!lg
converter
comparator
will
a
the
termination.
..§1l.!:! jJ1
switch
use
wherein
pulse
however,
power
chips
width,
instantaneous
modulator
delay
delays
a
signal
phase
lag
frequency,
a
the
may
phase
at
switching
frequency
of
9
margin
therefore
example,
microsecond
lag
= 360 td f
reduces
and
For
consistent
PWM
relationship:
gain
additional
make
filter,
moment
practice,
in
This
time
used,
frequency
pulse
to
method
delays
to
of
the
+m = 360 td/T
storage
is
output
majority
at
.!..9..9. jJ1
proportional
kHz,
the
according
~.(2Jln
time
according
filter
resonant
determining
voltage
~hase
switchinq
storage
directly
vast
of
sampled"
in
EMI
its
of
terminated
control
"naturally
results
The
method
is
feedback
input
and
result.
comparator
output
an
damped
frequency
will
Modulator
f,
well
resonant
interaction
simple
When
is
in
a
the
degrees,
at
the
contribute
crossover
to
frequency
greater
power
reducing
unity
control
of
than
50kHz,
switch
will
cause
phase
margin
25
a
an
by
that
amount.
REFERENCES
[1)
J.
R.
Crossover
04.16,
(2)
March
R.
Converter
Wood,
Frequency
D.
"Taking
in
Account
Closed
Loop
of
Output
Design,"
Resistance
POWERCON
10,
and
pp.
D4.1-
1983.
Middlebrook,
Feedback
"Predicting
Loops,"
Modulator
POWERCON
8,
pp.
Phase
H4.1-H4.6,
Lag
April
in
PWM
1981.
2-7
UNITRODE
CORPORATION.
5 FORBES
ROAD.
LEXINGTON,
MA 02173.
TEL.
(617) 861-6540.
TWX (710) 32&-6509
.TELEX
95-1064
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