Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials, Nagoya, 2011, pp1464-1465
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A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure
Daisuke Suzuki1,2, Masanori Natsui1,2, Tetsuo, Endoh1,3, Hideo Ohno1,4, and Takahiro Hanyu1,2
1
Center for Spintronics Integrated Systems (CSIS), Tohoku University, JAPAN
2
Laboratory for Brainware Systems, Tohoku University, JAPAN
3
Center for Interdisciplinary Research, Tohoku University, JAPAN
4
Laboratory for Nanoelectronics and Spintronics, Tohoku University, JAPAN
Phone: +81-022-217-5508, E-mail: {show-you, natsui, hanyu}@ngc.riec.tohoku.ac.jp
1. Introduction
The implementation of a nonvolatile field-programmable
gate array (FPGA) [1] is one promising solution for completely eliminating static power dissipation with an instant-on capability [2]. We have presented a nonvolatile
lookup table (NVLUT) circuit combining with magnetic
tunnel junction (MTJ) devices with MOS transistors [3, 4]
which is a fundamental component of a nonvolatile FPGA.
It is also necessary to design a nonvolatile logic element
(NVLE) which is composed of an NVLUT circuit and a
nonvolatile flip-flop (NVFF). This paper presents a compact MTJ/MOS-hybrid NVLE where both the NVLUT circuit and the NVFF are implemented based on a dynamic
current-mode logic (DyCML) [5, 6]. Since the low swing
signal from an MTJ device can be applied as logic value
directly, the proposed NVLE can be implemented compactly. The use of a DyCML also makes it possible
high-speed switching operation with low dynamic power.
In fact, the proposed 4-input NVLE reduces transistor
counts to 55 percent compared to a conventional nonvolatile SRAM (NVSRAM) [7] based implementation. Moreover, the switching delay and the active power of the proposed circuit are reduced to 83 percent and 64 percent with
HSPICE simulation under a 90-nm CMOS technology.
2. MTJ/MOS-Hybrid Nonvolatile Logic Element
Figure 1 shows a block diagram of the proposed 2-input
NVLE which is composed of a 2-input NVLUT circuit, an
NVFF and a multiplexer (MUX). Any 2-input combinational functions are performed by the NVLUT circuit and
sequential functions also can be performed by the combination of the NVLUT circuit and the NVFF.
Figure 2 shows a block diagram of the proposed 2-input
NVLUT circuit which is composed of a pre-charged sense
amplifier (PCSA) [8], a current selector and a reference
current generator. An MTJ device stores data Y as a resistance value; Y=1 corresponds to low resistance RP and Y=0
to high resistance RAP. When EN and CLK are activated at
high level, one current path in the current selector is activated according to the complementary inputs (X1, X1’) and
(X2, X2’), and a current IX is generated, while a reference
current IREF is generated by the reference current generator.
The small difference between IX and IREF is sensed and
complementary full-swing outputs (D, D’) are generated by
the PCSA. The MTJ devices in the reference current generator are used to adjust IREF according to the process variation [4]. MTJ devices in the NVLUT circuit are configured
by using word lines and bit lines such as WL0, WL1, BL0
and BL1.
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Figure 3 shows a circuit diagram of the proposed NVFF.
It consists of an NMOS-based differential-pair circuit
(DPC), cross-coupled CMOS inverters, two MTJ devices
and MTJ writing circuit. The complementary inputs (D, D’)
from the NVLUT circuit are stored in the cross-coupled
CMOS inverters in the normal operation. They are also
stored in MTJ devices (M, M’) in the master latch when
WCKB is activated at low level.
The behavior of the master latch is explained as follows.
Figure 4 (a) shows a THROUGH phase (CLK=1 and
CLK’=0). Assume that the voltage at the input node D is
VDD and that at D’ is 0V. Since M1 and M4 are turned on,
the load capacitance Cq’ is discharged to GND and M6 is
turned on. As a result, the load capacitance Cq is charged
and the voltage at the output node q becomes VDD while q’
becomes 0V. Figure 4 (b) shows a HOLD phase (CLK=0
and CLK’=1). Since M3 is turned ON, the voltages at the
output nodes (q, q’) are held in the cross-coupled CMOS
inverters. At the same time, M1 and M2 are turned off so
that the DPC does not operate. As a result, there is no DC
current path from VDD to GND. Figure 4 (c) shows a
STORE phase. When the input data (D, D’) is (1, 0) and
WCKB is activated at low level, M10 and M13 are turned
on by NOR gates and write current IW is applied to the MTJ
devices. To configure (M, M’) simultaneously, the voltage
signal VW is applied to M10 and M11 in the STORE phase.
Figure 4 (d) shows a RESTORE phase. When RESB is
activated at low level, M9 is turned on and the voltages at q
and q’ are balanced, and as a result, a clamped voltage is
supplied to each MTJ device. Then, the sensing currents IM
and IM’ penetrate through M and M’ respectively. When
RESB is activated at high level, M9 is turned off and the
difference between IM and IM’ is amplified by the
cross-coupled CMOS inverters.
3. Evaluation
A test chip where MTJ devices are stacked over the
CMOS logic circuit plane with 90-nm CMOS process has
been fabricated. Figure 5 (a) shows a measured R-I curve of
the fabricated MTJ device and Fig. 5 (b) shows its measurement environment. Since the total resistance of MOS
transistor is 0.18 kΩ in the deep-triode region, RP and RAP
are 2.60 kΩ and 1.27 kΩ respectively. The performance
comparisons between a conventional NVSRAM [7] based
4-input NVLE using a CMOS-based NVFF [9] and the
proposed one, are performed by the HSPICE simulation
under a 90-nm CMOS technology with the characteristics
of the fabricated MTJ device. Table I summarizes the result.
Since the small difference between IX and IREF can be applied as logic value directly, the sense amplifier is shared in
the proposed NVLUT circuit and the number of transistor is
greatly reduced. As a result, the proposed NVLE exhibits
45 percent of transistor counts reduction. Moreover, the use
of DyCML enables both 17 percent of the switching delay
and 36 percent of the active power reduction.
4. Conclusions
A compact MTJ/MOS-hybrid NVLE and its advantages
compared to a conventional NVSRAM based implementation are presented. It is important to discuss the relationship
between configuration energy and time of the MTJ devices.
As future prospect, it is expected that the MTJ/MOS-hybrid
FPGA realizes ultra-low power reconfigurable computing.
References
[1] V. Betz et al., IEEE Design & Test of Computers 15 (1998)10.
[2] Y. Guillemenet et al., IET Comput. Digit. Tech. 4 (2010) 211.
[3] D. Suzuki et al., Symp. VLSI Circuits Dig. Tech. (2009) 80.
[4] D. Suzuki et al., Ext. Abst. SSDM (2010) 1146.
[5] M. W. Allam et al., IEEE JSSC 36 (2001) 550.
[6] A. Mochizuki et al., IEICE Trans. Electron. 11 (2006) 1591.
[7] W. Zhao et al., Phys. Status Solidi A 205 (2008) 1373.
[8] W. Zhao et al., IEEE Trans. Magn. 45 (2009) 3784.
[9] N. Sakimura et al., IEEE JSSC 44 (2009) 2244.
VDD
VDD
M5
Cq’
M6
M9
M7
CLK’=0
(D, D’)
(X2, X2’)
Nonvolatile
(Q, Q’)
Flip-Flop
(NVFF)
(Y00,Y01,Y10,Y11)
Complementary
Inputs
SEL
MUX
Nonvolatile
Lookup Table
(NVLUT)
Circuit
CLK
D=0
VW
M4
M3
M2
D’=0
M4
CLK=0
(b)
M9
M7
M10
VDD
M8
M5
VW
IW
IM
M13
M3
CLK’=0
M9
M7
M=1 M’=0
M12
M6
M11
RESB=1
WCKB
=0
Complementary
Outputs
q’ = 0
q =1
Cq
M8
M1
(a)
D =1
(M, M’)
D’=0
M2
D’=0
(Z, Z’)
M9
M7
CLK’=1
M3
CLK=1
M6
RESB=1
M1
This research is supported by the JSPS through FIRST Program.
The authors also wish to thank Noboru Sakimura and Ryusuke
Nebashi of NEC, for help in fabrication of the chip.
(X1, X1’)
Cq
M5
RESB=1
D=1
Acknowledgements
M8
q’ = 0
q = 1 Cq’
M8
RESB
0→1
RP RAP
M=1 M’=0
CLK’=1
q’ = 0
q =1
IM’
M3
Fig. 1 Block diagram of the proposed NVLE.
(c)
CLK
(d)
Fig.4 Basic behavior of the NVFF: (a) THROUGH phase
(b) HOLD phase (c) STORE phase (d) RESTORE phase.
VDD
CLK
D
D’
R
Sense Amplifier
IX
Current Selector
X1
Y01
IIN
2.78kΩ
X1
X1’
X2
X2’
Reference
Current
Generator
1V
WL5
WL3
Y10
X2’
X2
WL2
Y11
X1’
X2’
WL1
WL0
X2
IREF
Y00
R
1.45kΩ
I11
I10
I01
WL6
BL0
I00
1V
EN
WL9
WL8
WL4
WL7
BL1
-180uA
RMTJ
RMTJ
RAP if Y = 0
RP if Y = 1
IX > IREF → (D, D’)=(1, 0)
IX < IREF → (D, D’)=(0, 1)
EN
GND
MTJ Device
Fig. 2 Circuit diagram of the proposed NVLUT.
MTJ Writing
Circuit
D’
M9
M10
WCKB
Conventional
Q’
Q
M8
RESB
M
M11
M3
CLK
M2
M1
CLK
M4
Master Latch
Proposed
29 MOSs
+ 2 MTJs
NVLUT
154 MOSs
+ 32 MTJs
70 MOSs
+ 20 MTJs
NVLE
198 MOSs
+ 34 MTJs
109 MOSs
+ 22 MTJs
Delay (*2)
180 ps
149 ps
Active Power
@1GHz (*2)
14.0 uW
9.02 uW
0 uW
0 uW
Standby Power
CLK’
(*1)
NVFF
M13
CLK’
(b)
38 MOS
+2 MTJs
Number
of
Devices
VW
M’
M12
D
q’
q
M6
M7
VW
IIN
Table I Performance comparisons of 4-input NVLEs.
VDD
M5
112uA
Fig. 5 Measurement of an R-I curve of the fabricated MTJ device:
(a) measured R-I curve (b) measurement environment.
BL2
Y
(a)
VDD = 1.0 [V], VW = 1.3 [V]
Slave Latch
(*1) It is composed of NVSRAM [7] and CMOS-based NVFF [9].
(*2) HSPICE simulation under a 90-nm CMOS technology.
Fig. 3 Circuit diagram of the proposed NVFF.
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