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IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 52, NO. 2, MAY 2010
Signal Integrity Design for High-Speed Digital
Circuits: Progress and Directions
Jun Fan, Senior Member, IEEE, Xiaoning Ye, Member, IEEE, Jingook Kim, Member, IEEE,
Bruce Archambeault, Fellow, IEEE, and Antonio Orlandi, Fellow, IEEE
(Invited Paper)
Abstract—This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines,
discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.
Index Terms—Differential signaling, discontinuities, equalization, equivalent circuit modeling, high-speed digital circuits, jitter
analysis, mode conversion, modulation, signal integrity (SI), SI
measurements, transmission line losses.
I. INTRODUCTION
IGNAL integrity (SI) is the practice of ensuring sufficient
fidelity of a signal transmitted between a driver and a receiver for proper functioning of the circuit, e.g., the signals over
the high-speed bus between a processor and its chipset. The integrity of a signal in real-world applications is compromised by
artifacts of the layout of the circuits on a printed circuit board
(PCB), the type of IC package being used, and is impacted by the
circuit logic family, power delivery network, and other aspects
of high-speed digital design. These nonideal, real-world effects
can lead to severely distorted voltage and current waveforms
and signal jitter, and result in faulty switching and logic errors.
Originating from timing issues in digital circuits, SI design
has undergone significant development in the past 15 years, and
grown into an area covering many critical aspects in high-speed
digital circuit design, including signal propagation on transmission lines (loss, termination, crosstalk, etc.), characterization
of parasitics and discontinuities, power integrity, IC driver and
receiver modeling, link-path and jitter analysis, interconnect design, and so on. With the continuous increase of operating speed,
frequency, and circuit density, as well as the decrease of circuit
dimension, system form factor, and logic level, nowadays it is
increasingly critical to ensure good SI design for high-speed
digital circuits [1]. Otherwise, they may not function properly.
S
Manuscript received September 29, 2009; revised February 17, 2010. First
published April 1, 2010; current version published May 19, 2010.
J. Fan and J. Kim are with the EMC Laboratory, Missouri University of
Science and Technology (formerly University of Missouri-Rolla), Rolla, MO
65401 USA (e-mail: jfan@mst.edu; kimjing@mst.edu).
X. Ye is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail:
xiaoning.ye@intel.com).
B. Archambeault is with International Business Machines Corporation, Research Triangle Park, Durham, NC 27713 USA (e-mail: barch@us.ibm.com).
A. Orlandi is with the Department of Electrical Engineering, University of
L’Aquila, L’Aquia I-67040, Italy (e-mail: antonio.orlandi@univaq.it).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TEMC.2010.2045381
Recent progress and future directions of SI design for highspeed digital circuits will be briefly overviewed in this paper.
However, it is not meant to be thorough and comprehensive
due to the length restriction and the limited knowledge of the
authors. In addition, two important topics, SI simulation and
power integrity, will have separate review papers, and thus, are
not the focus of this paper.
Signal propagation on transmission lines will be discussed
first in Section II, focusing on losses and differential signaling. Then, discontinuity modeling and measurement techniques
will be reviewed in Sections III and IV, respectively. Link-path
design and analysis will be covered in Section V, including
equalization and modulation techniques as well as jitter models.
II. SIGNAL PROPAGATION ON TRANSMISSION LINES
In today’s high-speed digital systems, traces in PCBs or multichip modules (MCMs) are usually not electrically short any
more, and thus, need to be treated, designed, and analyzed using
a multiconductor transmission line (MTL) model [2], [3]. The
term MTL typically refers to a set of n + 1 electrically long parallel conductors that transmit electrical signals between two or
more points, e.g., between a driver and a receiver. Although this
model was originally developed in the early fifties [4], the first
systematic approach oriented to electromagnetic compatibility
(EMC) and SI applications was reported in [5] and [6], respectively. Since then, much advancement has been achieved on the
solution of the MTL equations [7], [8], as well as on the adapting
of the model to evolving PCB technology. MTL structures on a
typical PCB or MCM consist of conductive traces buried in or
attached to a lossy dielectric layer with one or more reference
planes. Effects previously considered to be negligible and ignored in low-speed digital designs can become primary design
issues with the increase of signal speed and the decrease of circuit form factor. Nonideal effects such as frequency-dependent
losses, imbalance, and mode conversion are among the most
important variables that can significantly affect SI in modern
designs.
A. Frequency-Dependent Losses
Frequency-dependent losses during the propagation of digital signals on transmission lines are due to both the conductors
and the dielectrics that form the line geometry. The skin effect in conductors manifests itself as resistance and inductance
variations due to the migration of the conduction current toward exterior surfaces. To correctly quantify this effect, three
0018-9375/$26.00 © 2010 IEEE
FAN et al.: SIGNAL INTEGRITY DESIGN FOR HIGH-SPEED DIGITAL CIRCUITS: PROGRESS AND DIRECTIONS
high-frequency physical phenomena need to be taken into account including the crowding of the current at the corner of conductors [9], the proximity effect between traces and/or traces
and reference plane [10], and the surface roughness of conductors [11]. Although several formulas are available in the literature to calculate the skin-effect frequency-dependent resistance
and inductance [12]–[14], it should be noted that the crowding
and the proximity effects cause the direct calculations of the
internal inductance from the high-frequency resistance using
Wheeler’s rule [6] to be inaccurate. Therefore, they should be
computed separately. Furthermore, the square root of frequency
dependence (typical for conductors with a circular cross section) is no longer valid, and more accurate modeling should be
performed. As discussed earlier, high-frequency signals experience increased series resistance at high frequencies due to the
migration of the current toward the conductor outer surfaces.
The formulas to account for this loss, however, are derived on
the assumption of perfectly smooth metal surfaces. In reality,
the metal surfaces are rough, which effectively increases the
resistance when the mean surface roughness is a significant percentage of the skin depth. In recent and advanced experimental
studies [15], it has been found that high-frequency signals traveling on lines with significant surface roughness exhibit losses
that are higher than those calculated with the ideal formulas by
as much as 10% to 50%. Because the roughness pattern is random, it is impossible to predict the skin effect loss exactly. The
roughness of a conductor is usually described as a tooth structure and the magnitude of the surface variations is described as
its tooth size. From a design point of view, the surface roughness
begins to affect the accuracy of the ideal ac resistance equations
when the magnitude of the tooth size becomes significant compared to the skin depth. The ac resistance can be measured, and
an innovative and effective procedure to obtain the portion of the
measured attenuation constant α due to surface roughness was
illustrated in [11]. The challenge in this field is the incorporation
of these effects into practical design tools such as circuit simulators. A significant attempt in this direction was presented in [16].
The frequency-dependent dielectric loss is due to the electric
polarization of the molecules forming the dielectric substrate.
This microscopic phenomenon is described using a macroscopic
damping effect that changes with frequency. The challenges here
are associated with both the experimental characterization and
the modeling of dielectric materials. For experimental characterization, accurate measurement techniques and calibration
procedures are needed [17]. In addition, a statistical approach is
necessary to take care of the unavoidable differences among the
multiple stocks from which the test substrates are built. In terms
of modeling, the dielectric properties extracted from measurements need to be not only accurate but also, more importantly,
passive and causal [18]. Without the fulfillment of both constraints, the model of a dielectric material is useless and when
used in transmission line simulations, it can generate incorrect
and instable results. A procedure for the characterization of
a dielectric material using a genetic algorithm was developed
in [19], which addresses both passivity and causality.
Developing efficient modeling approaches that accurately account for various loss mechanisms and dielectric properties for
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transmission lines is of great need when data rate continues to
increase.
B. Differential Signaling, Imbalance, and Mode Conversion
The use of so-called differential signaling for high-speed signals has become very common in today’s high-speed system
designs. While this signal strategy allows better data quality
and SI at the receive end of long traces, there are some EMC
and SI issues that are not easily apparent [20]–[22]. A significant amount of common-mode signal can be created when the
differential signals have small amounts of in-pair skew, or if
the rise/fall times are slightly different, or the amplitude of the
two traces in the differential pair is slightly different [23]. This
common-mode signal can have a significant impact on the EMC
performance of the system as well as affect the differential SI by
crosstalk onto nearby traces or through mode conversion, where
the common-mode signal becomes a differential-mode noise.
The differential signaling in today’s high-speed designs often uses a pair of complementary single-ended nets. That is,
both traces are driven with respect to the PCB ground reference.
For this reason, these nets should be called “pseudodifferential”. This ground reference, whether on the PCB or within the
application-specific integrated circuit (ASIC) package, is often
imperfect, and may be a power layer or have discontinuities. At
the receive end, the ASIC is usually a true differential receiver,
which only looks for the difference between the two nets, without reference to the PCB (imperfect) ground-reference plane. In
this way, the complementary single-ended nets become differential at the receiver. Since the receiver is only measuring the
difference between the two nets, any common-mode noise is
ignored by the receiver. This provides additional signal quality
and allows longer traces to be used for higher data rates than
the traditional single-ended nets [24], [25]. However, potential
common-mode noise due to imperfect reference, whether on
PCB or on chip, could affect SI through crosstalk or mode conversion as discussed earlier. Thus, these nonideal effects need
to be carefully considered in high-speed designs.
1) Effects of Skew and Other Distortions: Among various
imbalances that are possible in a practical differential pair, skew
between the two complementary traces is a key parameter that
can significantly affect the performance of the differential pair. It
is found that a small amount of differential delay skew does not
affect the differential-mode signal too much. However, it could
result in a significant amount of common-mode noise [26], [27].
Although common-mode noise is more of a concern for EMC,
it could cause SI problems as well if the noise is coupled to the
adjacent traces through crosstalk or through a nonideal return
path.
As mentioned earlier, other differential signal distortions,
such as rise/fall time mismatch and pulse amplitude mismatch
can also create significant common-mode signals. While these
effects are typically slightly less than the in-pair skew effects,
they cannot be corrected on the PCB.
2) Mode Conversion: Whenever there is asymmetry in a differential pair, such as the “ground” pins in a connector or location of “ground” vias near a differential pair, there is some
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IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 52, NO. 2, MAY 2010
Fig. 1. Common-mode to differential-mode conversion due to asymmetric
ground via locations.
amount of differential-mode to common-mode conversion as
well as common-mode to differential-mode conversion. The latter can affect the SI of the differential signal, since any commonmode noise, whether from any of the aforementioned causes, or
from common-mode noise picked up from power distribution
network (PDN) noise between the planes, can potentially increase jitter and decrease the eye opening of the intentional
signal [28].
As an example, a simple four-via structure in a multilayer
PCB is studied with two center vias as differential signal vias
and two outer vias connected to the ground-reference planes.
The right-hand side ground via has a longer distance from the
signal vias than the left-hand side one. The amount of commonmode noise that is converted to the differential mode (|Scd21 |)
is shown in Fig. 1. As the difference in distance increases, the
amount of mode conversion increases until the ground-reference
via is far away from the differential pair and is effectively no
longer part of the circuit.
Often, the symmetry of the ground-reference is ignored, since
the designer is only interested in the differential-mode signal and
spends a lot of effort on the differential-mode loss, reflections,
etc. However, with the common-mode signals created by small
amounts of mismatch in the in-pair skew, rise/fall time mismatch, and/or amplitude mismatch, coupled with the fact that
real-world PCBs often have many via transitions (each with
some amount of mode conversion), significant distortion may
occur to differential signals, especially those with marginal eye
openings due to dielectric and skin effect losses. Therefore, for
high-speed designs, not only the differential but also the common modes need to be carefully considered.
III. DEALING WITH DISCONTINUITIES
In practical high-speed digital circuit designs, discontinuities
are inevitable. At high frequencies, they can cause many SI
problems. Reflection, loss, crosstalk, noise coupling, and mode
conversion could increase significantly in the discontinuity regions [29].
There are various kinds of discontinuities in a signal propagation path at both the PCB and package levels. One of the most
common discontinuities is the via transition. Signal traces are
more often routed through multiple vias, when more components are integrated together and system complexity increases.
This kind of routing is usually more efficient with the tradeoff
between performance and cost. In a signal via transition, both
the impedance and the reference of the trace can change. The
effects of via transitions on SI, as well as modeling approaches,
have been extensively investigated analytically and numerically [30]–[36]. Recently, equivalent circuit models for via transitions that include the distributed behaviors of plane pairs were
proposed using parallel-plane impedances and lumped capacitances in [30] and [31]. A 2-D cavity model combined with the
segmentation technique is used to obtain the multilayer parallelplane impedances. The lumped capacitances can be calculated
from analytical formulas that were derived either based on coaxial line equations [32], or using magnetic frill currents and the
Green’s function for the bounded parallel plate cavity [33].
Besides via transitions, there are many other discontinuities
in a common high-speed PCB or package. As a method of
reducing timing error, meander delay lines have been widely
adopted in critical nets to provide the desired timing delay.
However, crosstalk between the adjacent lines could cause eye
diagram distortion and jitter. These SI consequences were analyzed based on a time-domain even- and odd-mode analysis of a
coupled transmission-line structure in [37]. For bent differential
transmission lines, their SI effects were modeled and a commonmode noise reduction scheme using a shunt capacitance was
proposed in [38]. Today’s highly integrated chip-package-PCB
hierarchical structures also have critical discontinuities such as
the ball grid array and wire-bond connections. A method to
reduce the return loss of bonding wires was proposed using
the comb capacitors attached to the bonding pads [39]. Electromagnetic modeling and analysis of balls with vias in 3-D
packages were discussed in [40]. It was reported that 40-Gb/s
signaling was achievable in the low-cost wire-bonded plastic
ball grid array by employing discontinuity cancellation techniques in both the signal-current and return-current paths [41].
The corresponding design methods for bonding wires, vias, solder ball pads, and PDNs were suggested. In [42], a transition
from a coplanar waveguide to a microstrip with vias, which
is often used in wafer probe measurements, was investigated.
It was demonstrated how the presence and placement of the
vias could affect the bandwidth and alter the impedance of the
transitions. Another major discontinuity category is caused by
nonideal ground references. A thin slot in a ground plane is a
typical case, which could cause undesired effects such as signal
distortion, crosstalk, and radiation. An equivalent circuit model
for this kind of geometry using a gap voltage source was developed in [43]. In [44], a generalized partial-element equivalentcircuit method was proposed for modeling a planar circuit with
a thin narrow slot in the ground plane [45]. The reduction in the
slot-induced ground bounce noise by using differential signaling
was also investigated with a 2-D finite-difference time-domain
method in [46].
In the discontinuity regions, behaviors are dominated by
higher order electromagnetic modes. Thus, they are often characterized as an S-parameter network obtained either from modeling or measurements. To incorporate the discontinuity models
FAN et al.: SIGNAL INTEGRITY DESIGN FOR HIGH-SPEED DIGITAL CIRCUITS: PROGRESS AND DIRECTIONS
with other components for a time-domain simulation, it is often
preferred to extract an equivalent simulation program with integrated circuit emphasis (SPICE) model from the S-parameter
network. A popular method to do so is the pole-residue approach, which can be very effective and accurate for analyses,
if the S parameters are good in quality (causal and passive).
However, for designs and optimizations, a physics-based equivalent circuit model, where every circuit component is related to
some geometrical dimensions, has more advantages, since it has
a one-to-one relationship to geometry, and thus, could provide
a direct and intuitive physical understanding.
The future directions of discontinuity modeling include the
development of effective approaches for model extraction,
macromodeling with causality and passivity enforcement, and
efficient models that can be easily integrated into circuit simulators.
IV. SI MEASUREMENT TECHNIQUES
Various kinds of measurements are performed in both the time
and frequency domains for SI. Although digital circuits are of
interest, behavior at high frequencies up to the microwave range
is needed due to the high speed of the signals in the circuits.
Therefore, a good portion of SI measurements involves accurate characterization of passive components in the frequency
domain using a vector network analyzer (VNA). A challenge
particularly critical in these SI measurements is to properly account for the effects of test fixtures, since most of the digital
circuits in PCBs or packages are not coaxial and test fixtures
are usually necessary. To reduce the effects of connectors, a
probing station is sometimes used at both the PCB and package levels. In addition, to accurately quantify crosstalk among
traces, four-port measurements with true four-port calibration
are often needed. In some applications, multiport measurements
with more than four ports may be needed for crosstalk between
differential pairs. A lot of research work has focused on improving VNA measurement techniques. Coupled transmission
lines have been experimentally characterized using four-port Sparameter measurements up to 20 GHz in [47]. An analytical
methodology for characterizing electrical transitions associated
with transmission line-based microwave channels was presented
in [48]. Several deembedding standards and a statistical parameter estimation technique were studied in [49] to achieve more
accurate measurement results. In [50], the parameters of transmission lines embedded in multilayer PCBs were measured up to
18 GHz based on a mathematical error-removal scheme using
two different length transmission lines and a via–hole structure
that minimizes coupling.
Since transmission lines are widely used in high-speed digital
circuits, quantifying transmission line parameters (propagation
delay and characteristic impedance), impedance matching, and
discontinuities are necessary for SI designs. In addition to the
frequency domain VNA measurements, time-domain reflectometry (TDR)/time-domain transmission measurements are also
widely employed, since they are simple to use and can provide straightforward information. Although the dynamic range
of time-domain instruments is much smaller than frequency-
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domain ones, they are more commonly used in manufacturing
floors due to the cost consideration. A method has been developed to perform network analysis using TDR measurements including time-domain through-reflection-line (TRL) calibrations
for this exact purpose [51].
Another set of SI measurements target the performance of
the overall high-speed link and system interface. These measurements may involve a few different instruments including an
oscilloscope, bit error rate tester, jitter analyzer, and spectrum
analyzer [52]–[54]. Accurate modeling and characterization of
the timing jitter introduced by the clocking network, transmitter, receiver, and the transmission media is essential, as the data
rate of the chip-to-chip communication increases. Jitter can be
measured and decomposed into different components that are
directly related to certain noise mechanisms using an oscilloscope or signal analyzer with jitter analysis capabilities. The
receiver jitter, sensitivity, and bandwidth are related, and they
affect the bit error ratio (BER) of a high-speed link. Various measurements have been demonstrated for measuring the I/O link
performance. A 16-Gb/s bidirectional asymmetrical memory interface was characterized, and on-chip measurements were used
to complement the off-chip instrumentation [55]. Measurements
of electrical on-board module-to-module links were performed
with a per-channel data rate of up to 11 Gb/s utilizing a 16channel link chip with a programmable equalization in [56].
On-chip measurement circuitries were also implemented to diagnose and optimize the performance of the link. Two circuits
for data jitter measurements were implemented with a 0.11 µm
CMOS process and demonstrated in [57].
Improving VNA measurements continues to be a focus of the
future research in this area. True differential TRL calibration
techniques are of great interest when the test fixtures themselves
are coupled networks. Accurate time-domain network analysis
techniques are also highly desirable, especially for manufacturing floor, where TDRs are more popular than VNAs. In jitter measurements, jitter decomposition algorithms need to be
further improved so that the results from different scopes can
correlate better.
V. LINK-PATH ANALYSIS AND DESIGN
A link path starts at a transmitter on a silicon substrate, ends at
a receiver on another silicon substrate, and may include siliconto-package interconnects, interconnects in packages and PCBs,
package-to-PCB interconnects, as well as connectors and cables.
The performance of the link path directly determines the bit error
rate of the data communication between the transmitter and the
receiver [58]–[61]. Hence, link-path analysis and design is a
critical area in SI. Among various link path issues, equalization,
modulation, and jitter analysis are focused in this section, as
they are the most critical parts in today’s link-path analysis and
design.
A. Equalization
Equalization is emerging as a critical design technique to
achieve the ever-increasing data rate speeds in computer or
communication systems. There are various equalization designs
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Fig. 2.
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 52, NO. 2, MAY 2010
Multitap FIR equalizer.
Fig. 4.
Fig. 3.
IIR equalizer.
available [62], [63], but the basic idea is to compensate the signal distortion caused by the link path, also called as a channel,
between the transmitter and the receiver.
Intersymbol interference (ISI) is one of the major contributors
to the signal degradation through a channel, which is typically
nonideal and its frequency response is band-limited mainly due
to losses and reflections. Passing a signal through such a channel
results in frequency-dependent attenuation. This filtering of the
transmitted signal affects the shape of the pulse that arrives at
the receiver.
Equalization is the most common approach to mitigate ISI.
From the frequency-domain perspective, equalization helps
compensate the low-pass filtering characteristics of the channel by increasing the high-frequency components of the transmitted signal while lowering the low-frequency ones. From a
time-domain perspective, equalization minimizes the amplitude
of the pulse response that spreads out of its ideal position and
interferes with other symbols [64], [65].
1) Feed-Forward Versus Feed-Backward Equalization:
Finite-impulse response (FIR) filters are generally used for
transmitter deemphasis [62], [66], a common form of equalization. Fig. 2 illustrates a general N-tap FIR equalizer that can
compensate the ISI that spreads N bits before or after the ideal
response position. It should be noted that an FIR equalizer could
be implemented at either the transmitter or the receiver side, as
for most other equalization schemes.
The FIR equalizer illustrated in Fig. 2 is a feed-forward system. This is in contrast to an infinite-impulse response (IIR)
equalizer, which is a feed-backward system as shown in Fig. 3.
An FIR filter is usually more preferable to an IIR, since it is
inherently stable and does not require feedback. One main disadvantage of an FIR filter is that it requires more computational
power.
Although a traditional IIR filter as shown in Fig. 3 is not
popular in high-speed systems, an improved one with a decisionfeedback block (see Fig. 4) is very popular. This type of filter
is typically called a decision-feedback equalizer (DFE). If the
Typical DFE.
values of the symbols previously detected are known, the ISI
contributed by these symbols can be canceled out exactly at the
output of the DFE filter by subtracting the past symbol values
with appropriate weighting. The tap weights (K1, K2, K3, etc.)
can be adjusted simultaneously to fulfill a criterion such as
minimizing the mse.
2) Continuous Time-Domain Versus Discrete-Time Equalization: The equalization schemes described earlier are in the
discrete time domain, while the implementation can be done in
the continuous time domain as well [67]. The transfer function
of this kind of passive equalizer is a high-pass filter. It is often
seen in cables. In IC applications, active circuitry can be added
to boost the gain of the transfer function, or add peaking of
transfer frequency in the needed frequency range [68], [69].
3) Adaptive Equalization: To account for the variations in
channel performance, such as transmission line variations due
to manufacturing tolerance, environmental impact, and effects
of connector/socket, etc., equalization settings are preferred to
be adaptive for optimal performance. Examples of equalization
settings include tap coefficients in an FIR or IIR filter, or values
of the circuit components used in a passive equalizer.
The most widely used adaptation criterion is the mse calculated between the recovered signal and the training data in
the time domain at sampling points. The LMS algorithm or
its variations such as the sign–sign LMS are the most popular [70]–[72]. Another method is to obtain the error signal by
sampling the equalizer output waveform, and then, analyzing its
characteristics in the time domain [73], [74]. Alternatively, the
error signal can also be obtained from the statistical spectrum
information [63], [75].
Adaptive equalization is typically implemented at the receiver. To implement adaptive equalization at the transmitter, a
feedback mechanism to the transmitter is needed that can complicate the system design, since the feedback has to go through
the entire channel.
B. Modulation
In current state-of-the-art high-speed link design, modulation
techniques as well as equalization techniques are exploited.
Typical equalization techniques have to provide compensation for the frequency spectrum of the entire nonreturn to zero
(NRZ) data bandwidth. As data rate increases, the roll-off of
the channel frequency response is severe, and the discontinuity
of the channel (such as use of vias, connectors, and sockets,
etc.) may become severe in the frequency range of interest.
FAN et al.: SIGNAL INTEGRITY DESIGN FOR HIGH-SPEED DIGITAL CIRCUITS: PROGRESS AND DIRECTIONS
An alternative solution is to reduce the bandwidth of transmitted signal using multilevel coding or modulation. Duobinary
and PAM4 signals are among the most commonly used approaches [76]–[79].
The key feature of PAM4 and duobinary signals is that their
signal spectra are exactly a half of that of the NRZ data. In other
words, the bandwidth requirement of the channel is narrower,
which means less attenuation and distortion to the signal. However, due to multilevel signaling, the signal is more susceptible
to noise, so the SNR performance has to be sacrificed. They are
also harder to implement, and consumes more power compared
to the standard NRZ signaling. Generally speaking, duobinary
does not incur nearly as much SNR penalty as PAM4, and it is
easier to implement [78].
More research is needed to further understand the performance difference in real silicon design using different signaling
techniques. In [79], design and comparison of the three techniques, NRZ, PAM4, and duobinary, were reported for a 20-Gb/s
backplane link and it was shown that NRZ signaling has the best
BER performance.
C. Jitter Analysis
Jitter is the deviation of the significant edges in a sequence
of data bits from their ideal timing positions. It can cause the
receiver to fail in decoding the signal correctly. Jitter is a significant, and usually undesired, factor in the design of almost all
communications links.
Jitter is often characterized by two generalized types, deterministic jitter (DJ) and random jitter (RJ). DJ is caused by
nonGaussian events. It is always bounded in amplitude and has
specific causes. Examples of DJ include duty cycle distortion,
data-dependent jitter, jitter caused by power supply noise, coupling between two signals, spread spectrum clocking, etc. RJ is
the component that is Gaussian in nature. One example of RJ is
the thermal noise in a circuit [80], [81].
1) Peak Distortion Analysis (PDA): In recent years, PDA
has become a popular method to quickly determine the worst
case eye diagram of the link [82], [83]. The worst case voltage
magnitude at any given sampling point can be directly calculated
from the unit pulse response. In other words, the worst case eye
opening due to ISI can be almost instantaneously calculated for
the unit pulse response without having to run any additional
simulation.
Although PDA analysis is a computationally efficient approach to include ISI and crosstalk impact, it does not include
the transmitter and receiver jitter. In the full-link PDA analysis, silicon jitter and channel ISI/crosstalk need to be calculated
separately, and meet their individual design budgets.
2) Statistical BER Analysis: As mentioned earlier, PDA
analysis does not take into account the interaction of the transmitter/receiver jitter with the channel ISI. Another critical disadvantage of PDA is that the BER of the link is not available.
If the channel memory is long, the worst case bit pattern can
consist of an excessive number of bits, and the probability of
sending the exact sequence of the worst case bits is close to zero.
Designing for the worst case eye often results in an overdesign.
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A general framework of statistical BER analysis was introduced in [78], where, given the pulse response from an accurate channel model including crosstalk, transmitter and receiver
sampling distribution, and receiver sensitivity, BER can be determined analytically. The key to this statistical BER analysis
is to represent all interference sources with probability density
functions, and then, convolute them.
Further progress on the statistical BER analysis was achieved
in [84] and [85]. In [86], the methodology was enhanced to
include the transmitter jitter amplification through the channel. In other words, the transmitter jitter distribution cannot be
convoluted directly with the channel ISI and the receiver jitter
distributions, since the transmitter jitter can be distorted or amplified after passing through the channel. A rigorous method was
developed in [86] to take this phenomenon into account. Furthermore, in [87] and [88], new general formulations to model
the white and the colored bounded jitter were introduced.
3) Time-Domain Jitter and BER Analysis: One disadvantage of the statistical jitter and BER analysis is that timedomain waveforms are not available, since the eye diagram
is constructed based on the probability density functions only.
Furthermore, since all the interference sources are characterized with probability density functions, the correlation of each
source is not accounted for. For example, sinusoidal jitter or
duty cycle distortion cannot be accurately captured, because the
cycle-to-cycle relationship of the jitter sequence is totally lost
when their behavior is represented by their probability density
functions [89].
Time-domain empirical jitter analysis overcomes the disadvantages of the statistical analysis, by analytically constructing
the time-domain waveforms through convolution of superposition. In [90], a flexible and efficient method was proposed
for BER simulation using efficient time-domain interpolation
and superposition. It uses the step response of the channel,
and directly converts the bit sequence to the data stream in
the time domain and extracts the jitter distribution from the
actual reference-crossing points. The method is flexible with
coding schemes and capable of adding any correlated or uncorrelated transmitter or receiver jitter. The disadvantage of
this approach is that low BER performance of the link has to
be extrapolated, since it is computationally intensive to construct 10e12 (or more) bits of waveforms. However, there
exist various types of BER extrapolation methodologies. A
good summary of the extrapolation techniques can be found in
[91].
4) Special Note on Nonlinearity and Jitter Analysis: The
jitter analysis approaches mentioned earlier can accurately simulate system jitter performance only when the system is linear
time invariant (LTI) or can be well approximated as an LTI
system. For a nonLTI system, one cannot construct waveforms
based on impulse or pulse response, and the aforementioned fast
jitter analysis approaches will result in errors. There are techniques to resolve some specific nonLTI issues. In [92], a novel
algorithm was introduced using the superposition of multiple
edge responses to construct waveforms for different data patterns, which can account for nonlinearities that extend beyond
one bit as well as asymmetric rising and falling edges. With this
398
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new algorithm, the jitter analysis approaches become applicable
again.
A problem that remains in link-path analysis and design is the
lack of a meaningful parameter that can directly relate the linkpath behaviors to signal performance quantitatively. A lot of
research work is targeting this issue. Including nonlinear effects
and various noise-coupling mechanisms into consideration is
also a popular direction. Further improvements in jitter and
BER analysis methods are desirable as well.
VI. CONCLUSION
Recent progress and future directions in SI design for highspeed digital circuits have been reviewed in this paper. As technology evolves, SI, as an integral part of the design process for
high-speed digital circuits, will continue being developed and
to grow into new territories. In addition, it will become increasingly critical to codesign SI, power integrity, and EMC, in order
to achieve the design objectives of high quality, low emission,
cost reduction, as well as reduced time to market.
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Jun Fan (S’97–M’00–SM’06) received the B.S. and
M.S. degrees from Tsinghua University, Beijing,
China, in 1994 and 1997, respectively, and the Ph.D.
degree from the University of Missouri-Rolla, Rolla,
in 2000, all in electrical engineering.
During 2000–2007, he was a Consultant Engineer at NCR Corporation, San Diego, CA. In July
2007, he joined the Missouri University of Science
and Technology (formerly University of MissouriRolla), where he is currently an Assistant Professor
in electromagnetic compatibility (EMC) Laboratory,
Missouri University of Science and Technology, Rolla. His research interests
include signal integrity and electromagnetic interference (EMI) designs in highspeed digital systems, dc power-bus modeling, intrasystem EMI and RF interference, printed circuit board noise reduction, differential signaling, and cable/connector designs.
Dr. Fan was the Chair of the IEEE EMC Society TC-9 Computational Electromagnetics Committee during 2006–2008, and a Distinguished Lecturer of
the IEEE EMC Society during 2007–2008. He is currently the Vice Chair of
the Technical Advisory Committee of the IEEE EMC Society. He received an
IEEE EMC Society Technical Achievement Award in August 2009.
Xiaoning Ye (S’97–M’01) received the Bachelor’s
and Master’s degrees from Tsinghua University,
Beijing, China, in 1995 and 1997, respectively, and
the Ph.D. degree from the University of MissouriRolla (currently Missouri University of Science
and Technology), Rolla, in 2000, all in electrical
engineering.
He has been a Senior Hardware Engineer at Intel Corporation, Hillsboro, OR, since his graduation,
where he is involved in ensuring signal integrity of
high-speed differential signaling in server platforms,
providing platform design guidelines, and research and development of next
generation multi-Gb/s bus interfaces, etc. He was also engaged in research
and development of electromagnetic compatibility solutions for enterprise platforms. He holds three patents and several patent applications in the areas of
high-speed signaling.
Jingook Kim (M’09) received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from
Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2000, 2002, and 2006,
respectively.
He was involved in power/signal integrity, package modeling in gigahertz systems, as well as electromagnetic interference/electromagnetic compatibility
(EMC) design. From 2006 to 2008, he was a Senior
Engineer at Memory Division, Samsung Electronics, where he was engaged in high-speed I/O circuit
designs, focusing on power and signal integrity. Currently, he is at Missouri
University of Science and Technology, Rolla, where he joined the EMC Laboratory in 2009 as a Postdoctoral Research Fellow. His research interests include
power distribution network modeling and design at the chip/package/printed
circuit board levels, IC EMC, and RF interference.
Bruce Archambeault (M’85–SM’99–F’05) received the B.S.E.E degree from the University of
New Hampshire, Durham, in 1977, the M.S.E.E degree from Northeastern University, Boston, MA, in
1981, and the Ph.D. degree from the University of
New Hampshire, in 1997.
His doctoral research involved the computational
electromagnetics applied to real-world EMC problems. Currently he is an International Business Machines Corporation (IBM) Distinguished Engineer at
IBM, Research Triangle Park, Durham, NC. He has
authored or coauthored a number of papers in computational electromagnetics,
mostly applied to real-world EMC applications, and the books PCB Design for
Real-World EMI Control and EMI/EMC Computational Modeling Handbook.
Dr. Archambeault is currently the Chair of IEEE EMC Society Technical
Activities. He was a Member of the Board of Directors for the IEEE EMC
Society and a Member of the Board of Directors for the Applied Computational
Electromagnetics Society. He was a IEEE/EMCS Distinguished Lecturer..
Antonio Orlandi (M’90–SM’97–F’07) was born in
Milan, Italy, in 1963. He received the Laurea degree
in electrical engineering from the Sapienza University of Rome, Rome, Italy, in 1988.
From 1988 to 1990, He was with the Department of
Electrical Engineering, Sapienza University of Rome.
Since 1990, he has been with the Department of Electrical Engineering, University of L’Aquila, L’Aquia,
Italy, where he is currently a Full Professor at the UAq
EMC Laboratory. He has authored or coauthored
more than 190 technical papers in the field of electromagnetic compatibility in lightning protection systems and power drive systems
published in various international journals and conferences. His Current research
interests include numerical methods and modeling techniques to approach signal/power integrity, electromagnetic compatibility (EMC)/electromagnetic interference (EMI) issues in high-speed digital systems.
Dr. Orlandi received the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY Best Paper Award in 1997, the IEEE EMC Society Technical
Achievement Award in 2003, the IBM Shared University Research Award
(2004, 2005, and 2006, respectively), the Computer Simulation Technology
(CST) University Award in 2004, and the IEEE EMC Symposium Best Paper Award in 2009. He is a Member of the Education, TC-9 Computational
Electromagnetics and the Chairman of the TC-10 Signal Integrity Committees
of the IEEE EMC Society, the Chairman of the “EMC and Signal Integrity at
PCB level” Technical Committee of the International Zurich Symposium and
Technical Exhibition on EMC. He has been an Associate Editor of the IEEE
TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY and the IEEE TRANSACTIONS ON MOBILE COMPUTING.