Volume 48, Number 1, 2007
27
Power Factor Correction Converter
with Auxiliary Switch
Nicolae DRĂGHICIU, Daniel ALBU, Dan George TONŢ
and Gabriela TONŢ
Abstract - For lower-power, cost-sensitive applications, the single-stage power factor correction
approach may be more attractive. The proposed technique improves the input power factor, reduces the
stress on the energy-storage capacitor, and improves the overall efficiency. In this paper, an improved
single-stage power factor correction technique which employs an auxiliary switch is presented.
Keywords: single-stage power factor correction
1. INTRODUCTION
In all electronic equipment the power
supply plays an important role even though the
power supply typically has nothing to do with
the primary function of the equipment. The
most commonly used ac/dc power supply
configuration
(bridge-rectifier
+
filter
capacitor) is affected by the new norm, forcing
the manufacturers to pay attention to the way
that the ac/dc conversion is performed.
Conventional power converters with diode
capacitor rectifier front-end have distorted
input current waveform with high harmonic
content. Typically, these converters have a
power factor lower than 0,65. The active PFC
converters can be implemented using either the
two-stage approach or the single-stage
approach. The two-stage approach (fig. 1) is
the most commonly used approach. In this
approach, an active PFC stage is employed as
the front-end to force the line current to track
the line voltage. Additionally, the PFC stage
establishes a loosely regulated high-voltage dc
bus at its output, which serves as the input
voltage to a conventional dc/dc stage with a
tightly regulated output voltage. While the
two-stage approach is a cost-effective
approach in high-power applications, its costeffectiveness is diminished in low power
applications due to the additional PFC power
stage and control circuit. A low cost alternative
solution to this problem is to integrate the
active PFC input-stage with the isolated dc/dc
output stage However, unlike in the two-stage
approach the dc voltage on the energy-storage
capacitor in a single-stage PFC converter is not
regulated. As a result, in universal-line
applications (90 – 260 Vac), the energystorage-capacitor voltage varies with the load
and line. This increases the ratings, size, and
cost of the components, and it also reduces the
overall efficiency.
2. REVIEW OF TWO POWER FACTOR
CORRECTION APPROACHES
The generalized structure of the two-stage
power factor correction converters is shown in
Figure 1.
Figure 1. Conceptual structure of the two-stage PFC
converter.
In this approach, there are two
independent power stages. The front-end PFC
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ACTA ELECTROTEHNICA
stage is usually a boost or buck/boost (or
flyback) converter. The boost converter frontend consists of a boost inductor, boost switch,
and rectifier. The PFC controller senses the
line voltage waveform and forces the input
current to track the line voltage to achieve the
unit input power factor. Since the voltage V1,
of energy-storage bulk capacitor C1, is loosely
regulated, V1 is a dc voltage which contains a
small second order harmonic. This bus voltage
is typically regulated at around 380 V dc in the
entire line input voltage range from 90 to 260
Vac. The high bus voltage V1 minimizes the
bulk capacitor C1 value for a given hold-up
time. In addition, the narrow-range-varying V1
improves the efficiency of an optimized dc/dc
output stage.
The dc/dc output stage is the isolated
output stage that is implemented with at least
one switch, which is controlled by an
independent PWM controller to tightly
regulate the output voltage.
Figure 2(a) shows the input current and
voltage waveforms of a two-stage PFC
converter, whereas Fig. 2(b) shows the dutycycle variations of the front-end PFC stage and
the dc/dc output stage during a rectified-line
cycle. Since the input and output voltage of the
dc/dc converter are constant, the duty cycle of
the dc/dc converter, ddc/dc, is also constant, as
shown in Fig.2(b).
Figure 3. CCM boost PFC front-end with forward
output stage.
Generally, the hold-up time is the time during
which a power supply needs to maintain its
output voltages within the specified range after
a dropout of the line voltage. This time is used
to orderly terminate the operation of a
computer or to switch over to the
Uninterruptible Power Supply operation after a
line failure. For example, the majority of
today’s desktop computers and computer
peripherals require power supplies that are
capable of operating in the 90-260 Vac range
and can provide a hold-up time of at least 10
ms. The required energy to support the output
during the hold-up time is obtained from a
properly sized energy-storage capacitor C1.
The rating of the hold-up capacitor
significantly impacts the total size and cost of
power supply. Generally, capacitance C1 is
determined by equation (1), where V1-90 is the
low line full-load capacitor voltage, and V1-min
is the minimum designed capacitor voltage. P0max is the maximum output power, thold is the
hold-up time, and ηdc is the forward stage
efficiency.
2
C1 =
Figure 2. Ideal waveforms of the two-stage PFC
converter: (a) rectified input voltage and current;
(b) duty cycle of the PFC and DC/DC switches.
Figure 3 shows the circuit diagram of the
two-stage PFC converters consisting of a CCM
boost PFC converter as the front-end stage and
a forward converter as the dc/dc output stage.
In a majority of computer-related applications
a hold-up time is a very important requirement.
P0 _ max
η dc
.t hold
2
2
V1 _ 90 − V1 _ min
(1)
3. SINGLE-STAGE PFC CONVERTER
WITH A LOW -FREQUENCY
AUXILIARY SWITCH
In order to reduce the component count
and improve the performance, a number of
single-stage, single switch PFC techniques
have been introduced recently [3], [4], [5]. In a
single-stage, single switch PFC converter,
input current shaping, isolation, and tight
Volume 48, Number 1, 2007
regulation of outputs are achieved in a simple
single conversion step with only one switch.
According to the shape of the input inductor
current, the single-stage, single switch PFC
circuits can be classified as discontinuouscurrent-mode (DCM) and continuous currentmode (CCM) single-stage, single switch PFC
converters.
The discontinuous-current-mode singlestage, single switch PFC converters normally
have fewer components than the continuous
current-mode single-stage, single switch PFC
converters, but they suffer from a higher
current stress, lower efficiency, and require
larger EMI filters. As a result, in many
applications, the continuous current-mode
single-stage, single switch PFC converters are
preferred over the discontinuous-current-mode
single-stage, single switch PFC converters.
Figure 4 shows a typical discontinuouscurrent-mode single-stage, single switch PFC
converter. In the circuit in Fig. 4, inductor L1
is the boost inductor which shapes the input
current to meet the required harmonic-current
standard.
Figure 4. Discontinuous-current-mode single-stage
single switch PFC converter.
Switch S integrates the discontinuouscurrent-mode single-stage, single switch PFC
converters and the output dc/dc converter into
one stage. The tapped winding N1 is the
feedback winding used to limit the voltage
stress on energy-storage capacitor C1 and to
improve the overall efficiency. Generally, a
higher N1 reduces the voltage stress of the
semiconductor components and capacitor C1,
and improves efficiency. However, a larger N1
also decreases the conduction angle of the line
current and, consequently, increases the linecurrent harmonics. To meet PFC requirements
in a continuous current-mode single-stage,
29
a)
b)
Figure 5. Discontinuous-current-mode single-stage,
single switch PFC converter with tapped primary
winding.
single switch PFC converter, the auxiliary
inductor L3, shown in Fig. 5(a), is required.
As can be seen in Fig. 5(b), when the line
voltage is close to the zero crossings, the boost
inductor L1 operates in the discontinuous
current-mode, and i(L1) is very low. For
higher instantaneous line voltages, the boost
inductor L1 operates in the continuous currentmode mode, and the i(L1) waveform shows a
fast rise of i(L1). This paper introduces a new
technique which improves the performance of
the continuous current-mode single-stage,
single switch PFC converter.
The technique employs a low-frequency,
low-cost, and low-loss auxiliary switch to
extend the conduction angle of the line current
without a need to decrease N1. As a result, in
the improved circuit the required reduction of
the line-current harmonics can be achieved
without sacrificing the conversion efficiency.
Specifically, to reduce the voltage stress
on the energy-storage capacitor, as well as to
maximize the conversion efficiency, N1 should
be maximized. However, to meet the linecurrent harmonic specifications with a
desirable margin, N1 should be minimized.
Unfortunately, these two diametrically
opposed requirements cannot be met without a
major modification of the circuit. As can be
seen from Fig. 5(b), to reduce the line current
30
ACTA ELECTROTEHNICA
distortion, it is necessary to increase the
current around the zero crossings; i.e., it is
necessary to eliminate the dead angle of the
current. With the dead angle eliminated, the
line-current peak will be reduced and,
therefore, a lower THD will be achieved. To
eliminate the dead angle in the presence of an
optimally selected N1, it is necessary to
modify the converter by adding an auxiliary
switch as shown in Fig. 6(a).
In Fig. 6(a), switch S is the main power
switch, whereas Sr is the auxiliary switch,
which serves to improve the line-current
waveform by eliminating the dead time of the
line current. During each half line cycle when
the instantaneous line voltage is around the
zero crossings, Sr is turned on to disable the
tapped winding N1 and, thus, eliminate the
dead angle. Figure 7 shows the synthesis of the
timing waveform of the auxiliary switch Sr.
The turn-on signal for Sr is generated by the
comparator, which compares scaled, rectifiedR2
line voltage
.Vin with reference
R1 + R 2
voltage Vref. When the scaled, instantaneous,
rectified-line voltage is lower than the
reference voltage, which occurs around the
zero-crossings of the line voltage, Sr is turned
a)
on to bypass tapped winding N1. Otherwise,
auxiliary switch Sr is turned off so that
winding N1 actively participates in reducing
the energy storage-capacitor voltage and in
providing the energy transfer from the input to
the output for maximum efficiency.
Figure 7. Synthesis of duty cycle “d” of auxiliary
switch Sr.
The auxiliary switch Sr is a small, lowcurrent rated switch because it only conducts
current around the zero crossings of the line
voltage. In addition, Sr power dissipation is
also very low because its conduction loss, as
well the switching loss, is negligible since Sr
carries a very small current and switches at
twice of the line frequency. As shown in Fig.
6(a) the implementation of the control for Sr is
simple, too. It requires only a comparator and a
small number of passive components (resistors
and capacitors) since the reference dc voltage
can be derived from the energy-storagecapacitor voltage.
Furthermore, Sr does not require an
isolated gate drive because it only needs to be
turned on when S is on. Therefore, the
additional cost of the proposed circuit is
relatively small.
Figure 8 shows the maximum energy-storage
capacitor voltage of the three implementations
as a function of the line voltage. The proposed
circuit with the auxiliary switch exhibits the
lowest maximum voltage stress of 390 V dc,
which allows a safe use of a 450-Vdc rated
energy-storage capacitor.
4. IMPLEMENTATION VARIATIONS
b)
Figure 6. Conceptual circuit diagram of improved
continuous current-mode single-stage single switch
PFC converter with auxiliary switch Sr.
The described concept with the auxiliary
switch can be implemented in a variety of
ways.
Volume 48, Number 1, 2007
Figure 8. Maximum energy-storage-capacitor C1
voltage stress.
For example, Fig. 9(a) show the
implementation which uses the proposed
approach to disable auxiliary inductor L3
instead of disabling winding N1. While the
disabling of L3 increases the current in the
DCM region around the zero crossings of the
line voltage, this approach does not eliminate
the dead angle.
a)
31
Yet another implementation of the
proposed concept is shown in Fig. 9 (b). In this
implementation, both L3 and N1 are disabled
around the zero crossings of the line voltage.
This approach eliminates the dead angle
completely and increases the line current in the
DCM regions even more than the circuit in
Fig. 7.
As a result, the circuit in Fig. 9 (b) has a
lower THD than the THD in the circuit in Fig.
5 (b).
5. REFERENCES
1. Dan Lascu -„Tehnici şi circuite de corecţie activă a
factorului de putere” Editura de Vest, Timişoara
2004;
2. Viorel Popescu -„Stabilizatoare de tensiune în
comutaţie” Editura de Vest, Timişoara, 1992;
3. J. Qian, Q. Zhao, F. C. Lee -„Single-Stage SingleSwitch Power Factor Correction AC/DC Converters
with DC Bus Voltage Feedback for Universal Line
Applications,” IEEE Applied Power Electronics
Conf. (APEC) Proc. 1998. pp. 223-229
4. L. Huber; Milan M. Jovanovic – “Single–Stage,
Single-Switch Input-Current-Shaping Technique
with Reduced Switching Loss”- IEEE Applied
Power Electronics Conference (APEC), 1997;
5. L. Huber; M. M. Jovanovic – “Design optimization
of single stage, single-switch input-current shapers”
IEEE Power Electronics Specialists Conference
(PESC) Rec., pp. 519-526, Jun. 1997.
Nicolae DRĂGHICIU
Daniel ALBU
Dan George TONŢ
Gabriela TONŢ
b)
Figure 9. Implementation variations: (a) Disabling
of L1; (b) Disabling of L1 and N1.
University of Oradea,
Universităţi Str., No. 1
410087, Oradea, Romania