Back Gate Voltage and Buried-oxide Thickness Influences on

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Silicon-On-Insulator (SOI) technology has been
intensively investigated due to its advantages such as
higher mobility, transconductance and integration
density. When the temperature is reduced, some of
these characteristics are even improved, e.g. the
mobility and the subthreshold slope [1]. However,
series resistance (Rseries) is an intrinsic problem in SOI
devices due to the small silicon film thickness, and this
problem becomes more critical when the temperature is
reduced [2].
The influence of the back gate voltage on the
series resistance becomes appreciable mainly at low
temperatures and with thin buried oxides. Some
extraction methods have used the back interface
conditions (depletion and/or accumulation) to extract
electrical parameters. The influence of the back gate
voltage on the series resistance is normally negligible.
The goal of this work is to verify the influences of the
back gate voltage and buried oxide thickness on the
series resistance extraction at low temperatures.
The LDD (Lightly Doped Drain) fully depleted
SOI nMOSFET's were simulated by MEDICI [3] with
drawn channel width (Wm) of 20 µm and different
drawn channel lengths (Lm) of 0.6, 0.8, 1.0, 1.2, 1.6,
and 2.0 µm. A gate oxide thickness (toxf) of 15 nm,
buried oxide thickness (toxb) of 80 and 400 nm, silicon
film thickness (tsi) of 80 nm and a substrate doping Na
= 1x1017 cm-3 were used in the simulations. The front
channel characteristics (Ids x Vgs) were simulated for
different back gate voltages (Vgb) and different
temperatures.
The series resistance Rseries was obtained from
Ids x Vgs curves using the technique proposed by G. J.
Hu [3] for different overdrive voltage (Vgs - Vth) to
reduce the influence of the device geometry. Figure 1
shows the results of the series resistance change ∆R,
defined in Eq. (1), as a function of the back gate bias
Vgb for toxb equal to 80 and 400 nm, for (Vgs - Vth) =
2.45 V, at 77 K.
(
)
(
(
)
)
R
V ≠ 0 − R series V gb = 0 


 series gb

∆R =
x100
R

V
=
0


 series gb

(1)
As can be observed, ∆R is significantly influenced
by the back gate voltage mainly with toxb = 80 nm.
Figure 1 also shows that for Vgb < - 15 V, ∆R
becomes almost constant for toxb = 80 nm.
When the back gate bias becomes more negative,
the depletion region of the back interface inside the
140
LDD SOI nMOSFET - T = 77 K
120
100
∆R [%]
Aparecido S. Nicolett
[email protected]
Ph.D. Research
(Adivisor: Prof. Dr. João A. Martino)
LDD region increases and the series resistance also
increases due to the reduction of the film neutral
volume available for conduction [5]. For Vgb = - 15 V,
the back interface below the LDD region is inverted
and the depletion region reaches its maximum value.
This can explain why the series resistance changes
hardly for
Vgb < - 15V.
toxb = 400 nm
toxb = 80 nm
80
60
40
20
0
-20
-35
-30
-25
-20
-15
-10
-5
0
5
Vgb [V]
Figure 1: Variation of the series resistance as a
function of the back gate bias at 77 K.
Figure 2 shows the influence of the temperature
on ∆R. It can be seen that the influence of the back gate
voltage is higher when the temperature is reduced, once
the maximum depletion is larger in this case due to the
reduction of the effective LDD concentration.
120
LDD SOI nMOSFET
Vgb =
Vgb =
Vgb =
Vgb =
Vgb =
Vgb =
Vgb =
100
80
∆R [%]
Back Gate Voltage and Buried-oxide Thickness
Influences on the Series Resistance of Fully
Depleted SOI MOSFETs at 77 K
60
-
0V
5V
10 V
15 V
20 V
25 V
30 V
40
20
0
150
200
250
300
T [K]
Figure 2: Influence of the temperature on ∆R for
different back gate voltages with toxb = 80 nm.
Conclusion:
When the back gate bias is decreased the series
resistance increases until the back interface below the
LDD region reaches inversion. In this condition, the
depletion region depth is maximum and the series
resistance becomes practically constant. This effect
becomes more pronounced when thin buried oxides
and low temperature are used.
References:
[1] F. J. Garcia Sanches, A. Ortiz-Conde, M. Garcia Nunes,
R. L. Anderson, Solid State Electronics, vol. 37, No. 12, pp.
1943, 1994.
[2] F. Balestra, Proceedings of the First European Workshop
on Low Temperature Electronics, p. C6-13, July 1994.
[3] TMA MEDICI, version 4.0, 1997.
[4] G. J. Hu, C. Chang and Chia, IEEE Trans. on Electron
Devices, ED-34, p. 2469, 1987.
[5] G. Reichert, T. Ouisse, J. L. Pelloie, S. Cristoveanu,
Solid-State Electronics, Vol. 39, No. 9, p. 1347, 1996.
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