lecture 300 – buffered op amps
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Lecture 300 – Buffered Op Amps (3/21/02) Page 300-1 LECTURE 300 – BUFFERED OP AMPS (READING: AH – 352-368) Objective The objective of this presentation is: 1.) Illustrate the method of lowering the output resistance of simple op amps 2.) Show examples Outline • Open-loop, MOSFET buffered op amps • Closed-loop MOSFET buffered op amps • BJT output op amps • Summary Buffered Goal High Frequency To illustrate the degrees of freedom and Differential Output choices of different circuit architectures that can enhance the performance of a Two-Stage given op amp. Op Amp Low Power Low Noise Low Voltage ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 – Buffered Op Amps (3/21/02) Fig. 7.0-1 © P.E. Allen - 2002 Page 300-2 What is a Buffered Op Amp? A buffered op amp is an op amp with a low value of output resistance, Ro. Typically, 10Ω ≤ Ro ≤ 1000Ω Requirements Generally the same as for the output amplifier: • Low output resistance • Large output signal swing • Low distortion • High efficiency Types of Buffered Op Amps • Buffered op amps using MOSFETs With and without negative feedback • Buffered op amps using BJTs ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-3 Source-Follower, Push-Pull Output Op Amp VDD M9 M6 IBias I17 M10 M5 R1 M8 M12 M18 Cc M15 R1 M1 VSG18 + - M11 M7 + vin M17 M2 + VSG21 + - M16 M14 VSS vout VDD M21 I20 M3 VSS CL VSS VGS19 - M13 M4 + VDD V GS22 - M19 R1 - M22 M20 Buffer Fig. 7.1-1 1 Rout = gm21+gm22 ≤ 1000Ω, Av(0) = 65dB (IBias=50µA), and GB = 60MHz for CL = 1pF Output bias current? M18-M19-M21-M22 loop ⇒ VSG18+VGS19 = VSG21+VGS22 2I18 2I19 2I21 2I22 which gives + = + KPS18 KNS19 KPS21 KNS22 ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-4 Crossover-Inverter, Buffer Stage Op Amp Principle: If the buffer has high output resistance and voltage gain (common source), this is okay if when loaded by a small RL the gain of this stage is approximately unity. VDD 240 14 M7 144 M3 14 100µA C1=8pF M4 240 14 M6 2400 7.5 C2=5pF vout RL - - vin + + vin' Input stage M1 M2 M5 360 7.5 460 7.5 Cross over stage VSS 1400 14 Output Stage Fig. 7.1-2 This op amp is capable of delivering 160mW to a 100Ω load while only dissipating 7mW of quiescent power! ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-5 Crossover-Inverter, Buffer Stage Op Amp - Continued How does the output buffer work? The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the buffer input voltage, vin’. Consider the idealized voltage transfer characteristic of the crossover inverters: VDD 240 14 M7 144 M3 14 240 14 M4 C1=8pF C2=5pF vin' M1 M2 460 7.5 M7 360 7.5 M2 Active M2-M4 Inverter M1-M3 M2 SaturInverter M1 Saturated ated vout 100µA vout VDD M6 RL M1 Active 0 VSS VA VB vin' VDD VSS Fig. 7.1-3 Crossover voltage ≡ VC = VB-VA ≥ 0 VC is designed to be small and positive for worst case variations in processing (Maximum value of VC ≈ 110mV) ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-6 Crossover-Inverter, Buffer Stage Op Amp - Continued Performance Results for the Crossover-Inverter, Buffer Stage CMOS Op Amp Specification Supply Voltage Quiescent Power Output Swing (100Ω Load) Open-Loop Gain (100Ω Load) Unity Gainbandwidth Voltage Spectral Noise Density at 1kHz PSRR at 1kHz CMRR at 1kHz Input Offset Voltage (Typical) ECE 6412 - Analog Integrated Circuit Design - II Performance ±6V 7 mW 8.1 Vpp 78.1 dB 260kHz 1.7 µV/ Hz 55 dB 42 dB 10 mV © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-7 Compensation of Op Amps with Output Amplifiers Compensation of a three-stage amplifier: Poles This op amp introduces a third pole, p’3 (what p1' and p2' about zeros?) + v2 + With no compensation, vin -Avo Vout(s) Unbuffered s s Vin(s) = s op amp p’ - 1 p’ - 1 p’ - 1 1 2 3 Pole p3' vout x1 Output stage CL RL Fig. 7.1-4 Illustration of compensation choices: jω jω p2 p3' Compensated poles Uncompensated poles p 1' p 1 p2' p2 σ p3=p3' p2' σ p1' p1 p3 Miller compensation applied around both the second and the third stage. Miller compensation applied around the second stage only. Fig. 7.1-5 ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-8 Low Output Resistance Op Amp To get low output resistance using MOSFETs, negative feedback must be used. Ideal implementation: VDD Error Gain Amplifier Amplifier viin + - Error Amplifier M2 + iout vout + CL M1 VSS RL Fig. 7.1-5A Comments: • The output resistance will be equal to rds1||rds2 divided by the loop gain • If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not defined ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-9 Low Output Resistance Op Amp - Continued Offset correction circuitry: VDD + vin - + M6 M16 - -A1+ Cc VOS M9 vout Error Loop M8 Unbuffered op amp - + A2 M17 + VBias - M10 M8A M6A M12 M13 VSS M11 Fig. 7.1-6 The feedback circuitry of the two error amplifiers tries to insure that the voltages in the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the output for any error in the loop. The circuit works as follows: When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducing IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreases by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2. ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-10 Low Output Resistance Op Amp - Continued Error amplifiers: VDD M6 M3 M4 Cc1 MR1 vin M1 + M5 VBias A1 amplifier ECE 6412 - Analog Integrated Circuit Design - II vout M2 M6A VSS Fig. 7.1-7 © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-11 Low Output Resistance Op Amp - Complete Schematic VDD + vin - + - M16 + VBiasP - M4H M3H M3 M5A MP3A MP4 MP5 M4 MP4A Cc M6 MP3 MR1 M9 M8A Cc2 Cc1 MR2 M10 M1 M2 M2A M1A MN3A M6A M8 M17 M5 MN3 MN5A MN4 M13 M12 + VBiasN - M3A M4A M11 M3HA MN4A M4HA VSS vout Compensation: Uses nulling Miller compensation. Short circuit protection: MP3-MN3-MN4-MP4-MP5 MN3A-MP3A-MP4A-MN4A-MN5A (max. output ±60mA) RC gm1 Fig. 7.1-8 CC gm6 R1 C1 RL ECE 6412 - Analog Integrated Circuit Design - II CL © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-12 Low Output Resistance Op Amp - Continued Table 7.1-2 Performance Characteristics of the Low Output Resistance Op Amp: Specification Power Dissipation Open Loop Voltage Gain Unity Gainbandwidth Input Offset Voltage PSRR+(0)/PSRR-(0) PSRR+(1kHz)/PSRR-(1kHz) THD (Vin = 3.3Vpp) RL = 300Ω CL = 1000pF THD (Vin = 4.0Vpp) RL = 15KΩ CL = 200pF Settling Time (0.1%) Slew Rate 1/f Noise at 1kHz Broadband Noise Simulated Results 7.0 mW 82 dB 500kHz 0.4 mV 85 dB/104 dB 81 dB/98 dB Measured Results 5.0 mW 83 dB 420 kHz 1 mV 86 dB/106 dB 80 dB/98 dB 0.03% 0.08% 0.13%(1 kHz) 0.32%(4 kHz) 0.05% 0.16% 3 µs 0.8 V/µs - 0.13%(1 kHz) 0.20%(4 kHz) <5 µs 0.6 V/µs 130 nV/ Hz 49 nV/ Hz rds6||rds6A 50kΩ Rout ≈ Loop Gain ≈ 5000 = 10Ω ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-13 Low-Output Resistance Op Amp - Continued Component sizes for the low-resistance op amp: Transistor/Capacitor µm/µm or pF M16 184/9 M17 66/12 M8 184/6 M1, M2 36/10 M3, M4 194/6 M3H, M4H 16/12 M5 145/12 M6 2647/6 MRC 48/10 11.0 CC M1A, M2A 88/12 M3A, M4A 196/6 M3HA, M4HA 10/12 M5A 229/12 M6A 2420/6 10.0 CF Transistor/Capacitor M8A M13 M9 M10 M11 M12 MP3 MN3 MP4 MN4 MP5 MN3A MP3A MN4A MP4A MN5A ECE 6412 - Analog Integrated Circuit Design - II µm/µm or pF 481/6 66/12 27/6 6/22 14/6 140/6 8/6 244/6 43/12 12/6 6/6 6/6 337/6 24/12 20/12 6/6 © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-14 Simpler Implementation of Negative Feedback to Achieve Low Output Resistance VDD M8 M3 200µA 10/1 1/1 M4 M6 1/1 10/1 vout + vin - CL M2 M1 10/1 10/1 1/1 M5 M10 10/1 M9 1/1 10/1 M7 VSS Fig. 7.1-9 Output Resistance: Ro Rout = 1+LG where 1 Ro = gds6+gds7 and gm2 |LG| = 2gm4 (gm6+gm7)Ro Therefore, the output resistance is 1 Rout = gm2 . (gds6+gds7)1 + 2g (gm6+gm7)Ro m4 ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-15 Example 7.1-1 - Low Output Resistance Using the Simple Shunt Negative Feedback Buffer Find the output resistance of above op amp using the model parameters of Table 3.1-2. Solution The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of 1 1000 Ro = (λ +λ )1mA = 0.09 = 11.11kΩ N P To calculate the loop gain, we find that gm2 = 2KN’·10·100µA = 469µS gm4 = 2KP’·1·100µA = 100µS and gm6 = 2KP’·10·1000µA = 1mS Therefore, the loop gain is 469 |LG| = 100 12·11.11 = 104.2 Solving for the output resistance, Rout, gives 11.11kΩ Rout = 1 + 104.2 = 106Ω (Assumes that RL is large) ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-16 BJTs Available in CMOS Technology Illustration of an NPN substrate BJT available in a p-well CMOS technology: ;;; ;; ; ;;; ;;; Emitter n+ (Emitter) Base p+ p- well (Base) Collector (VDD) Collector (VDD) n+ Base n- substrate (Collector) Fig. 7.1-10 Emitter Comments: • gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower • Can use the lateral or substrate BJT but since the collector is on ac ground, the substrate BJT is preferred • Current is required to drive the BJT ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-17 Two-Stage Op Amp with a Class-A BJT Output Buffer Stage Purpose of the M8-M9 source VDD follower: M5 M7 M12 1.) Reduce the output resistance + (includes whatever is seen from vin the base to ground divided by M1 M2 I Bias 1+βF) Cc 2.) Reduces the output load at the M4 M3 drains of M6 and M7 M6 M13 M8 Q10 vout M9 CL RL M11 Output Buffer VSS Fig. 7.1-11 Small-signal output resistance : rπ10 + (1/gm9) 1 1 = gm10 + gm9(1+ßF) Rout ≈ 1+ßF = 51.6Ω+6.7Ω = 58.3Ω where I10=500µA, I8=100µA, W9/L9=100 and ßF is 100 Maximum output voltage: Ic10 2KP’ vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD V ln t Is10 I8(W 8/L8) Voltage gain: gm10RL gm9 vout gm1 gm6 = vin gds2+gds4gds6+gds7gm9+gmbs9+gds8+gπ101+gm10RL Compensation will be more complex because of the additional stages. ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 – Buffered Op Amps (3/21/02) © P.E. Allen - 2002 Page 300-18 Example 7.1-2 - Designing the Class-A, Buffered Op Amp Use the parameters of Table 3.1-2 along with the BJT parameters of Is = 10-14A and ßF = 100 to design the class-A, buffered op amp to give the following specifications. Assume the channel length is to be 1µm. VDD = 2.5V VSS = -2.5V GB = 5MHz Avd(0) ≥ 5000V/V Slew rate ≥ 10V/µs Rout ≤ 100Ω CL = 100pF ICMR = -1V to 2V RL = 500Ω Solution Because the specifications above are similar to the two-stage design of Ex. 6.3-1, we can use these results for the first two stages of our design. However, we must convert the results of Ex. 6.3-1 to a PMOS input stage. The results of doing this give W 1= W 2 = 6µm, W3 = W4 = 7µm, W5 = 11µm, W6 = 43µm, and W7 = 34µm. BJT follower: SR = 10V/µs and 100pF capacitor give I11 = 1mA. ∴ If W13 = 44µm, then W11 = 44µm(1000µA/30µA) = 1467µm. I11 = 1mA ⇒ 1/gm10 = 0.0258V/1mA = 25.8Ω MOS follower: To source 1mA, the BJT must provide 2mA which requires 20µA from the MOS follower. Therefore, select a bias current of 100µA for M8. If W12 = 44µm, then W8 = 44µm(100µA/30µA) = 146µm. ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-19 Example 7.1-2 - Continued If 1/gm10 is 25.8Ω, then design gm9 as 1 1 gm9=R - (1/g )(1+ß ) = (100-25.8)(101) = 133.4µS gm9 and I9 ⇒ W/L = 0.809 m10 F out Let us select W/L = 10 for M9 in order to make sure that the contribution of M9 to the output resistance is sufficiently small and to increase the gain closer to unity. This gives a transconductance of M9 of 469µS. To calculate the voltage gain of the MOS follower we need to find gmbs9. gm9γN 469·0.4 ∴ gmbs9 = = = 57.1µS 2 2φF + VBS9 2 0.7+2 where we have assumed that the value of VSB9 is approximately 2V. 469µS ∴ AMOS = 469µS+57.1µS+4µS+5µS = 0.8765 V/V. The voltage gain of the BJT follower is 500 ABJT = 25.8+500 = 0.951 V/V Thus, the gain of the op amp is Avd(0) = (7777)(0.8765)(0.951) = 6483 V/V The power dissipation of this amplifier is, Pdiss. = 5V(1255µA) = 6.27mW ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-20 Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage This amplifier can reduce the quiescent power dissipation. VDD M5 M10 + vin - M7 Q8 95µA M1 M2 133µA Cc vout IBias M3 M9 M4 CL RL M6 Output Buffer VSS Fig. 7.1-12 Slew Rate: + IOUT (1 + βF)I7 SR+ = CL = CL and SR- β9(VDD − 1V + |VSS| − VT0)2 = 2CL If βF = 100, CL = 1000pF and I7 = 95µA then SR+ = 8.59V/µs. Assuming a W9/L9 = 60 (I9 = 133µA), ±2.5V power supplies and CL = 1000pF gives SR= 35.9V/µs. (The current is not limited by I7 as it is for the positive slew rate.) ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-21 Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage Small-signal characteristics: Cc + gmIVin R1 V1 gmIIV2 - Cπ + Vπ + R2 V 2 - gm8Vπ R3 Nodal equations: gmIVin = (GI + sCc)V1 − sCcV2 + 0Vout 0 = (gmII − sCc)V1 + (GII + gπ + sCc + sCπ)V2 − (gπ + sCπ)Vout 0 ≅ gm9V1 − (gm13 + sCπ)V2 + (gm13 + sCπ)Vout where gπ > G3 The approximate voltage transfer function is: (s/z1) − 1 (s/z2) − 1 V9(s) Vin(s) ≈ Av0(s/p1) − 1 (s/p2) − 1 where −gmIgmII gm13 gmII gm9 1 Av0 = GIGII z1 = C z2 = − Cπ + Cc 1 + gmII Cπ gm9 c gmII − gm13 1 + gmII −gm13gmII Cπ GIGII -1 −GIGII gm9 p1 = gmIICc 1 + βFgmII + Cc gm13gmII p2 ≅ (gmII + gm9)Cπ ECE 6412 - Analog Integrated Circuit Design - II Vout gm9V1 Fig. 7.1-13 © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-22 vOUT (Volts) Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage - Continued Output stage current, IC8: S9 60 IC8 = ID9 = S6ID6 = 43 95µA = 133µA Small-signal output resistance: rπ + RII 19.668kΩ + 116.96kΩ rout = 1 + βF = =1353Ω 101 if I6 =I7 = 95µA, and βF = 100. 2 Loading effect of RL on the voltage transfer curve (increasing W9/L9 will 1 improve the negative part at the cost of power dissipation): R = 1000Ω L 0 RL = 100Ω RL =50Ω -1 -2 -3 -2 ECE 6412 - Analog Integrated Circuit Design - II -1.5 -1 -0.5 0 0.5 vIN (Volts) 1 1.5 2 Fig. 7.1-14A © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-23 Example 7.1-3 - Performance of the Two-Stage, Class AB Output Buffer Using the transistor currents given above for the output stages (output stage of the two-stage op amp and the buffer stage), find the small-signal output resistance and the maximum output voltage when RL = 50Ω. Use the W/L values of Example 7.1-2 and assume that the NPN BJT has the parameters of ßF = 100 and IS = 10fA. Solution It was shown on the previous slide that the small-signal output resistance is rπ + rds6||rds7 19.668kΩ + 116.96kΩ = = 1353Ω rout = 1+ßF 101 Obviously, the MOS buffer of Fig. 7.1-11 would decrease this value. The maximum output voltage is given above is only valid if the load current is small. If this is not the case, then a better approach is to assume that all of the current in M7 becomes base current for Q8. This base current is multiplied by 1+ßF to give the sourcing current. If M9 is off, then all this current flows through the load resistor to give an output voltage of vOUT(max) ≈ (1+ßF)I7RL If the value of vOUT(max) is close to VDD, then the source-drain voltage across M7 may be too small to be in saturation causing I7 to decrease. Using the above equation, we calculate vOUT(max) as (101)·95µA·50Ω or 0.48V which is close to the simulation results shown using the parameters of Table 3.1-2. ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002 Lecture 300 – Buffered Op Amps (3/21/02) Page 300-24 SUMMARY • A buffered op amp requires an output resistance between 10Ω ≤ Ro ≤ 1000Ω • Output resistance using MOSFETs only can be reduced by, - Source follower output (1/gm) - Negative shunt feedback (frequency is a problem in this approach) • Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is larger than the gm of a MOSFET • Adding a buffer stage to lower the output resistance will most like complicate the compensation of the op amp ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
