Low Power CMOS
Process Technology
Scott Crowder
IBM, SRDC, East Fishkill, NY
Outline
•
•
•
•
•
What is Low Power?
Process For Low Standby Power
Process For Low Active Power
Other Low Power Requirements
Conclusions
Process Technology/Scott Crowder
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Power Components in Digital CMOS
• Standby Power
–
–
–
–
Power when no function is occurring
Critical for battery driven
Can be reduced through circuit optimization
Temperature dependent leakage current dominates power
• Active Power
– Switching power plus passive power
– Critical for higher performance applications
• Other Sources of Power Consumption
– Analog & I/O Power
• Some circuit configurations have current flow even w/o switching
– Dynamic Memory Refresh Power
• eDRAM, 1T SRAM require periodic refresh of data
Process Technology/Scott Crowder
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Power Components (simple version)
Power = Switching Power + Passive Power
f*C*V*V
Frequency
Voltage
Capacitance
I (V,T) * V
Current
Process Technology/Scott Crowder
Voltage
4
Power Trends
Handheld Technology
Desktop Processor Technology
Base Devices, 10% Activity, 105C
Gate
Source
Power for 10 x 10 mm chip (Watts)
200
Well
without High-K
Passive Power (picoWatts/Micron)
High Vt Devices, 25C
150
100
50
0
180nm 130nm
90nm
65nm
45nm
100
Gate
Sub Vt
Active
80
60
40
20
0
180nm
Process Technology/Scott Crowder
130nm
90nm
65nm
5
What is Low Power in CMOS?
• Depends on product application
• Examples
#1: Handheld phone chip
#2: Server microprocessor chip
Process Technology/Scott Crowder
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Example #1: Handheld Application
• Key Attributes:
–
–
–
–
–
Battery Powered
In off-state significant portion of time
Standby condition at room temperature
Lawsuit if chip gets too hot
Standby dominates power requirements
• Leakage current at room temperature dominates power
• What is Low Power Optimized Design?
– Want highest performance @ given leakage current
Process Technology/Scott Crowder
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Example #2: Server Application
• Key Attributes:
–
–
–
–
–
Powered by electrical grid
Almost always on
Power condition at operating temperature
Lower power reduces packaging & cooling expense
Switching power dominated power requirements in past
• Want lower capacitance, voltage at maximum frequency
– Passive power at operating temperature now a major component
• Want lower high temperature leakage current & lower voltage
• What is Low Power Optimized Design?
– Want switching power to dominate
– Want to maximize performance & modulate voltage to meet power
requirements
Process Technology/Scott Crowder
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One More Major Component: Cost
• Critically important to technical solution
• Example #2: Server microprocessor
– Higher performance = higher end product price
– Will add reasonable cost to enable performance
• Higher cost process: strain engineering, added metal levels
• Flip-chip packaging, heat sinks & fans
• Example #1: Handheld application
– Market will not allow higher cost solutions
– Lower power specifications
– Focus on lowest cost process that meets market demand
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Low Standby Power
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Components of Passive Power
• Major components
– Source leakage current
• Sub threshold off-state
current
– Gate current
VDD
IG,off
VDD
IS, off
IG,on
GND
IG,off
• Tunneling current thru
gate dielectric
– Well current
IW
Process Technology/Scott Crowder
IW
IS, off
IG,on
• Band-to-band tunneling
current to well
VDD
GND
11
IS: Source Sub threshold Leakage
Sub threshold current
Ioff (pA/um)
10000000
10000000
1000000
100000
100000
10000
1000
1000
100
10
10
1
0.1
0.1
0.01
0.001
0.001
1e-4
1E-5
1e-5
1e-6
1E-7
1e-7
0.1 0.2
0.2 0.3
0.3 0.4
0.4 0.5
0.5 0.6
0.6 0.7
0.7 0.8
0.8 0.9
0.9
1.1 1.2
1.2
00 0.1
11 1.1
25C
125C
Vt (V)
• Strong Vth dependence
• Strong Temperature dependence
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Under scaling Supply Voltage
Ring Delay (psec)
30
1.0V
25
1.1V
20
1.0V
1.2V
15
1.1V
1.2V
10
1.0V
1.1V
1.2V
500mV
350mV
250mV
Lower leakage power at same
performance at higher Vth & Vdd
5
0
0.1
1
10
100
1000
Relative Leakage Power
•
•
Higher performance at given leakage power by raising Vdd
Vdd scaling has slowed dramatically for low standby power
Process Technology/Scott Crowder
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Methods to Modulate IS Leakages
• Reverse Body Bias or Active Well
NFET
PFET
Silicide
N+
P+
PWell
NWell
N-band for NFET Active Well
Added well
implant to
separate well
and substrate
P-type Substrate
Process Technology/Scott Crowder
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Reverse Body Bias
LOW VT DEVICES
HIGH VT DEVICES
Total Leakage
Total Leakage
1e-5
1e-3
Reverse bias
1e-6
1e-7
1e-4
125C
~5x
1e-8
Reverse bias
125C
1e-5
1e-6
1e-9
-0.4
25C
25C
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
1e-7
0.4 -0.4
-0.3
-0.2
Body Bias Voltage
Body bias dependence limited
by IG & IW leakage
-0.1
0.0
0.1
0.2
0.3
0.4
Body Bias Voltage
Leakage dominated by IS but
low body effect
Process Technology/Scott Crowder
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IG: Gate Leakage
1.0
NFET Gate Leakage (µA)
0.9
~10x
per
0.2nm
SiOxNy
0.8
0.7
0.6
0.5
0.4
0.3
0.2
~12 Angstromgate oxide
+1V
0.1
0.0
0
25
Q. Liang, IBM
50
75 100
Temperature (C)
125
150
Kraus, et al, IEEE TED Vol 52, No. 6 2005, page 1141
• Function of gate dielectric material and thickness
• Low temperature dependence -> dominates at low T
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Methods to Reduce Gate Leakage: N
fixed EOT contours
Kraus, et al, IEEE TED Vol 52, No. 6 2005, page 1141
• Increased Nitrogen concentration reduces gate leakage
Process Technology/Scott Crowder
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Methods to Incorporate Nitrogen
N plasma
plasma
nitridation
thermal
nitridation
N-implant
N
SiO2 base oxide
SiO2 base oxide
N
N
700-1000C
NH3, NO
N
oxidation
N
N
N
N
N
N
more N at top surface
N
N throughout
N
N
Process Technology/Scott Crowder
N
more N at bottom
18
Methods to Reduce Gate Leakage: High-K
PolySi or
Metal Gate
High-k Layer
Bottom interface
silicon
High-k/Metal Gate Stack: Tinv = 14.5A, ToxGL = 16A
Benefits
• >1000x lower IG
• Lower Tinv at same IG
to enable device scaling
Issues
• Vth control (WF engineering)
• Charge trapping
• Mobility degradation
• Increased complexity
Process Technology/Scott Crowder
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Mobility
• Acceptable long channel mobility with Hf-based oxides
• Requires optimization of HfSiO(N)/SiO(N) composition
[M Frank et al., VLSi-TSA05 ]
Process Technology/Scott Crowder
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Contact
S/D
STI
2
Oxide/Nitride
spacer
HfSiO
gate
stack
Counter
doping
interfacial
layer
('cap')
EXT
EXT
halos
Capacitance density [µF/cm ]
Gate Workfunction Tuning
Contact
S/D
STI
Bulk Si
Fig.1 schematic to illustrate different components
for vt adjustments for HfSIO gate stack
1.20
SiON
1.00
0.80
pFET
nFET
0.60
High-k / SiON
High-k / SiO2
0.40
0.20
0.00
-1.5
Conventional
HfSiO
-1.0
-0.5
0.0
0.5
Gate voltage [V]
1.0
1.5
Fig. 3 Split C-V curves demonstrating
Optimized high-k dielectric stackthe
reduces
Vt shift
by 200~300 mV
Vt shiftpFET
obtained
by gate
Selective use of ultra-thin interface/surface
modification
layers
stack optimization
onM.SiO
and SiON
2
M. Frank et al VLSI-TSA 2005
interface layers
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IW: Tunneling & Trap-Assisted Current
Gate Field
Enhanced
BTB
*
S/D
De
p le
tio
n
*
*
BTB tunneling
Trap Assisted
Well
100
Current (pA/um)
* * * * ** *
1000
10
IS
IG
IW
1
0.1
0.01
*
*
Schematic of IW sources
200
150
100
50
Technology Node (nm)
Relative Contribution of IW
• Band to band tunneling increases with doping levels & steeper gradients
• Gate field enhanced tunneling increases with thinner gate dielectric
• Reduction of trap assisted current varies with cause
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Methods to Reduce Junction Leakages
2.5
Capacitance (pF/um2)
Current (pA/um)
2
1.5
1
1.5
6
1.4
5.5
1.3
5
1.2
4.5
1.1
4
1
3.5
0.9
0.5
25
30
35
40
45
50
25
30
35
40
3
45
Implant Energy (KeV)
Halo implant angle (degrees))
NFET Junction Leakage vs. Halo Angle
Current (pA/um)
• Leakage modulated primarily by transistor doping profiles
PFET Junction Leakage vs. S/D Energy
Ref: Hook, ACEED 2005
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Low Active Power
Process Technology/Scott Crowder
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Components of Active Power
Power ~ f * C * V * V + I (V,T) * V
Voltage
Higher Transistor Performance at Same Leakage
Same Fmax at Lower Voltage
Lower Active Power
Process Technology/Scott Crowder
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Performance Scaling
Traditional performance scaling: Shorter Gate Length
Higher Gate Capacitance (IG)
Shallower Junctions (IW)
Lower Threshold Voltage (IS)
Lower Supply Voltage
All did not scale in
65nm technology
Higher performance with:
Higher Supply Voltage
Higher Inversion Capacitance
Higher Mobility
Process Technology/Scott Crowder
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Mobility Innovation: Stress Memory
After anneal & Nit Removal
n F E T Ioff (n A /u m )
Amorphous layer
By implant
1000
1e-05
Control
100
1e-06
Tensile Nit stressor
10
1e-07
1
1e-08
0.006
0.007
0.008
0.009
0.01
0.011
0.012
0.013
0.014
600 700 800 900 1000 1100 1200 1300 1400
b (M 1 FN10
10 0 08 0 07 M 1 I
)
nFET Ion (uA/um)
Si is crystallized and stress is “memorized”
Process Technology/Scott Crowder
[Chan, CICC ’05]
27
Mobility Innovations: Strained Liner
Compressive
Tensile
Nit +Nitride
Ge
Contact
Tensile nit
Compr nit
N
P
ST
10-5
a) NMOS
10-6
10 -5
Ioff (A/µm)
Ioff (A/µm)
10 -4
Un-stress
10 -6
tensile
10 -7
10 -8
700
900
1100
Ion (µA/µm)
1300
b) PMOS
Un-stress
Compressive
10-7
10-8
10-9
350
450
550
Ion (µA/µm)
[Chan, CICC ’05]
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Mobility Innovations: Embedded SiGe
1700
[Luo, IEDM 2005]
Rodlin (ohm)
1500
1300
1100
P+
900
w/o eSiGe
700
eSiGe
500
300
eSiGe
Compressive liner
eSiGe
eSiGe + CSL
0
[Luo, IEDM 2005]
0.01 0.02 0.03 0.04 0.05 0.06 0.07
PFET Lgate (um)
PFET Liner Mobility Enhancement
Embedded SiGe Cross-section
• Introduces compressive stress
• Lowers contact resistance
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Mobility Innovations: <100> PFET
X (100)
<011> channel
Z (001)
<011> channel
X (100)
0o notch
Y (010)
<001>
channel
Z (001)
<010>
channel
45o notch
Y (010)
Process Technology/Scott Crowder
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Mobility Innovations: <100> PFET
p
insensitive
, ,
10-6
100
05
Carrier direction
<110>
Carrier direction
<100>
10
pMOS Ioff (A/um)
pFET Ioff (nA/um)
1000
10-7
06
compressive
10-8
07
Neutral
tensile
10-9
08
1
0.0002
200
0.0003
0.0004
0.0005
300
400
500
pFET Ion (uA/um)
M 1 FPRVT1 x_08 M 1 Io n
0.0006
600
.
0 002
200
0 0025
0 003
300
0 0035
0 004
400
0 0045
0 005
500
0 0055
pMOS Ion (uA/um)
0 006
600
[Chan, CICC ’05]
• Significant boost in PFET current without added process steps
• Loss of ability to increase current with compressive stress
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Mobility Innovations: Hybrid Orientation
• 110 surface:
2x higher PFET µ
>2x lower NFET µ
• Hybrid Orientation
• 110 for PFET
• 100 for NFET
M. Yang, VLSI 2004
Process Challenges:
- Low defect epitaxy
- Planarization
- Trench isolation
PMOS
Process Technology/Scott Crowder
NMOS
32
Inversion Capacitance: Metal Gates
Stability <700C
Stability >700C
1
IA
H
IIA
Li
Be
Na Mg
18
* = NFET; **=PFET
16
17
IIIA
IVA
VA
VIA
VIIA
He
B
C
N
O
F
Ne
P
S
Cl
Ar
6
7
IIIB
IVB
VB
VIB
VIIB
IB
IIB
Al* Si
V*
Cr Mn* Fe Co** Ni** Cu
Zn
Ga Ge As
Se
Br
Kr
Ru Rh** Pd** Ag
Cd
In
Sn
Sb
Te
I
Xe
W Re** Os Ir** Pt** Au
Hg
Tl
Pb
Bi
Po
At
Rn
Sc
Ti*
Rb
Sr
Y
Zr* Nb* Mo
Cs
Ba
*
La Hf* Ta*
Fr
Ra
**
Ac
*
**
Tc
11
15
5
VIII
10
14
4
Ca
9
13
3
K
8
VIIlA
12
Ce
Pr
Nd Pm Sm Eu Gd Tb
Dy
Ho
Er Tm Yb
Lu
Th
Pa
U
Cf
Es
Fm Md No
Lr
Np
Pu Am Cm
Bk
Metals 3-5 nm thick on 500 nm SiO2, anneal 3 oC/s up to 1000 oC in FG
Binary/ternary alloys: W2N*, Ta2N*, TaN*, TaSiN*, RuO2**, CoSi2, NiSi
• Metal gate incorporation to remove gate depletion
• Holy Grail: Band edge workfunction & thermally stable
Process Technology/Scott Crowder
33
Metal Gate Integration Options: FuSi
“Two Steps”
“One Step”
Metal (Ni,Co)
Polysilicon
Silicide
Metal Deposition
Anneal, Strip, Anneal
Metal (Ni,Co)
Polysilicon
Silicide
NiSi
Anneal, Strip, Anneal
Silicide
[Kedzierski, IEDM ’02]
Process Technology/Scott Crowder
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Challenges for FuSi
O
Al
Ni
Hf
Si+Hf
• Dual Workfunction creation
Counts
– Alloys
– DopingAl spike
– Phase change
NiAlSi
Al pile up
HfO2
[ YH Kim IEDM’05]
• Workfunction control & stability
• Variation with gate density & size
Process Technology/Scott Crowder
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Metal Gate Integration Options:
Replacement Gate
Build Device
Etch Gate
Deposit High-k
Deposit Gate Metal
Deposit Fill Metal
CMP
Challenges:
• Integration of different workfunction metals: high complexity
• High-k deposition on small gate area
• ALD probably required for gate metal
Process Technology/Scott Crowder
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Metal Gate Workfunction Stability
2
Capacitance Density (norm.)
Workfunction of integrated metal gates has strong
dependence on deposition & annealing conditions
Deposition
Annealing
Capacitance Density µ(F/cm )
•
3.0
2.5
2.0
Method2
1.5
1.0
Method1
0.5
0.0
-0.5
0.0
0.5
1.0
1.5
2.0
As deposited
1.0
0.8
Reducing
Ambient
0.6
Oxidizing
Ambient
0.4
0.2
[E. Cartier, VLSI ’05]
0.0
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
Gate Voltage (V)
•
Potential root causes of workfunction shifts
–
–
–
–
–
Metal induced gap states (MIGS)
Oxide charge (O vacancies) in HfO2
Oxidation of interfacial metal
Hf-diffusion into metal (WF change)
Dipole layers at SiO2/HfO2 interface
Process Technology/Scott Crowder
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Memory Limitation to Voltage Scaling
• SRAM cell stability limits scaling of array Vdd
– Vth mismatch due to dopant fluctuation in best case is
constant with scaling
• Lack of gate dielectric scaling has caused it to increase
– Reduction of all other components of mismatch critical
[VLSI 2005]
1.0
• Design Options
0.4
Cell area =
0.197µm2
0.0
0.0 0.2 0.4 0.6 0.8 1.0
Vleft [V]
Vright [V]
Vright [V]
0.8
0.6
0.2
8T
1.0
0.8
– Larger cells
– Separate array Vdd
– Alternative cells/memory
• 8T SRAM
• eDRAM
6T
0.6
0.4
0.2
Cell area =
0.262µm2
0.0
0.0 0.2 0.4 0.6 0.8 1.0
Vleft [V]
Butterfly curve comparison for scaled cells
Process Technology/Scott Crowder
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Components of Switching Power
Power ~ f * C * V * V
Capacitance
Transistor
Ccg
Metallization
Cmg
Cg
Cd, area
Cov
Cvert
Cd, per
Cd, per
Process Technology/Scott Crowder
Chor
39
Capacitance Reduction: SOI
Cd, per
Cd, area
Cd, per
Cd, per
Cd, area
Cd, per
Bulk Transistor
SOI Transistor
• Reduction of area diffusion capacitance to negligible level
• Reduction of perimeter capacitance with film scaling
• Additional AC drive current benefit from gate coupling
Process Technology/Scott Crowder
40
Options to Gate Capacitance Scaling
• Need better electrostatic control to scale LG
– Higher gate inversion capacitance
• High-K gate dielectric material to reduce EOT
• Metal gate material to eliminate gate depletion
– Fully depleted double gate structures
• Better channel control through structural change
• LG must decrease more than Cinv increases
Process Technology/Scott Crowder
41
Capacitance Scaling with Metal Gate
• LG must decrease to prevent capacitance increase
Si Band edge
DIBL at constant LG
Towards mid-gap
Gate Workfunction
• Short channel effect degradation when metal gate
workfunction deviates too far from band edge
– Lose portion of performance benefit and most of power benefit
Process Technology/Scott Crowder
42
One Double Gate Structure: FinFET
NiSi Gate
NiSi
Si
Fin
Tox = 1.6nm
Tsi = 25nm
Si
[D. Fried]
BOX
Kedzierski,
IEDM 03
Process Challenges:
• Fin creation and control
• Source/drain resistance engineering
• Contact formation and control
Process Technology/Scott Crowder
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BEOL Capacitance Scaling
Performance ~ R * C
Cvert
h
Chor
Capacitance ~ keff * h / space
Resistance ~ ρ / (h * w)
Reduce inter-level dielectric constant => lower capacitance
Reduce resistance => lower height => lower capacitance
Process Technology/Scott Crowder
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Capacitance Scaling: Reducing BEOL k
A. Grill et al., Adv. Metalliz. Conf. 2001
Cohesive Strength, Γ (J/m2)
12.0
X-H. Liu et al., Adv. Metal. Conf. (2004);
8.0
4.0
0.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Nominal Dielectric Constant, k
• Multiple porous dielectric options with k < 2.4
– Spin-on and CVD deposition options
• All materials have lower material strength as k decreases
– Optimization of BEOL stack & packaging required
Process Technology/Scott Crowder
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Capacitance Scaling: Scaling h
Line Resistivity (µΩ-cm)
14
Assumptions
Grain size = 2x line width
Smooth surfaces
Mean free paths: Al=15 nm; Cu=39 nm;
Au =40 nm; Ag=45 nm
Cu
12
10
Ag
8
Au
6
Note: Pure Al has poor E-M;
Al(Cu) alloy has poor R.
4
2
0
0.01
Al (pure)
45 nm
0.1
Linewidth (µm)
1
S. Rossnagel, Semicon West (2004).
• Copper will continue to be material for low ρ metallization
Process Technology/Scott Crowder
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Capacitance Scaling: Scaling h
Ta/TaN
Liner
Cu
[Edelstein, 2005]
ITRS 45nm PVD liners demonstrated
•
Cu BEOL using Ru liner
Scaling requires thinner liner & seed films
– 45nm dimensions demonstrated
– Porous dielectrics must be compatible with thin liner to have benefit
•
ALD liner & Cu seed reduction provide opportunity for additional scaling
Process Technology/Scott Crowder
47
2X
pitch
wires
Min.
pitch
wires
Native BEOL capacitor
Capacitance/Area (fF/um 2)
Passives Scaling: BEOL Capacitors
3
2.5
Native BEOL
2
1.5
1
0.5
0
0
50
100
150
Technology (nm)
• Benefit of scaling:
better “free” BEOL capacitors
• Good tolerance due to
averaging over many levels
Process Technology/Scott Crowder
48
Passives Scaling: Decoupling Capacitors
Capacitance (fF/um2)
200
150
Trench Capacitor
100
Gate Oxide Caps
50
0
0
0.5
1
1.5
Leakage (nA/um2)
2
2.5
Trench Capacitors
• Gate capacitor scaling not possible with low passive power
• >10x reduction in area & >100x reduction in leakage with
trench capacitors
Process Technology/Scott Crowder
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Conclusions: Handheld Low Power
• Standby power dominated
• Choices:
– Add strain engineering without gate scaling
– Add high-K dielectrics to enable gate scaling
– Add design complexity to modulate leakage
• Decision will be driven by lowest cost solution
Process Technology/Scott Crowder
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Conclusions: Plugged In Low Power
• Active Power Dominated
• Performance elements added as developed
• Choices:
– Lower supply voltage
• May require new memory choice
– Add design complexity to reduce both switching and
passive power
• Voltage islands, clock gating, etc…
Process Technology/Scott Crowder
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