Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-1
LECTURE 192 – CMOS PASSIVE COMPONENTS - I
(READING: Text-Sec. 2.10)
Objective
The objective of this presentation is:
1.) Examine the passive components that are compatible with CMOS technology
2.) Physical influence on passive components
Outline
• Capacitors
• Resistors
• Summary
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-2
Types of Capacitors in a MOSFET
Physical Picture:
SiO2
Gate
Source
C1
Drain
C2
C3
FOX
FOX
C4
CBS
CBD
Bulk
Fig120-06
MOSFET capacitors consist of:
• Depletion capacitances
• Charge storage or parallel plate capacitances
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-3
MOSFET Depletion Capacitors
Model:
1.) vBS ≤ FC·PB
CJ·AS
CJSW·PS
,
CBS =
MJ +


vBS
vBSMJSW
1 
1 
PB 
PB 


and
2.) vBS> FC·PB
CJ·AS
CBS =
1+MJ

+



1- FC
CJSW·PS

1 - FC
Polysilicon gate
H




Source
Drain
F
E
A
SiO2
B
Bulk
Fig. 120-07
Drain bottom = ABCD
Drain sidewall = ABFE + BCGF + DCGH + ADHE
VBS
1 - (1+MJSW)FC + MJSW PB 
CBS
where
AS = area of the source
vBS ≤ FC·PB
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
ECE 4430 - Analog Integrated Circuit Design I
C
D
VBS
1 - (1+MJ)FC + MJ PB 
1+MJSW
G
vBS ≥ FC·PB
PB
vBS
FC·PB
Fig. 120-08
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-4
Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Mask L
LD
Actual
L (Leff)
Oxide encroachment
Mask
W
Actual
W (Weff)
Gate
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Gate
FOX
Source
Gate-Channel
Capacitance (C2)
Bulk
FOX
Drain
Channel-Bulk
Capacitance (C4)
Overlap capacitances:
C1 = C3 = LD·Weff·Cox = CGSO or CGDO
(LD ≈ 0.015 µm for LDD structures)
Channel capacitances:
C2 = gate-to-channel = CoxWeff·(L-2LD) =
CoxWeff·Leff
C4 = voltage dependent channelbulk/substrate capacitance
Fig. 120-09
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-5
Charge Storage (Parallel Plate) MOSFET Capacitances - C5
View looking down the channel from source to drain
Overlap
Overlap
Gate
Source/Drain
FOX C5
C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 × 10-4 F/m2:
Type
CGSO
CGDO
CGBO
CJ
CJSW
MJ
MJSW
P-Channel
220 ×10-12
220 × 10-12
700 × 10-12
560 × 10-6
350 × 10-12
0.5
0.35
N-Channel
220 × 10-12
220 × 10-12
700 × 10-12
770 × 10-6
380 × 10-12
0.5
0.38
Units
F/m
F/m
F/m
F/m2
F/m
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Expressions for CGD, CGS and CGB
Cutoff Region:
CGB = C2+2C5 = Cox(Weff)(Leff)
+ 2CGBO(Leff)
CGS = C1 ≈ Cox(LD)Weff = CGSO(Weff)
CGD = C3 ≈ Cox(LD)Weff = CGDO(Weff)
Saturation Region:
CGB = 2C5 = CGBO(Leff)
CGS = C1+(2/3)C2 = Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
Nonsaturated Region:
CGB = 2 C 5 = 2CGBO(Leff)
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
ECE 4430 - Analog Integrated Circuit Design I
Page 192-6
Cutoff
VB = 0
;;;
;;;
;;;
;;;
VS = 0
CGS
VG < VT
Polysilicon
p+
p- substrate
Saturated
VB = 0
p+
p- substrate
Active
VB = 0
n+
VS = 0
CGS
n+
CGB
VG >VT
Polysilicon
n+
p- substrate
VD >VG -VT
CGD
n+
Inverted Region
VS = 0
CGS
VG >VT
Polysilicon
p+
VD > 0
CGD
n+
VD <VG -VT
CGD
n+
Inverted Region
Fig120-1
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-7
Illustration of CGD, CGS and CGB
Comments on the variation of CBG in the cutoff region:
1
CBG = 1
Capacitance
1 + 2C5
+
C4 Large
C2 C4
C2 + 2C5
1.) For vGS ≈ 0, CGB ≈ C2 + 2C5
(C4 is large because of the thin
inversion layer in weak inversion
where VGS is slightly less than VT))
2.) For 0 < vGS ≤ VT, CGB ≈ 2C5
(C4 is small because of the thicker
inversion layer in strong inversion)
ECE 4430 - Analog Integrated Circuit Design I
Lecture 192 – CMOS Passive Components - I (7/10/04)
CGS
C1+ 0.67C2
C1+ 0.5C2
C1, C3
2C5
0
CGS, CGD
vDS = constant
vBS = 0
C4 Small
CGS, CGD
CGD
CGB
Off
Saturation
VT
vGS
NonSaturation
vDS +VT
Fig120-12
© P.E. Allen - 2002
Page 192-8
Characterization of Capacitors
• C is the desired capacitance
• Dissipation of a capacitor
Q = ωCRp
where Rp is the equivalent parallel resistance associated with the capacitor, C
• A varactor is a variable capacitor
• Cmax/Cmin ratio is the ratio of the largest value of capacitance to the smallest when the
capacitor is used as a varactor.
• Parasitic capacitors are the capacitors to ac ground from both terminals of the desired
capacitance.
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-9
Standard MOS Capacitors
Polysilicon-Oxide-Channel for Enhancement MOSFETs
G
D,S
;;;
;;;;;;;
;;;
;;;;;;;
D,S
G
VDG = VGS > VT
Gate
Bulk
p+
Source
n+
CGC
Drain
n+
Channel
p- substrate/bulk
Fig. 192-01
Comments:
• The capacitance variation is achieved by changing the mode of operation from depletion
(minimum capacitance) to inversion (maximum capacitance).
• Capacitance = CGS ≈ CoxW·L
• Channel must be formed, therefore VGS > VT
• With VGS > VT and VDS = 0, the transistor is in the active region.
• LDD transistors will give lower Q because of the increase of series resistance.
ECE 4430 - Analog Integrated Circuit Design I
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-10
Standard MOS Capacitors - Continued
Bulk tuning of the polysilicon-oxide-channel capacitor (0.35µm CMOS)
0.8
-0.65V
CG
vB
Fig. 192-02
VT
0.6
0.4
Volts or pF
1.0
CG
0.2
0.0
-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5
vB (Volts)
Cmax/Cmin ≈ 4
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Standard MOS Capacitors - Continued
Bulk connected to Source-Drain
G,B
Gate
Bulk
p+
Source
n+
p- substrate/bulk
Fig. 192-03
;;;
;;;
D,S
G,B
D,S
Page 192-11
CGC
Drain
n+
CBC
CG-D,S
CG-D,S = CGS + CGB
CGS
Comments:
• Capacitance is more constant as a function of VG-D,S
• Still not a good capacitor for large voltage swings
• Increased parasitics from the gate/bulk terminal
CBG
VG-D,S
Fig. 192-04
VT
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-12
Standard Mode NMOS Varactor – Continued
More Detail - Includes the LDD transistor
;;;
;;;;;;;;
;;;
;;;;;;;;
D,S
G
Shown in accumulation mode
Bulk Rsj Cj
p+
Cov
n+
p- substrate/bulk
Rd
Cov
Cox
Csi Cd
Cd
Rsi
D,S
Rd
B
n+
G
n- LDD
Fig. 192-05
Best results are obtained when the drain-source are on ac ground.
Experimental Results (Q at 2GHz, 0.5µm CMOS):
Cmin
Cmax
4.5
CGate (pF)
4
34
VG = 2.1V
3.5
3
VG = 2.1V
32
30
28
VG = 1.8V
2.5
VG = 1.8V
VG = 1.5V
26
VG = 1.5V
2
Qmin
Qmax
38
36
24
22
1.5
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
Fig. 192-06
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-13
MOS Capacitors - Continued
Accumulation-Mode Capacitor† ††
;;
=
CG-D,S
Polysilicon
n+
Source
n+
n+
Substrate
Drain
Source
Oxide
p+
Channel
n-well
Fig. 192-07
Comments:
• Again, the capacitor variation is achieved by moving from the depletion (min. C) to
accumulation (max. C)
• ±30% tuning range
• Q ≈ 25 for 3.1pF at 1.8 GHz (optimization leads to Qs of 200 or greater)
†
T. Soorapanth, et. al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs,” Proc. 1998 Sym. on VLSI Circuits, Digest of
Papers, pp. 32-33, 1998.
††
R. Castello, et. al., “A ±30% Tuning Range Varactor Compatible with future Scaled Technologies,” Proc. 1998 Sym. on VLSI Circuits, Digest of
Papers, pp. 34-35, 1998.
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-14
;;;
Accumulation Capacitor – More Detail
Bulk
p+
Cov
Cw
Rs
Rw
n+
;;;
;;;;
Rd
D,S
G
Shown in depletion mode.
Cov
Cox
Rd
Cd
Cd
n- LDD
D,S
B
n+
G
n- well
p- substrate/bulk
Fig. 192-08
Best results are obtained when the drain-source are on ac ground.
Experimental Results (Q at 2GHz, 0.5µm CMOS):
Cmin
Cmax
4
VG = 0.9V
3.2
VG = 0.6V
VG = 0.6V
35
2.8
VG = 0.9V
30
VG = 0.3V
2.4
VG = 0.3V
40
QGate
CGate (pF)
3.6
Qmin
Qmax
45
2
25
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
Fig. 192-09
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
ECE 4430 - Analog Integrated Circuit Design I
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-15
MOS Capacitors - Continued
Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs
A
A
IOX
IOX
IOX
poly
FOX
B
B
FOX
n-active
poly
n-well
p-substrate
n-active
n-well
p-substrate
Unit capacitance ≈ 1.2 fF/µm2
Voltage dependence:
C(V) ≈ C(0) + a1V + a2V2, where a1 ≈ 0 and a2 ≈ 210 ppm/V2
(Not as good linearity as poly-poly capacitors)
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-16
MOS Capacitors - Continued
Polysilicon-Oxide-Polysilicon (Poly-Poly)
A
B
IOX
IOX
Polysilicon II
IOX
Polysilicon I
FOX
FOX
substrate
Best possible capacitor for analog circuits
Less parasitics
Voltage independent
Possible approach for increasing the voltage linearity:
A
Top Plate
Top Plate
Bottom Plate
Bottom Plate
Fig. 162-12
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B
© P.E. Allen - 2002
Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-17
Implementation of Capacitors using Available Interconnect Layers
M3
M2
B
M1
T
Poly
T
M3
T
M2
M1
B
M2
B
T
B
M1
Poly
T
M2
M1
B
Fig. 192-13
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-18
Horizontal Metal Capacitors
Capacitance between conductors on the same level and use lateral flux.
Top view:
Fringing field
Metal
Metal
Metal 3
+
-
+
-
Metal 2
-
+
-
+
Metal 1
+
-
+
-
Side view:
Fig2.5-9
These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors (i.e.,
1.5fF/µm2).
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Lecture 192 – CMOS Passive Components - I (7/10/04)
Page 192-19
To Be Continued
The next lecture will continue the examination of passive components compatible
with CMOS technology.
ECE 4430 - Analog Integrated Circuit Design I
© P.E. Allen - 2002