Design Note DN 2013-10
V1.0 January 2013
CrCM PFC Boost Converter Design
Mladen Ivankovic
Infineon Technologies North America (IFNA) Corp.
Design Note DN 2013-10
CCM PFC Boost Converter Design
V1.0 January 2013
Edition 2013-10
Published by
Infineon Technologies North America
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DN 2013-10
Subjects: CrCM PFC Boost Converter Design
Author: Mladen Ivankovic (IFNA PMM SMD AMR PMD 3)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will
help us to continuously improve the quality of this document. Please send your proposal (including a
reference to this document) to: [Mladen.Ivankovic@infineon.com]
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Design Note DN 2013-10
CCM PFC Boost Converter Design
V1.0 January 2013
Table of contents
1 Introduction .................................................................................................................................................. 4
2 Boost topology ............................................................................................................................................ 4
3 PFC Modes of Operation ............................................................................................................................. 5
4 CrCM PFC Boost Design Equations .......................................................................................................... 7
4.1
Rectifier Bridge .................................................................................................................................. 7
4.2
Input Capacitor ................................................................................................................................... 7
4.3
Input Inductor ..................................................................................................................................... 8
4.4
MOSFET ..........................................................................................................................................10
4.5
Boost Diode......................................................................................................................................13
4.6
Output Capacitor: .............................................................................................................................14
4.7
Heatsink ...........................................................................................................................................15
5 References .................................................................................................................................................16
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Design Note DN 2013-10
CCM PFC Boost Converter Design
1
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Introduction
Power Factor Correction (PFC) shapes the input current of the power supply to be in synchronization with the
mains voltage, in order to maximize the real power drawn from the mains. In a perfect PFC circuit, load should
look like a pure resistance load. The input current is a clean sine wave and in phase with the voltage, with no
input current harmonics. This document is intended to discuss the topology and operational mode for low power
(<300W) PFC applications, and provide detailed design equations through an example.
2
Boost topology
Active PFC can be achieved by any basic topology, the boost converter (Figure 2.1) is the most popular
topology used in PFC applications.
The advantages of boost topology are:

Voltage gain >1 works for AC input

Only one MOSFET

Control Voltage referred to ground

capable of high efficiency

simple choke, no problems with magnetic coupling

CCM provides continuous input current

CCM mode with favorable waveform
factor for conduction loss
The disadvantages of boost topology are:

MOSFET: VDS ≈ VO >VI

no galvanic isolation - short circuit protection a problem

Medium ripple current loading of output capacitor

CCM Mode requires hard switching of boost diode- SiC required for high efficiency
Comments on other topologies:

Buck:
Lacks voltage gain; pulsating input current

Buck/Boost:
Complex, output voltage has opposite polarity, pulsating input current

Flyback:
Easily resistive, but pulsating input current (can be solved with interleaved), but 2x copper losses for
given magnetic

SEPIC:
Step down/step up with continuous input current, but having two inductors,
two capacitors, more complex control, only one inductor can be made sinusoidal, more distortion.
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Design Note DN 2013-10
V1.0 January 2013
CCM PFC Boost Converter Design
Boost Key Waveforms
DC Bus
PFC
Converter
AC
Vac
DC/DC
Converter
Load
Figure 2.1
3
PFC Modes of Operation
The boost converter can operate in three modes; continuous conduction mode (CCM), discontinuous
conduction mode (DCM), and critical conduction mode (CrCM). Fig. 3.1 shows modeled waveforms to illustrate
the inductor and input currents in the three operating modes, for the same exact voltage and power conditions.
15
15
10
10
Iin ( t)
15
Iin( t)
I in( t)
IL ( t)
I L ( t)
5
0
0
0
-4
-4
-4
-4
Continuous Conduction Mode (CCM)
1
10
2
3
10
t
10
4
10
10
IL ( t)
5
5
0
-4
1 10
-4
-4
2 10
3 10
-4
4 10
Critical Conduction Mode (CrM)
t
Figure 3.1
Quick comparison between operting modes is given in the table below:
5
0
0
-4
110
-4
210
-4
310
-4
410
Discontinuous Conduction
Mode (DCM)
t
Design Note DN 2013-10
CCM PFC Boost Converter Design
Part / Characteristic
Input Current
2
I XR MOSFET loss
MOSFET tON
CrCM Variable Frequency
Fixed Frequency CCM
Variable Frequency CCM
High Ripple current - large EMI
Lower Ripple Current-
Lower Ripple Current -
filter
smaller EMI
smaller EMI
High conduction loss: 9-12%
Trapezoidal waveform-
Trapezoidal waveform-
penalty
lower loss
lower loss
High- dependent on Boost
High- dependent on boost
diode
diode
Lower - Toff dependent on
Lower- Toff dependent on
design
design
Slow, cheap type OK- select
Best performance with SiC
Best performance with
for QR
or GaN
SiC or GaN
Design for high ripple- gapped
Design for high average LF
Design for high average
soft ferrite usually best choice;
current and lower ripple
LF current and lower
combine with Litz wire; lower
current; powdered core:
ripple current; powdered
temp range
Kool Mu, High Flux
core: Kool Mu, High Flux
Sized for fAC input current, very
Sized for fAC input current,
Sized for fAC input current,
HF RMS ripple current
HF RMS ripple current
HF RMS ripple current
Quasi resonant Ton possible
Toff at 2x input current- high
MOSFET tOFF
loss
High fSW = higher losses
Boost Diode
Inductor
Output Capacitor
Controller and design
PF/Distortion
Controller and design
dependent; fixed CCM
dependent; can be quite good
inherently higher distortion
due to current loop
Power Density
Cost
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Controller and design
dependent; very low
distortion possible; few off
the shelf controller
solutions
Design dependent on
Design dependent on
inductor and
inductor and
semiconductors
semiconductors
Low for lower power levels;
Better at higher power
Better at higher power
EMI filter a limit
levels
levels
Design dependent on inductor
and semiconductors
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Design Note DN 2013-10
CCM PFC Boost Converter Design
4
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CrCM PFC Boost Design Equations
The following are design equations for the CrCM operated boost, also a design example is integrated to further
clarify the usage of all equations. The boost converter encounters the maximum current stress and power
losses at the minimum line voltage condition (
), hence, all design equations and power losses will be
using the low line voltage condition.
Table 1 Specifications
Input voltage
90-270 Vac 60Hz
Output voltage
420V
Maximum power
150W
Minimum frequency
25kHz
Output voltage ripple
10Vp-p
Hold-up time
16.6ms @ Vo.min=350V
Estimated efficiency η
0.9
4.1
Rectifier Bridge
The bridge total power loss is calculated using the average input current flowing through two of the bridge
rectifying diodes.
.
4.2
Input Capacitor
The input high frequency filter Cin has to attenuate the switching noise due to the high frequency inductor
current ripple (twice of average line current). The worst conditions will occur on the peak of the minimum input
voltage.
The maximum high frequency voltage ripple is usually imposed between 1% and 10% of the minimum rated
input voltage. This is expresses by a coefficient r (typically, r = 0.01 to 0.1).
High values of Cin helps EMI filter but causes lower power factor to decrease (higher displacemet component),
especially at high input voltage and low load. Low values of Cin improve power factor (lower displacement
component) but require larger EMI filter.
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Design Note DN 2013-10
CCM PFC Boost Converter Design
4.3
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Input Inductor
Lets define following parameters:
a - ratio between peak input voltage and output voltage (DC bus voltage)
a_max  1.41
Vinmax
Vo
-1
a_max  9.064  10
a_min  1.41
Vinmin
Vo
a_min  3.021  10
-1
Ro - equivalent output load (resistance)
2
Ro 
Vo
Pin
Ro  1.058  10
3
Switching frequency is changing with input voltage amplitude and angle. Amplitude varies from minimum
(90V*1.41 ) to maximum (270*1.41) value. Angle is changing from o to π during each half grid cycle. Switching
frequency as function of these two variable is represented on graph below:
f ( x y) 
1 1 2
 y ( 1 - ysin( x) )
2 2
normalized operating frequency
f
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Design Note DN 2013-10
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CCM PFC Boost Converter Design
One can notice that during each cycle (angle axis) switching frequency start with maximum value travels
through minimum value at peak voltage (angle = π/2) and goes back to maximum. See details below:
operating frequency versus line voltage angle
0.25
0.2
f ( x a_max )
f  x 0.5 
0.15
f ( x a_min) 0.1
0.05
0
0
1
2
3
x
Also, when amplitude changes from minimum value (90*1.41) to the maximum value (270*1.41) frequency
travel from one minimum through maximum to another minimum value. One needs to choose smaller of these
two and use to calculate inductance value. Details are given below:
operating frequency versus peak input voltage
0.04

f  y 
2 
0.03
0.02
0.01
0.4
  a_max  1.922  10- 2

2

f
  a_min  1.593  10- 2

2

f
0.6
y
0.8
Frequency multiplier at max input voltage.
Frequency multiplier at max input voltage
One needs to select condiotion at overall minimum frequency, so:
boost inductor value is:
Lin 
Ro
 
 

min f  a_min f  a_max 
fswmin
2
2
 
 

-4
Lin  6.743  10
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Design Note DN 2013-10
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CCM PFC Boost Converter Design
Design criteria comment:
Calculated LP was to obtain operating frequencies higher than 25kHz at peak input voltage (min or max) and
twice of nominal output power (to cover start up and load transients).
Let’s calculate other inductor parameters like peak current and RMS current. Peak current is responsible for
inductor saturation and RMS current together with inductor resistance produces heat. These three parameters
(Lin, IPKin and IRMSin) determine inductor and a vendor can design and provide inductor based on them.
Peak Input current
IPKin  4 
Pin
a_minVo

IPKin  5.253
RMS Input current
IRMSin
IPKin
3 2
IRMSin 2.145
4.4
MOSFET
In order to select the the optimum MOSFET, one must understand the MOSFET requirements in a CrCM boost
converter. High voltage MOSFETS have several families based on different technologies, which each target a
specific application, topology or operation. For a boost converter, the following are some major MOSFET
selection considerations:

Low FOMs - Ron*Qg and Ron*Qoss

Fast Turn-on/off switching, gate plateau near middle of gate drive range

Low Output capacitance Coss for low switching energy,
to increase light load efficiency.

Switching and conduction losses must be balanced for
minimum total loss- this is typically optimized at the
low line condition, where worse case losses and
temperature rise occur.

VDS rating to handle spikes/overshoots

Low thermal resistance RthJC.

Package selection must consider the resulting total
thermal resistance from junction to ambient.

Body diode speed and reverse recovery charge are
not important, since body diode never conducts in a
boost converter.
10
Fig 4.1 Gate voltage versus charge
Design Note DN 2013-10
CCM PFC Boost Converter Design
V1.0 January 2013
The recommended CoolMOS MOSFET series for boost applications are the CP series and the C6/E6 series.
CP CoolMOS provides fastest switching, hence, best performance, but requires careful design in terms of gate
driving circuit and PCB layout. While C6/E6 series provides cost advantage, easier design, but less
performance compare to CP series.
MOSFET IPW60R199CP is selected, and its parameters will be used for the following calculations.
The MOSFET rms current across the 60Hz line cycle can be calculated by the following equation, and
consequently the MOSFET conduction loss is obtained.
MOSFET RMS current:
RMSsw
1
6
-
4 a_min
9 
RMSsw  0.352
IRMSsw IPKinRMSsw

IRMSsw  1.849
MOSFET conduction losses are:
The switching losses ,due to current – voltage cross, occur only at turn-off because of the Critical Conduction
Mode operation.
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Design Note DN 2013-10
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CCM PFC Boost Converter Design
Average input peak current is:
Where
is crossover time at turn off. Estimate value is around
.
Average switching frequency needs to be calculated at minimum input voltage as well.
Let’s first calculate MOSFET on time.
MOSFET on time at minimum input voltage:
IPKinLin
T on 
a_minVo

-5
Ton  2.791  10
4
3.510
4
310
4
2.510
4
210
4
fsw ( x)
Switching frequency as function of input voltage
angle is given on Fig 4.2:
fsw (x) 
410
1
(1 - a_minsin
 (x))
T on
0
1
2
3
x
Fig 4.2 Switching frequency as function of angle
The average switching frequency is:

fswav 
1 
 fsw ( x) dx
 0
fswav  2.893  10
4
Now, one can calculate switching losses as:
Turn-on the losses are due to the discharge of the total drain-source capacitance inside the MOSFET.
Where
is energy contained in the MOSFET output capacitance.
This is the worst case scenario, if MOSFET turns on at max voltage. Because MOSFET operates in QR mode
This value is much smaller, an estimate says that is usually half of this value. So,
MOSFET total losses are:
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Design Note DN 2013-10
CCM PFC Boost Converter Design
4.5
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Boost Diode
The boost freewheeling diode will be a fast recovery one. The value of its DC and RMS current, useful for
losses computation, are respectively:
Diode RMS current:
RMSd 
1
3

4 a

RMSd  0.207
IRMSd  IPKinRMSd

IRMSd  1.086
The conduction losses can be estimated as follows:
Where
(threshold voltage) and Rd (differential resistance) are parameters of the diode.
The breakdown voltage is fixed with the same criteria as the MOSFET.
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CCM PFC Boost Converter Design
4.6
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Output Capacitor:
The output bulk capacitor (Co) selection depends on the DC output voltage, the output power and the desired
voltage ripple.The 100 to 120Hz (twice the mains frequency) voltage ripple is a function of the capacitor
impedance and the peak capacitor current :
Output capacitor value based on ripple:
Cor 
Po
4  fl VoVo
Cor  2.707  10
-5
is usually selected in the range of less than 5% of the output voltage.
Although ESR usually does not affect the output ripple, it has to be taken into account for power losses
calculation. The total RMS capacitor ripple current, including mains frequency and switching frequency
components, is:
Output capacitor RMS current:
 Po 

 Vo 
2
IRMSd - 
IRMSc 
2
IRMSc  1.026
If the application has to guarantee a specified hold-up time, the selection criterion of the capacitance will
change: Co has to deliver the output power for a certain time (tHold) with a specified maximum dropout voltage:
Output capacitor based on hold up time:
Coh 
2 Pothold
2
2
Vo - Vomin
Coh  2.268  10
-5
where Vomin is the minimum output voltage value (which takes load regulation and output ripple into (account)
and Vopmin is the minimum output operating voltage before the ’power fail’ detection from the downstream
system supplied by the PFC.
Final selection is larger out of these two:
Co  max(CorCoh)
Co  2.707  10
-5
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CCM PFC Boost Converter Design
4.7
Heatsink
The MOSFET and diode can have separate heatsinks or share the same one, however, the selection of the
heatsink is based on its required thermal resistivity.
In case of separate heatsinks for the diode and MOSFET,
thermal resistors are modeled as in Figure 4.1.
PFET
TJ.FET RthJC.FET TC.FET
Pdiode
TJ.diodeRthJC.diode TC.diode RthCS.deiode TS.diodeRthSA.diode
RthCS.FET TS.FET RthSA.FET
Figure 4.1
In case of a single heatsink for both the diode and the
MOSFET, thermal resistors are modeled as in Figure 4.2.
The maximum heatsink temperature
outcome of the two equations below
PFET
TJ.FET RthJC.FET TC.FET
RthCS.FET
is the minimum
TS
Pdiode
Once
is specified, then the heatsink thermal resistance
can be calculated.
TJ.diode
RthJC.diode
TC.diode RthCS.diode
RthSA
TA
PFET+Pdiode
Figure 4.2
is the thermal resistance from junction to case, this is specified in the MOSFET and Diode datasheets.
is the thermal resistace from case to heatsink, typically low compared to the overall thermal resistance,
its value depends on the the interface material, for example, thermal grease and thermal pad.
is the thermal resistance from heatsink to ambient, this is specified in the heatsink datasheets, it depends
on the heatsink size and design, and is a function of the surroundings, for example, a heatsink could have
difference values for
for different airflow conditions.
is the heatsink temperature,
is the case temperature ,
is the ambient temperature.
is FET’s total power loss ,
is diode’s total power loss.
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Design Note DN 2013-10
CCM PFC Boost Converter Design
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V1.0 January 2013
References
TM
[1] CoolMOS Selection Guide.
http://www.infineon.com/dgdl/infineon_CoolMOS_SelectionGuide.pdf?folderId=db3a304314dca389011528372fbb12ac&fileId=db3a30432f91014f012f95fc7c24399d
TM
[2] Infineon Technologies Application Note: “CoolMOS CP - How to make most beneficial use of the latest
generation of super junction technology devices”. February 2007.
http://www.infineon.com/dgdl/Aplication+Note+CoolMOS+CP+(+AN_CoolMOS_CP_01_Rev.+1.2).pdf?fold
erId=db3a304412b407950112b408e8c90004&fileId=db3a304412b407950112b40ac9a40688
[3] Infineon Technologies Application Note: “AN-PFC-TDA4862-1” Octobar 2003
http://www.infineon.com/cms/en/product/power-management-ics/ac/dc/power-control-ics/pfc-dcmdiscontinuous-conduction-mode-control-ic-forsmps/channel.html?channel=ff80808112ab681d0112ab6a73f6050c&tab=2
[4] ST Application Note: “AN-966 Enhanced transition mode power factor controller”
[5] Infineon Technologies Application Note: “CCM Boost converter design” by Abdel-Rahman Sam,
Infineon Technologies; January 2013
[6] “PFC topologies and control fundamentals” by Jon Hancock and Mladen Ivankovic, Infineon technologies
Detroit PFC training; September 2011.
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Design Note DN 2013-10
CCM PFC Boost Converter Design
Symbols used in formulas
Vinmin: Minimum input voltage
Vo: Output voltage
Vinmax: Maxmum input voltage
Vo: Output voltage
Po: Output power
fsw: Switching frequency
Tsw: Switching time period
fline: line frequency
Lin: Input Inductor
IAVin: Inductor average current across the line cycle
IPKin: Inductor peak current
Vf.bridge: Bridge diode forward voltage drop
Pbridge: Bridge power loss
o
Ron(100C): MOSFET on resistance at 100 C
Qgs: MOSFET gate-source charge
Qgd: MOSFET gate-drain charge
Qg: MOSFET total gate charge
Rg: MOSFET gate resistance
Vpl: MOSFET gate plateau voltage
Vth: MOSFET gate threshold voltage
ton: MOSFET switching on time
toff: MOSFET switching off time
Eoss: MOSFET output capacitance switching energy
IRMSsw: MOSFET rms current across the line cycle
Pcond: MOSFET conduction loss
Pcross: MOSFET switching off power loss
Pcap: MOSFET output capacitance switching loss
IDo: Boost diode average current
IRMSd: Boost diode average current
Vto: Boost diode threshold forward voltage drop
PDon: Boost diode conduction loss
Co: Output capacitor
ESR: Output capacitor resistance
thold: Hold-up time
Vomin: Hold up minimum output voltage
∆Vo: Output voltage ripple
IRMSC: Output capacitor rms current
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