Vol. 35, No. 5
Journal of Semiconductors
May 2014
A low power 20 GHz comparator in 90 nm COMS technology
Tang Kai(唐凯)1; 2 , Meng Qiao(孟桥)1; 2; Ž , Wang Zhigong(王志功)1; 2 , and Guo Ting(郭婷)1; 2
1 Institute
of RF- & OE-ICs, Southeast University, Nanjing 210096, China
Research Center of RF-ICs and RF-Systems, Ministry of Education, Nanjing 210096, China
2 Engineering
Abstract: A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power
analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases
of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is
adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS
technology, this comparator only occupies a die area of 65 150 m2 with a power dissipation of 14 mW from
a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating
with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with
5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The
comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed
applications.
Key words: comparator; ADC; ultra-high-speed; low power; latch; CMOS
DOI: 10.1088/1674-4926/35/5/055002
EEACC: 2570
1. Introduction
Comparators are the critical block in the implementation
of the analog-to-digital converters (ADCs). Not only do they
represent the link between the analog and digital domains but
they also play a significant role in the overall sampling rate
and resolution of the ADCs. With the rapid development of the
wireless communication systems, like the 40 Gb/s optical coherent system and ultra wide band (UWB) radio receiver, the
speed of digital signal processing has greatly improved over
time, which requires a large increase in the data conversion
rates to enhance the overall performance. Therefore, the highspeed ADC has received significant attention and the demand
for high-speed ADC is rapidly increasing. As the comparator
plays a key role in determining the overall performance of the
ADC, research into high sampling rate and medium resolution
comparators certainly becomes the hot topic.
Some high speed comparators in SiGe HBTs, InP HBTs
and GaAs have been published in recent years. A monolithic
ultra-high-speed comparator was implemented in SiGe BiCMOS with sampling rates of up to 32 GHz and power dissipation of 405 mW, reported in Ref. [1]. Two 20 GSps comparators
have been fabricated in InP HBTs with a power dissipation of
336 mW and 440 mW, and an input sensitivity of 10 mV and
16 mV, respectivelyŒ2; 3 . These comparators need a high voltage supply and consume a large amount of current. Compared
to HBTs, at high frequency, processes with small feature sizes
are also attractive, such as deep sub-micro CMOS process technology due to its higher speed, smaller area, lower power and
ease of the system on a chip (SoC) design. A 65 nm CMOS
comparator with modified latch to achieve 7 GHz/1.3 mW
at 1.2 V was reported in Ref. [4]. Reference [5] presented
a 24 GSps ADC with time-interleaved architecture in 90 nm
CMOS technology and the power consumption is 1.2 W at
1.2 V. In Ref. [6], a 10 GHz three-stage comparator in 1.2 V
0.11 m CMOS technology is presented, which is designed to
extract every 4th bit of a 40 Gb/s data stream.
In this paper, a low power high-speed comparator working
at a sampling rate of 20 GHz with medium resolution has been
designed and realized in a 3 bit 20 GSps flash ADC in 90 nm
CMOS technology. The proposed comparator employs a fully
differential configuration to mitigate common-mode noise. A
master-slave latch is used to achieve high operation rates. In
order to achieve lower power consumption, the current bias
is replaced by a clock-controlled nMOSFET, which does not
consume static power. Measurement results show that the comparator can sample up to 20 GHz and the power dissipation is
only 14 mW under a 1.2 V supply.
2. The circuit design
Figure 1 shows a block diagram of the proposed comparator, which used a three-stage topology and band width enhancement techniques to achieve a small aperture time under the
1.2 V supply. The comparator consists of a preamplifier stage,
Fig. 1. The comparator block diagram.
* Project supported by the PhD Programs Foundation of Ministry of Education of China (No. 2009009211001) and the Important National
Science & Technology Specific Projects (No. 2010ZX03006-003-02).
† Corresponding author. Email: mengqiao@seu.edu.cn
Received 12 October 2013, revised manuscript received 20 December 2013
© 2014 Chinese Institute of Electronics
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Tang Kai et al.
Fig. 2. 6 stages cascaded preamplifier.
master-slave latches and an output buffer. The preamplifier is
designed with a low voltage fully differential structure to lessen
the overdrive recovery time, offer sufficient gain for the latch
and have a large bandwidth. The master-slave latches, which
consist of two stages: amplification and regenerative, is designed to compare the two voltage levels and produce a fast
digital decision as soon as possible. The output is designed to
produce a well defined digital data buffer, which is made up of
a three cascaded differential amplifier followed by two CMOS
inverters.
2.1. Preamplifier stage
The input amplifier acts as an isolator between the voltage reference and the master-slave latch to improve input bandwidth and decrease input offset. The fully differential preamplifier has a number of advantages over conventional closed
loop architectures. It enables high speed operation, better signal swing and high speed gain, good immunity to supply noise
and low power consumption.
Multi-stage preamplifier topology for the high speed comparator was reported in Refs. [7–9]. According to an n gain
stages amplifier, each with gain A and time constant is , the
delay time of the amplifier td and the output can be calculated
based on a single-pole amplifier model as followsŒ8 :
td D n D
n
Vout .t/ D Vin A
"
1
nG 1=n
;
GBW
e
t =
(1)
#
n 1
X
.t=/k
;
kŠ
(2)
kD0
where G D An is the gain of the n stages amplifier, and GBW
is the gain–bandwidth product of each stage. To minimize the
comparison time with respect to the number of stages, dt/dn is
set equal to zero and the solutions of n and A can be achieved.
When the gain A equals e, three to ten stages are a good choice
to have a fast response.
The effective input referred offset of n stages cascaded amplifier can be derived asŒ7
Voffset; in D Voffset; 1 C
n
X
Voffset; i
i D2
iQ1
;
In this design, a six-stage amplifier is adopted and Figure
2 highlights the cascaded fully differential preamplifier. The
first stage is a four inputs low gain pre-amplifier. This stage
is utilized to reduce input offset by applying large size input
transistors. The second to sixth stages are the high gain amplifiers to reduce the effect of latch offsets. The preamplifier was
sized keeping speed and intrinsic gain as the primary considerations. All input transistors are minimal length NMOS pairs.
The widths of the transistors were adjusted to obtain requisite
gain and to keep output offset to a minimum. The preamplifier uses a resistor as the load. These loads were sized to have
decent overdrive recovery and reduced mismatch errors. Simulations show that the total delay is 21 ps and the offset is less
than 17 mV, which can meet the demand of the comparator operating frequency up to 20 GHz with the sensitivity of 20 mV.
2.2. The latch stage
In a regenerative comparator, the latch is used for its capability of high speed and the ratio of the transconductance of
the cross-coupled transistors to the parasitic capacitance in the
latch determines speed. We can use small signal analysis to estimate the speed of the comparator. The analysis is based on
the regenerative latch circuit shown in Fig. 3. Transistors M1
and M2 provide the transconductance of the amplifier, reset
and track when CK D 1, while the cross coupled transistors
M3 and M4 generate negative resistance during the latching
and holding phase when CKN D 1. At first, the time constant
of the preamplifier is derived. Once the latch is disabled when
the CK is high, the preamplifier clears the differential voltage at
the output nodes from the previous latching phase, and the output begins to reset and then track the input signal. The equivalent small signal model of the preamplifier and track phase is
shown in Fig. 3(a). Using Kirchhoff’s current law (KCL) for
nodes VoutC and Vout , we can obtain the following first-order
differential equations:
(3)
Ak
kD1
where Voffse; i is the offset voltage of the i th stage, and Ak is
the gain of the kth stage. As can be seen from Eq. (3), the input
referred offset is reduced substantially via the product of n gain
factors.
gm1; 2 Vin C
dVoutC
VoutC
C C1
D 0;
R1
dt
(4)
gm1; 2 VinC C
dVout
Vout
C C1
R1
dt
(5)
D 0;
where gm1; 2 is the transconductance of the input transistors M1
and M2, R1 and C1 represent the total resistance and capacitance at the output nodes during the tracking and preamplifier
operation, respectively. Assuming that Vout .t/ D VoutC .t/
Vout .t /, Vin .t/ D VinC .t/ Vin .t /, Vout .0/ D Vtrack_initial ,
Vtrack_initial is the initial condition for the differential equations
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Fig. 3. Latch schematic and equivalent circuit. Small signal model of latch (a) in the tracking phase and (b) in the regeneration phase.
(4) and (5), the value is the final differential output voltage at
the end of the previous latching and regeneration phase. We
can calculate the difference output voltage as follows:
Vout .t / D Vout .0/e
t=track
D Vtrack_initial e
C gm R1 Vin .t/.1
t=track
e
t=track
C gm R1 Vin .t/.1
e
/
t=track
/;
(6)
where track is the time constant of the track and amplifier
phase, which is given by track D R1 C1 . From this expression, the first term represents the reset process, while the second term means the tracking process. Based on our analysis, a
smaller track can lead to both faster reset and tracking.
When the clock is low, the comparator works as a latching
phase. The equivalent small-signal mode of the comparator in
the latching and regeneration stage is shown in Fig. 3(b). Also,
using KCL for nodes VoutC and Vout , we can obtain the following first-order differential equations:
gm3; 4 Vout C
VoutC
dVoutC
C C2
D 0;
R2
dt
(7)
gm3; 4 VoutC C
Vout
dVout
C C2
R2
dt
(8)
D 0;
where gm3; 4 is the transconductance of the cross coupled
NMOS transistors M3 and M4, R2 and C2 represent the total
resistance and capacitance at the output nodes VoutC and Vout
during regeneration and latching. Assuming Vreg_initial is the final output voltage at the end of the tracking process, using the
same method as above, we can get the difference output Vout (t)
as follows:
Vout .t/ D Vreg_initial et=reg ;
(9)
reg D
C2
gm3; 4
1=R2
:
makes the time constant reg positive. From Eq. (9), a large
output voltage at the end of the tracking phase is good for the
regeneration speed. We can achieve a large voltage through the
preamplifier as the first stage, but the gain of the preamplifier
is limited because of the preamplifier gain-bandwidth tradeoff. For a given capacitance C2 , increasing gm3; 4 could reduce
the regeneration time constant reg from Eq. (10). The gm3; 4
can be increased either by using wider transistors or larger bias
currents. However, increasing the transistor width will also increase the parasitic capacitance, which will decrease the regeneration and latching speeds and, if we want to ultimately increase the speed, this requires additional power consumption.
We can also increase the resistance of R2 in the regeneration
process.
In order to increase the comparator speed, the master-slave
latch is used in the proposed comparator. The latch was used for
its capability of high speed. The latch also has good tolerance to
meta-stability error. It has input differential pairs (M1 and M2)
that turn on when the clock is high and track the input from the
previous stage. When the clock is low, the latching stage takes
over, providing positive feedback and slight amplification. The
bias transistors were sized to provide low swing and, along with
the triode loads, provide lower charging and discharging times
for the latch.
Based on the analysis, a dynamic SCL is used for the
master-slave latch and the schematic is shown in Fig. 4. This
structure can achieve smaller resistance loads (R1 / in the reset
and tracking phase to ensure a small time constant, and larger
resistance loads (R2 / in the regeneration phase because of the
dynamic loads’ resistance varying with the voltage of the clock
signal. The dynamic loads’ resistance rds of the active resistant
can be derived as follows:
rds D
(10)
From this solution, we can see that output voltage Vout .t/
increases exponentially if gm3; 4 is larger than 1/R2 , which
1
1 C VDS
D
D
gds
ID 1
W
K0
.jVGS j
2L
;
(11)
jVT j/2 where is the channel-length modulation factor, K 0 is the process transconductance coefficient, and W and L are the length
and width of NMOS transistors MR1 and MR2. VGS , VT , ID
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Tang Kai et al.
Fig. 6. The layout of proposed comparator.
Fig. 4. The proposed dynamic SCL latch.
Fig. 5. The schematic of output buffer.
are the operating parameters of MR1 and MR2.
In the tracking mode, when CK is high and the transistors
MR1 and MR2 are on, the resistance rds is small, therefore,
track D R1 C1 D rds C1 is smaller and the process of reset and
tracking tends to be faster. In the regeneration and hold mode,
CK is low and the transistors MR1 and MR2 are off, the resistance rds is larger, which means reg decreasing leads to a high
speed process. The large load resistance makes it reliable to design a smaller gm in the latch transistor pairs; in this case, the
sizes of cross-coupled transistors M3 and M4 can be set smaller
to decrease the parasitic capacitances during the regeneration
mode, which speeds up the dynamics of the latch.
2.3. Output stage
An output buffer is required between the output of the latch
and the digital encoder. As is shown in Fig. 5, an output buffer
made up of a three cascaded stages differential amplifier followed by two CMOS inverters is presented. To ensure the gain
of the buffer and mitigate the device self-heating, a large tail
current was provided for the differential amplifier. With two
inverters placed at the end, the output buffer can produce welldefined digital data for the following stages of the ADC.
3. Layout and post simulation result
The proposed comparator is realized in a flash ADC design
in TSMC 90 nm CMOS technology and occupies an active area
of 65 150 m2 . In order to decrease the mismatch between
the signal paths and devices, symmetrical topology is used in
the layout design. Dummy devices are placed around to provide
the same and identical environment to reduce the random noise
and offset caused by mismatch. The layout of the comparator
in the ADC is shown in Fig. 6.
Fig. 7. The simulation results of the comparator @ fclk D 20 GHz. (a)
fin D 2.5 GHz. (b) fin D 10 GHz.
The performance of the comparator is verified by post
simulation under technology corners and temperature. Figure
7 shows the simulation results with ss corner and 40 ıC when
the comparator operation clock fclk is 20 GHz. In Fig. 7(a),
the frequency of input sine signal fin is 5 GHz and the measured rise and fall times are 7.2 ps and 6.8 ps. The waveform
of the Nyquist with the sampling rate up to 20 GSps is shown
in Fig. 7(b), the measured rise and fall times are 11.3 ps and
10.1 ps. The simulation results demonstrate that the operation
frequency of this comparator can reach up to 20 GHz and is
suited for high speed ADCs.
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Table 1. Performance summary and comparison.
Reference
Technology
Ref. [10]
0.18 m SiGe BiCMOS
SiGe BiCMOS
InP HBT
0.25 m SiGe BiCMOS
65 nm CMOS
110 nm CMOS
90 nm CMOS
Ref. [1]
Ref. [2]
Ref. [3]
Ref. [4]
Ref. [6]
This work
Area (mm2 /
Max. fsampling
(GHz)
20
Input sensitivity/
fin (mV/GHz)
8.9/N/A
Supply
voltage (V)
3.5
Pdiss
(mW)
82
1.8/0.0455
32
20
12.5
8.4/5
16/20
2/3.125
3.5
4
3.3
405
440
150
1.975/0.0226
0.78
0.38
7
10
20
16.5/4
N/A
25/1
1.2
1.2
1.2
1.3
37
14
0.415
0.075 0.1
0.065 0.15
Fig. 9. The proposed comparator’s measured output waveforms with
fin D 5 GHz @ fclk D 10 GHz.
Fig. 8. (a) Chip microphotograph of the proposed comparator in the
ADC and (b) the measurement setup.
4. Measurement result
The chip microphotograph of the proposed comparator is
shown in Fig. 8(a). During testing, the output of the comparator
was observed from the MSB of the ADC. An Agilent 81250
was used to generate the differential clock frequency. A 0.5–
12 GHz balun was used in the input port to connect the 0.01–40
GHz Rohde-Schwarz SMP04 signal generator as differential
input sinusoidal signals. A BiasT was also used to provide the
input bias voltage. The measurement setup is shown in Fig.
8(b). The circuit was tested under sine wave input and clock
signals. The total power consumption is about 14 mW at a 1.2
V supply.
Time domain measurements were conducted using Tektronix and Agilent oscilloscopes. The measured output waveform (single-ended) of the comparator operating at a clock frequency of 10 GHz, with the input frequency of 5 GHz, is shown
in Fig. 9. The top line is the output waveform and the bottom
line is the clock signal. Figure 10 shows the measured out-
Fig. 10. The proposed comparator’s measured output waveforms with
fin D 10 GHz @ fclk D 20 GHz.
put waveform (single-ended) of the comparator at a clock frequency of 20 GHz, with an input frequency of 10 GHz, the
measured rise and fall times are about 21 ps and 23 ps. The results indicate that the comparator works well and has a broad
bandwidth because of the preamplifier. The simulated input
sensitivity of the comparator is 20 mVppd and the measured
result is about 25 mVppd. The experimental offset of the comparator is less than 19 mV when the input frequency is smaller
than 2 GHz.
The experimental results of this comparator are summarized in Table 1. A comparison has also been made between
this high-speed comparator and some other comparators using
a similar process or transfer rate that were found in the literature. Compared to the comparators published in the literature
with the operational frequency up to 20 GSps, the comparator
presented here demonstrates a power consumption comparable
to the best one achieved and good trade-off speed, resolution
and power.
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5. Conclusion
In this paper, a low power ultra-high-speed comparator
has been designed and implemented in TSMC 90 nm CMOS
technology and the power consumption is only 14 mW. The
master-slave latches architecture was adopted to achieve the
high speed and the experimental results show that the clock frequency can be up to 20 GHz. The comparator has good performance when the input frequency is 1 GHz @ 20 GSps and the
input sensitivity is 25 mV. The measurement results indicate
that the presented comparator is suitable for use in ultra-highspeed medium-resolution ADCs and low power applications.
Such a comparator has been successfully used in a 20 GSps
flash ADC.
Acknowledgment
The authors thank Li Zhang for the help with layout checking and design analysis tutoring and Wei Li for the help with
chip testing.
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