U
I
Thyristor Controlled
Reactor
ECE 529
Lecture 36
 Two options for inductor
models
XL
2
XL
» Little impact on digital
simulation
 Average susceptance
with firing delay angle, 
TACS
U
I
1
· 1
·
2·
sin 2 ·
1
Spring 2015
ECE 529
Lecture 36
TCR Power Circuit
 Built-in thyristor models
 Switch resistance of 0.001
for loss approximation
 Series connected devices
and associated circuits not 0.001
modeled
 Reactor R, L for application
 Numerical snubber if needed
TACS
XL
2
2
RL
XL
Rsnub
0.001
C snub
Spring 2015
1
TCR Internal Control
Scheme (one option)
U
I
ECE 529
Lecture 36
Measured
voltage or
current
Input Filter
and Phase
Compensation
Synchronization
(Phase Lock Loop)
Bref
Xref
or Iref
Convert
Current/Admittance
to Delay Angle 
(loop-up table)
TACS

Gate
Pulse
Generator
Gate Pulses
Spring 2015
3
U Current/Admittance to
I Delay Angle Conversion
ECE 529
Lecture 36
 Implement:
1
· 1
·
2·
sin 2 ·
 Can use current or impedance instead
 Bref() is a requested value
 Rather than calculating directly, a look-up
table is used.
» Appropriate scaling
TACS
4
Spring 2015
2
U
I
ECE 529
Lecture 36
Input Filtering
 Instantaneous voltage or current brought in
through an instrument transformer
 Analog and/or digital filtering to produce
fundamental component for synchronization
TACS
5
U
I
Spring 2015
ECE 529
Lecture 36
Input Filtering (cont.)
 Input voltage/current digitally sampled
 Anti-aliasing filter to remove sampling effect
» Low pass, below 1/4 sampling frequency
» Possibly add additional digital filters to pass
fundamental or block certain harmonics
 Closed loop control requires RMS voltage
and/or current
» Fundamental component from digital filter
TACS
6
Spring 2015
3
U
I
ECE 529
Lecture 36
Phase Correction
 Input filtering a time (phase delay) in the
instantaneous measured quantities
 The amount of phase delay is predictable
» Fine tune with feedback from synchronization
circuit
» Add a phase lead to correct for phase lag
» May be included within the phase locked loop
(PLL) circuit
TACS
7
U
I
Synchronization
Spring 2015
ECE 529
Lecture 36
 Detect zero crossing of input fundamental
frequency waveform
» Delay by 90 degree to get peak
» Proper delay requires knowledge of actual
system frequency (not the ideal value)
» Inputs include phase error (from measuring
circuit and system drift), and base frequency
 Note use of “analog” signals, could do this
digitally as well
TACS
8
Spring 2015
4
U
I
ECE 529
Lecture 36
Synchronization
 The device gating is synchronized with
to the phase voltage or line current
 A fairly simple approach is to use the
zero crossings.
 Need accurate detection of zero
crossing and determination of frequency
 Free of distortion
TACS
9
U
I
Spring 2015
ECE 529
Lecture 36
Synchronization
 Several common schemes used in
FACTS and Custom Power devices
» Details not available
 Phase-locked oscillator developed for
HVDC--John Ainsworth.
» Trade secret
 Implementation needed in simulation
TACS
10
Spring 2015
5
Option 1: Current Zero
U
I Crossings to Create Pulses
Named Delay= PWIDTH
P1
54
ECE 529
Lecture 36
FIREP
ALPHA
54
PWIDTH
N1
52
PLUS1
54
FIREN
ALPHA
Free Format
FORTRAN
91
CS
CS
11
SIGMA
90. - SIGMA/2 ALPHA
60*360
TACS
(in seconds)
Spring 2015
11
U Option 1: Current Zero
ICrossings to Create Pulses
ECE 529
Lecture 36
 Can add pulse blocking or bypass
command too
FIREP
From
Last
Page
+
FIREN
+
PSCR
SUM
Z
GATE
Gain=20
TACS
11
BYPASS
11
BLOCK
-
12
Spring 2015
6
Option 2: Ramp
Comparator
U
I
ECE 529
Lecture 36
 Zero detector produces pulses at current zero





crossings
Positive zero crossing kept, used to reset integrator
Output is a ramp, 0 to 360o, reset every cycle
Output (Alpha1) is compared with a phase angle
setting (ref1) which in this case is varied with a
slide control
Interpolated firing pulse generation
Note second pulse offset by 180o
TACS
Spring 2015
13
Option 2: Ramp
Comparator
U
I
ECE 529
Lecture 36
0.001 sec
45
ALPHA
90 deg
S1
PWIDTH
RAMP
HALFCY
XX0031
PLUS1
PLUS1
ZERO
XX0032
T
P1
T
N1
DELTAT
T
S2
0.5
T
PLUS1
0.008333
PWIDTH
ALPHA
S4
+
V1
-
S3
T
PLUS1
RAMP
G=21600
TACS
14
Spring 2015
7
U
I
ECE 529
Lecture 36
Waveform outputs
400
350
300
250
200
150
100
50
0
0.18
0.20
0.22
(f ile tc s c 11.pl4; x -v ar t) t: RA MP
0.24
t: A NGP
TACS
0.26
0.28
0.30
t: P1
Spring 2015
15
Thyristor Controlled
U
I Resistor (light dimmer)
ECE 529
Lecture 36
TACS Vmeas
T
V1
20 ohm
VP
VS
0kV pk
N1
VM
Rsmall
700
P1
525
350
175
0
-175
-350
-525
-700
0.00
0.03
(file TCRES.pl4; x-var t) v:V1
factors:
1
0.07
offsets:
0
0
TACS
16
c:VS
1
0
0.06
0.09
0.12
0.15
-V1
Spring 2015
8
U
I
Thyristor Controlled
Reactor
ECE 529
Lecture 36
TACS Vmeas
T
V1
0.1 mH
VP
VS
N1
10kV pk
P1
VM
Rsmall
TACS
U
I
Spring 2015
17
Thyristor Controlled
Reactor
ECE 529
Lecture 36
400
*10 3
300
200
100
0
-100
-200
-300
-400
0.00
(file TCR1.pl4; x-var t) v:V1
factors:
1
40
offsets:
0
0
TACS
0.03
c:VS
1
0
0.06
0.09
0.12
0.15
-V1
18
Spring 2015
9