1. Introduction to the Design of Analog Integrated Circuits

1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1. Introduction to the Design of Analog Integrated Circuits Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC) Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 1 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 2 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 3 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS modeling cause/effect simplification multi-disciplinar Synthesis vs analysis: OR Vof f Pd GD C CM RR D C P SRR D C SR ts(1%) f max TH D BW GB W φm Vnieq Area Upper Lower ±σ Vin = 2.5V + − + − Vout = 2 → 3V Vout = 3 → 2V Vout = OR Vout = OR/ 2@10KHz −3dB 100Hz to 10MHz >4 <1 >3 <10 <1.5 >60 >50 >50 >50 >1.5 >1.5 <1500 <1500 <1 >1 >50 <1 <0.025 - Schematics Specifications V/ µs ns KHz % Hz MHz deg mVrms mm2 - 4 /76 exhaustive high speed high precision large database Layout mVpp V Vpp mVrms mW dB dB dB Lab vs IC Design Scenario IR CM R Modeling OpAmp Synthesis Synthesis Circuit Physical Analysis Analysis EDA tools do not design ICs! Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Analog vs Digital If it can be done by digital, don't use analog! Analog IC design is complex... Background in physics, electronics, information and control theory, signal processing, communications Variety of state-of-the-art solutions What is this? High dependence from technology Modeling skills Complex EDA tools Digital way Design of Analog and Mixed Integrated Circuits and Systems Analog way F. Serra Graells Lab 5 /76 Idea-Chip Micro-Macro CMOS Modeling OpAmp Analog vs Digital AGC Preamp Background in physics, electronics, information and control theory, signal processing, communications μP ply Sup Power manager FPGA DSP ...but still necessary! Design of Analog and Mixed Integrated Circuits and Systems LNA Memory Mixer Reference Complex EDA tools Filter μC PLL PA VCO F. Serra Graells Com m u nic a tio Modeling skills ADC DAC Analog IC design is complex... High dependence from technology 6 /76 Transdu cer s If it can be done by digital, don't use analog! Variety of state-of-the-art solutions Lab ns 1. Introduction to the Design of Analog ICs 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Analog vs Digital ply Sup FPGA Mixer PLL RF Temperature frontend sensing Audio input/output Accelerometer PA VCO Imager Battery manager Magnetometer Light sensing Design of Analog and Mixed Integrated Circuits and Systems LNA Memory Reference Complex EDA tools Touch screen DSP F. Serra Graells ns Modeling skills μP Power manager Filter μC Com m u nic a tio High dependence from technology AGC Preamp Background in physics, electronics, information and control theory, signal processing, communications Variety of state-of-the-art solutions ADC DAC Analog IC design is complex... Most modern ICs are really mixed-signal 7 /76 Transdu cer s If it can be done by digital, don't use analog! ...but still necessary! Lab 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 8 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp IC vs PCB What can analog IC design offer compared to PCB? Good Design of Analog and Mixed Integrated Circuits and Systems Bad F. Serra Graells Lab 9 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp IC vs PCB What can analog IC design offer compared to PCB? Good Bad Small size and high density Complex systems High speed operation Low power consumption Heterogeneous SoC (A/D/RF/MEMS/Power) Low production costs Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 10 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab IC vs PCB What can analog IC design offer compared to PCB? Good Bad Small size and high density Low observability/controllability Complex systems Few device primitives High speed operation Technology variability (process and mismatching) Low power consumption Complex modeling Heterogeneous SoC (A/D/RF/MEMS/Power) High design costs (EDA/personnel) Low production costs High prototyping costs Long design cycles Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 11 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp IC Flavors Each application may require a different IC solution: Full-custom Density Flexibility Performance Design time EDA tools Prototype costs Target volume Mixed-mode High A and D Hand-drawn geometry All layers customized Application-specific IC (ASIC) result Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 12 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab IC Flavors Each application may require a different IC solution: Full-custom Macro-cell High High A and D A and D Density Flexibility Performance Design time EDA tools Prototype costs Target volume Mixed-mode Sigmatel STMP3520 MP3 Decoder Predefined macro blocks (ADC, memory...) Automated routing All layers customized ASIC result Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 13 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 14 /76 IC Flavors Each application may require a different IC solution: Full-custom Macro-cell Standard-cell Density Flexibility Performance Row of cells Design time EDA tools Prototype costs High High High A and D A and D D Target volume Mixed-mode I/O pad ring Gate level cells + automated routing Regular floorplan All layers customized ASIC result Routing Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp IC Flavors Each application may require a different IC solution: Full-custom Macro-cell Standard-cell Gate-array High High High Medium A and D A and D D D Density Flexibility Performance Design time EDA tools Prototype costs Target volume Mixed-mode Pre-built transistors/gates Only routing layers customized ASIC result Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 15 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab IC Flavors Each application may require a different IC solution: Full-custom Macro-cell Standard-cell Gate-array FPGA High High High Medium Low A and D A and D D D D (A) Density Flexibility Performance Design time EDA tools Prototype costs Target volume Mixed-mode Programmable logic blocks Programmable routing Not an ASIC Altera Cyclone III Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 16 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab p+ n+ Full-Custom Design Fixed CMOS technology: Materials and processes Vertical dimensions p+ n+ n+ p+ p-well n-well Analog design space: Circuit topology Device horizontal sizing non-linear! Device biasing Width Length Multiplicity Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 17 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab p+ n+ 18 /76 Full-Custom Design Fixed CMOS technology: Materials and processes Vertical dimensions p+ n+ n+ p+ p-well n-well Analog design space: Circuit topology Device horizontal sizing Device biasing other device cases: Number of turns Inner Diameter Spacing Width Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Power consumption (lifetime, range...) Silicon area (costs, packaging...) Full-Custom Design Fixed CMOS technology: Resources ce Performan Materials and processes Vertical dimensions Analog design space: Circuit topology Device horizontal sizing Figure of Merit (FoM) Device biasing 1 E+07 Analog IC design optimization rules 1 E+06 1 E+05 P/fsnyq [pJ] e.g. ADC circuits 1 E+04 1 E+03 1 E+02 ISSCC 2013 VLSI 2013 ISSCC 1997-2012 VLSI 1997-2012 FOMW=10fJ/conv-step FOMS=170dB 1 E+01 1 E+00 B. Murmann, ADC Performance Survey http://www.stanford.edu/~murmann/adcsurvey.html 19 /76 1 E-01 10 20 30 40 50 60 70 80 90 SNDR @ fin,hf [dB] Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 100 110 120 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp System Complexity Analog IC designers deal with several hierarchy and abstraction levels e.g. electrochemical smart sensor Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 20 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 21 /76 System Complexity Analog IC designers deal with several hierarchy and abstraction levels Systems switch (action) { case SAMPLING: /* Sampling action */ OUTPUT_CHANGED(out) = FALSE; *inp_mem = inp; break; case QUANTIZATION: /* Quantization action */ OUTPUT_CHANGED(out) = TRUE; if (*inp_mem>inp_th) { out = ONE; OUTPUT_DELAY(out) = t_rise; } else { out = ZERO; OUTPUT_DELAY(out) = t_fall; } OUTPUT_STATE(out) = out; OUTPUT_STRENGTH(out) = STRONG; *out_mem = out; break; case HOLDING: /* Holding action */ OUTPUT_CHANGED(out) = FALSE; } Circuits Devices Functional (Verilog/VHDL/SystemC-AMS, XSpice, Simulink) Top down Electrical (SPICE) Physical (FE simulators) Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Bottom up 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 22 /76 System Complexity Analog IC designers deal with several hierarchy and abstraction levels Mixing different abstraction levels during design switch (action) { case SAMPLING: /* Sampling action */ OUTPUT_CHANGED(out) = FALSE; *inp_mem = inp; break; case QUANTIZATION: /* Quantization action */ OUTPUT_CHANGED(out) = TRUE; if (*inp_mem>inp_th) { out = ONE; OUTPUT_DELAY(out) = t_rise; } else { out = ZERO; OUTPUT_DELAY(out) = t_fall; } OUTPUT_STATE(out) = out; OUTPUT_STRENGTH(out) = STRONG; *out_mem = out; break; case HOLDING: /* Holding action */ OUTPUT_CHANGED(out) = FALSE; } Design of Analog and Mixed Integrated Circuits and Systems Simulation speed up Study of circuit non-ideal effects Multi-level and multi-domain simulation needed (single engine or glue approach) F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 23 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 24 /76 Moore's Law Number of transistors per chip doubles every 18 (24) months http://en.wikipedia.org/wiki/Moore%27s_law Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 25 /76 Moore's Law Number of transistors per chip doubles every 18 (24) months Thanks to scaling at device (lithography) but not at chip (yield!) levels 1.2nm SiO2 thickness (5 atomic layers!) 3nm thickness http://www.intel.com Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Moore's Law Lab 26 /76 http://www.intel.com Number of transistors per chip doubles every 18 (24) months Thanks to scaling at device (lithography) but not at chip (yield!) levels Cut-off frequency increases, but it is not fully exploited (RF and power limitations) → parallelism wavelength http://www.itrs.net Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 27 /76 Moore's Law Number of transistors per chip doubles every 18 (24) months Thanks to scaling at device (lithography) but not at chip (yield!) levels Cut-off frequency increases, but it is not fully exploited (RF and power limitations) → parallelism wafer diameter Cost/transistor improved also due to wafer scaling (capacity) http://www.intel.com Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 28 /76 Moore's Law Number of transistors per chip doubles every 18 (24) months Thanks to scaling at device (lithography) but not at chip (yield!) levels Cut-off frequency increases, but it is not fully exploited (RF and power limitations) → parallelism Cost/transistor improved also due to wafer scaling (capacity) Small is beautiful, but what to do with so many, inexpensive and super fast devices? Intel 10-Core Xeon Westmere-EX 2.6Gtransistor 32nm 512mm2 Design of Analog and Mixed Integrated Circuits and Systems http://www.intel.com F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 29 /76 More than Moore Diversification of technology applications Ubiquitous computing Health Personal health monitoring Not only signal processing but: Wireless communications Power control Multi-domain integrated systems: Physics Chemistry Biosensors Transport Autom. fare collection Sm art key Telematics Society trends Smart sensing Driver monitor ing Energy Power efficiency Hybrid electr ic Sm ar t metering driving Ultra low power Security Sm ar t sensor tags Motor management Crash free E-blister E-gov Communication Wireless connectivity Ultra low power Infotainment Wideband tuning Connected car Biology Medicine Data Proc. Communication Consumer Automotive Industrial Medical Identification Design of Analog and Mixed Integrated Circuits and Systems Markets F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp More than Moore Diversification of technology applications Ubiquitous computing Not only signal processing but: Smart sensing Wireless communications Power control Multi-domain integrated systems: Physics Chemistry Biology Medicine Extended CMOS technologies Application-specific packaging Advanced analog IC design (low-power, high-speed, high-voltage, massive parallel, low-noise...) Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 30 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab ASIC Development Selecting the mixed-mode (MM) / radio-frequency (RF) CMOS technology: Triple well? Number of metal layers? Multiple-VT (low-leakage vs high-speed) MOSFETs? High-value polySi resistors (HIPO) with good linearity and low TC? Poly-insulator-poly (PiP) or Metal-insulator-metal (MiM) linear capacitors? Thick top metal for high-Q RF inductors? RF linear varactors? Anti-reflective coating and implant layer for CMOS image sensors (CIS)? Non-volatile memory (NVM) like fuse, flash, ROM...? ...? More process modules = higher costs + difficult design migration Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 31 /76 Idea-Chip 1. Introduction to the Design of Analog ICs Micro-Macro CMOS Modeling OpAmp Lab 32 /76 ASIC Development Typical project scheduling: M0 1 2 Specs 3 4 5 6 Design 7 Custom library test chips 8 9 10 11 12 Integration 13 14 15 Testing 16 17 18 19 21 22 23 Complete system-on-chip (SoC) Alignment with foundry fixed run calendar Long design iterations (typ. 6M) First complete prototype >18M Design of Analog and Mixed Integrated Circuits and Systems 20 F. Serra Graells 24 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 33 /76 Money after All Design costs (staff and EDA license) 1 layer/mask 36-mask set Foundry CMOS integration: layer #1 depends on process modules 25mm Die size: <625mm2 Mask costs: 100k€ Processing costs: 2k€/wafer Die samples: >50/wafer (200mm diameter) Intended for full production (>200 wafer/year) 25mm Full mask set production run Stepper reticle Wafer map e.g. 0.15μm 1P6M CMOS technology Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 34 /76 Money after All Design costs (staff and EDA license) 1 layer/mask 36-mask set Foundry CMOS integration: design #1 25mm Full mask set production run Multi project wafer (MPW) run design #N 25mm Die size: >4mm2 Mask and processing costs: 1k€/mm2 Die samples: <100 Intended for prototyping Stepper reticle Wafer map e.g. 0.15μm 1P6M CMOS technology Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 35 /76 Money after All Design costs (staff and EDA license) 4 layer/mask 9-mask set Foundry CMOS integration: Full mask set production run Multi layer mask (MLM) engineering run layer #2 layer #3 layer #4 12.5mm Multi project wafer (MPW) run layer #1 12.5mm Stepper reticle Die size: <156mm2 Mask costs: 25k€ Processing costs: 2k€/wafer (6-wafer lots) Die samples: >200/wafer (200mm diameter) Intended for small series (<100 wafer/year) Wafer map e.g. 0.15μm 1P6M CMOS technology Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 36 /76 Money after All Design costs (staff and EDA license) 9 layer/mask 4-mask set Foundry CMOS integration: layer #2 layer #3 Multi project wafer (MPW) run layer #4 layer #5 layer #6 Multi layer mask (MLM) engineering run layer #7 layer #8 layer #9 Full mask set production run 8.3mm layer #1 8.3mm Stepper reticle Die size: <69mm2 Mask costs: 12k€ Processing costs: 2k€/wafer (6-wafer lots) Die samples: >450/wafer (200mm diameter) Intended for small series (<100 wafer/year) Wafer map e.g. 0.15μm 1P6M CMOS technology Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 37 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Intrinsic and extrinsic model parts S B p+ n+ G D n+ p-well Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 38 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS S B p+ p-well n+ G D n+ OpAmp Lab 39 /76 Analytical (physical) vs numerical (fitting) modeling Bulk Enhancement MOSFET Intrinsic and extrinsic model parts Modeling MODEL MY_NMOS BSIM3V3 TYPE=N + VERSION=3.2 PARAMCHK=1 + NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04 + WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10 + WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0 + TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02 + PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01 + VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03 + K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01 + DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02 + A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02 + MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08 + UA=9.395E-07 UB=2.828E-15 UC=5.191E-08 + DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03 + PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08 + PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02 + CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03 + NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02 + DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01 + CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07 + CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15 + NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0 + LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0 + ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01 + JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01 + CJ=5.000E-04 MJ=5.000E-01 PB=1 + CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1 + CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1 + CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01 + TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04 + UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5 + XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0 + NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29 + NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07 + XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02 + PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05 + PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04 + WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01 . Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Idea-Chip 1. Introduction to the Design of Analog ICs Micro-Macro CMOS Intrinsic and extrinsic model parts Threshold voltage Mobility Output resistance G D Subthreshold Charge model Substrate p + n + n Lab 40 /76 MODEL MY_NMOS BSIM3V3 TYPE=N + VERSION=3.2 PARAMCHK=1 + NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04 + WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10 + WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0 + TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02 + PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01 + VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03 + K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01 + DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02 + A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02 + MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08 + UA=9.395E-07 UB=2.828E-15 UC=5.191E-08 + DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03 + PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08 + PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02 + CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03 + NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02 + DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01 SPICE + CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07 + CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15 + NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0 + LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0 + ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01 + JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01 + CJ=5.000E-04 MJ=5.000E-01 PB=1 + CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1 + CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1 + CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01 + TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04 + UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5 + XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0 + NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29 + NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07 + XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02 + PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05 + PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04 + WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01 . Process S OpAmp Analytical (physical) vs numerical (fitting) modeling Bulk Enhancement MOSFET B Modeling Junction diode + Overlap cap. Thermal model Noise model p-well Accurate results from electrical simulation Too complex for hand design! Scaling Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Bulk Enhancement MOSFET Classic large signal I/V model: Linear mode Saturation region D G CLM S Non linear Channel cut-off Channel length modulation (CLM): negligible for large signal, but critical in small signal Current factor Pinch-off voltage Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 41 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 42 /76 Bulk Enhancement MOSFET Simple enough for hand design Classic large signal I/V model: Body effect in stacked circuits? D G B Body effect coefficient S Non linear Asymmetrical D/S model! or Channel length modulation (CLM): negligible for large signal, but critical in small signal Subthreshold operation? Current factor Pinch-off voltage Single expression wanted for all regions with continuous derivatives (small signal)... Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells ? 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Bulk Enhancement MOSFET EKV large signal I/V model: G Pinch-off voltage S D B Subthreshold slope (1<n<2) Inversion coefficient Strong inversion Saturation (forward) Conduction Weak inversion (subthreshold) Reverse Specific current http://ekv.epfl.ch Enz Krummenacher Vittoz Forward Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 43 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Bulk Enhancement MOSFET Modeling OpAmp Lab Forward saturation example (neglecting CLM): EKV large signal I/V model: G http://ekv.epfl.ch Enz Krummenacher Vittoz S D B Moderate Strong inversion Weak Simple enough for hand design Symmetrical D/S expressions Leakage Explicit body effect Single expression from strong to weak inversion and from conduction to saturation Continuous derivatives for small signal parameters Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 44 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Classic small signal transconductance model: D D G Small signal increments only G B S Non-linear operating point B S Linear equivalent circuit Analog circuits biased through current sources → op as a function of drain current Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 45 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Classic small signal transconductance model: D D G Small signal increments only G B S Non-linear operating point B S Linear equivalent circuit Analog circuits biased through current sources → op as a function of drain current Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 46 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Classic small signal transconductance model: D D G Small signal increments only G B S Non-linear operating point B S Linear equivalent circuit Asymmetrical parameters and non-explicit expressions... Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 47 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET EKV small signal transconductance model: Small signal increments only G D G S D B Non-linear operating point Linear equivalent circuit Strong inversion Saturation (forward) Conduction Weak inversion (subthreshold) S B Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 48 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Bulk Enhancement MOSFET EKV small signal transconductance model: D Small signal increments only G G S D B B Non-linear operating point Equivalence between models: S Linear equivalent circuit Continuty between operating regions: Best power efficiency Strong inversion Weak Design of Analog and Mixed Integrated Circuits and Systems Moderate F. Serra Graells 49 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 50 /76 Bulk Enhancement MOSFET Input only elements: Quasi-static transcapacitance model: Small signal increments only G G S D S D B Non-reciprocal! Conduction B Fwd. Saturation Moderate Weak Gate oxide cap. Strong inversion 3.9 (SiO2) (e.g. n = 1.3) Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Bulk Enhancement MOSFET Small signal noise model: OS interface trapping Uncorrelated phenomena: Thermal agitation Power spectral density (PSD) statistics: Thermal (white) component: -10dB/dec Flicker (pink) component: Flicker Thermal Technology dependent (NMOS >> PMOS) Memory effect Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 51 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 52 /76 Bulk Enhancement MOSFET Small signal noise model: OS interface trapping Thermal agitation Noise-aware analog IC design: Signal full scale Signal-to-noise ratio Thermal (white) component: Flicker (pink) component: Dynamic Range Power Dynamic Range Area Technology dependent (NMOS >> PMOS) Memory effect Low-power circuit design Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Circuit design scalability 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Technological mismatching model: Gaussian General Pelgrom Law Device parameter P? e.g. dopant non-uniformity e.g. thickness gradient CMOS process dependent http://dx.doi.org/10.1109/JSSC.1989.572629 M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989 Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 53 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 54 /76 Bulk Enhancement MOSFET Technological mismatching model: Gaussian General Pelgrom Law e.g. dopant non-uniformity M1 M2 e.g. thickness gradient CMOS process dependent Weak Moderate Strong inversion Best area efficiency For MOS transistors, small and uncorrelated mismatching: Typically, VTH mismatch is dominant... http://dx.doi.org/10.1109/JSSC.1989.572629 M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989 Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 55 /76 Bulk Enhancement MOSFET Technological mismatching model: Analog design scalability? Depletion layer Gaussian General Pelgrom Law e.g. dopant non-uniformity e.g. thickness gradient CMOS process dependent NMOS VTH mismatching: 0.8mVµm × tox[nm] 50 Rule of thumb: 45 40 2.0µm 2.5µm 35 AVTHN [mVµm] For MOS transistors, small and uncorrelated mismatching: 2.0µm 2.5µm 30 1.6µm 25 1.2µm 20 0.6µm 0.8µm 15 10 0.18µm 0.35µm 5 0.25µm 0.12µm 0 0 1.0µm 0.7µm Precision Area 0.30µm 10 20 30 tox [nm] http://dx.doi.org/10.1109/JSSC.1989.572629 M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989 Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 40 50 60 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Bulk Enhancement MOSFET Extrinsic D/S diffusion diodes: S B p+ G D n+ n+ n+ p-well p-well Geometry parameters: Reverse leakage current: Depletion capacitance: Bottom plate Side walls Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 56 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Passive Components OpAmp Top plate Coplanar capacitors: Inter-layer thin insulator Modeling Low-ohmic connectors Lab 57 /76 Not stretchable! Bottom plate Overlap + fringing capacitance: Electrical permittivity [F/m] Process dependent Typ. available CMOS structures: Voltage linearity MOS PolySi-insulator-PolySi http://dx.doi.org/10.1109/EDL.1982.25610 PiP or MiM Metal-insulator-Metal Temp. indep. >1 1~10 Sandwitch techniques... C.P.Yuan and T.N.Trick, A Simple Formula for the Estimation of the Capacitance of Two-Dimensional Interconnects in VLSI Circuits, IEEE Electron Device Letters, 3(12):391-3, Dec 1982 Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Passive Components Serpentine resistors: Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab Not stretchable! Low-ohmic connectors Volume resistivity [Ωm] Process dependent Square resistance: Highly resistive stripes Design aspect ratio Typ. available CMOS structures: Voltage linearity Highly resistive PolySi Well ~1k Diffusion ~100 PolySi ~10 Metal ~1m HiPo 1k~10k Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Temp. indep. 58 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 59 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Universal Analog Building Block Operational voltage amplifier (OpAmp) e.g. Instrumentation amplifier Single ended case study Analog signal processing functions Non-linear, temp. uncompensated... e.g. I/V converter Wanted performance As far as OpAmp gain and bandwidth are large enough Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 60 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 61 /76 Universal Analog Building Block Operational voltage amplifier (OpAmp) CMOS OpAmp known as operational transconductance amplifier (OTA) Single ended case study Analog signal processing functions Non-linear, temp. uncompensated... e.g. switched capacitor (SC) filters Wanted performance As far as OpAmp gain and bandwidth are large enough Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 62 /76 OpAmp Performance Parameters Large signal static figures (ideal): Input range Open-loop differential DC voltage transfer curve (VTC) at constant CM: Finite Output range Equivalent input offset Open loop differential DC gain Differential input Common mode input supply voltage Design of Analog and Mixed Integrated Circuits and Systems Systematic F. Serra Graells Mismatching 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab OpAmp Performance Parameters Large signal static figures (ideal): Input common-mode DC sweep: Input range Output range Equivalent input offset Open loop differential DC gain Common mode range Depending on feedback topology! Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 63 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 64 /76 OpAmp Performance Parameters Small signal dynamic figures (ideal): AC Bode diagram: Open loop differential DC gain Bandwidth -20dB/dec Gain-bandwidth product Phase margin Equivalent input noise -40 Frequency Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 65 /76 OpAmp Performance Parameters Small signal dynamic figures (ideal): AC Bode diagram: Open loop differential DC gain Bandwidth -20dB/dec Gain-bandwidth product Phase margin Equivalent input noise -40 Common mode rejection ratio Frequency Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 66 /76 OpAmp Performance Parameters Small signal dynamic figures (ideal): AC Bode diagram: Open loop differential DC gain Bandwidth -20dB/dec Gain-bandwidth product Phase margin Equivalent input noise -40 Common mode rejection ratio Power supply rejection ratio Frequency Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 67 /76 OpAmp Performance Parameters Large signal dynamic figures (ideal) Settling time Transient step response: Amplitude independance (linear behaviour) Time Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 68 /76 OpAmp Performance Parameters Large signal dynamic figures (ideal) Settling time Transient step response: Amplitude independance (linear behaviour) Slew rate Finite power! Time Amplitude dependence (non-linear behaviour) Slope limit [V/s] Time Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 69 /76 OpAmp Performance Parameters Large signal dynamic figures (ideal) Settling time Transient harmonic response: Amplitude independance (linear behaviour) Slew rate Maximum frequency Finite power! Time Amplitude dependence (non-linear behaviour) Small/large signal boundary Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Time 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab 70 /76 OpAmp Performance Parameters Large signal dynamic figures (ideal) Transient harmonic response: Settling time Amplitude compression Slew rate Maximum frequency Total harmonic distortion Slope limitation Both static and dynamic non-linearity = signal distortion Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Time 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp OpAmp FoMs Quantitative design comparison Useful in circuit optimization: Design modification Optimization rule Electrical simulation Cost evaluation Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 71 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp Lab OpAmp FoMs Quantitative design comparison Useful in circuit optimization: Too many performance parameters! formance Per Resources Design modification Optimization rule Electrical simulation Application specific FoMs... Cost evaluation Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells 72 /76 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp 1 From the Idea to the Chip 2 Microelectronic vs Electronic Design 3 CMOS Technologies 4 Device Modeling for Analog Design 5 The Operational Amplifier and its FoMs 6 Lab Proposal Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 73 /76 Idea-Chip 1. Introduction to the Design of Analog ICs Micro-Macro CMOS My OpAmp in CNM25 V in+ + V in- - V SS V in- G T D B B V DD WINDOW B T METAL G D M4 B S POLY1 M2 M3 VIA V in+ NPLUS M1 M5 D S V SS METAL2 GASAD POLY0 NTUB p+ n+ n+ p+ p-well p+ V out Ccomp S B G M7 M8 G S 74 /76 V out Simple 2.5μm 2P2M CMOS technology (CNM25) D Lab V DD Two-stage Miller OpAmp design case B Modeling OpAmp n+ n-well Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells M6 1. Introduction to the Design of Analog ICs My OpAmp in CNM25 Two-stage Miller OpAmp design case Idea-Chip Micro-Macro CMOS Modeling OpAmp IR CM R Upper Lower OR Vof f Pd GD C CM RR D C P SRR D C SR Simple 2.5μm 2P2M CMOS technology (CNM25) ts(1%) f max TH D BW GB W φm Vnieq Area OpAmp circuit optimzation 75 /76 Initial specs Electrical simulation Choose one out of these three FoM! Lab ±σ Vin = 2.5V + − + − Vout = 2 → 3V Vout = 3 → 2V Vout = OR Vout = OR/ 2@10KHz −3dB 100Hz to 10MHz >4 <1 >3 <10 <1.5 >60 >50 >50 >50 >1.5 >1.5 <1500 <1500 <1 >1 >50 <1 <0.025 mVpp V Vpp mVrms mW dB dB dB V/ µs ns KHz % Hz MHz deg mVrms mm2 Circuit optimization Full-custom analog CMOS layout M7 M8 M1 M3 M5 M2 M4 M6 My layout Physical verification Mask design Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells My schematic 1. Introduction to the Design of Analog ICs Idea-Chip Micro-Macro CMOS Modeling OpAmp My OpAmp in CNM25 Two-stage Miller OpAmp design case Simple 2.5μm 2P2M CMOS technology (CNM25) OpAmp circuit optimzation Full-custom analog CMOS layout Freeware and multi-OS (MS Windows, Linux) EDA tools Work at home and tutorial at lab... Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells Lab 76 /76

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